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Messages from 153250

Article: 153250
Subject: Re: balancing IIR filter (after adding extra registers)
From: Mawa_fugo <ccon67@netscape.net>
Date: Wed, 18 Jan 2012 07:16:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 12, 6:49=A0am, "zak" <kazimayob2@n_o_s_p_a_m.aol.com> wrote:
> I designed a low pass IIR filter in starix iv but I got speed problem. I
> need to run it on 245MHz but can only achieve about 180. I was advised by
> experts to insert extra registers and this improved speed but the output =
of
> filter went wrong.
>
> I was advised to balance the filter since I inserted extra registers. But
> how ?
>
> I did some modeling and realized with a surprise that it seems just not
> possible that I can balance any IIR filter(but can with FIR filter).
>
> Has anybody any idea about balancing IIR filters. The difficulty is in th=
e
> feedback terms.
>
> The filter I am using is Yn =3D (1-alpha)*Xn + alpha*Yn-1
>
> Thanks in advance
>
> ---------------------------------------
> Posted throughhttp://www.FPGARelated.com

Classic problem: need for speed

* Add registers : to reduce delay due to your logic (someone's better
than others)

* Manual routing ...yeah: man vs. machine

* Split the process: if we can't do it in 254 MHz we will do it in
254/2 MHz

Article: 153251
Subject: Re: ABEL to VHDL/Verilog converter
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 18 Jan 2012 11:07:27 -0500
Links: << >>  << T >>  << A >>
KJ wrote:
> On Jan 17, 7:29 am, "ksheik.abdul"
> <ksheik.abdul@n_o_s_p_a_m.gmail.com> wrote:
>> Hi,
>>   where i can get the tool to ocnvert ABEL HDL to VHDL/verilog converter.
>>
>> Thanks & Regards,
>> sheik
>>
> 
> I haven't tried this, but Xilinx seems to support exactly what you're
> looking for.
> http://www.xilinx.com/support/answers/17000.htm
> 
> Kevin Jennings

Or for Verilog, Lattice has this:

http://www.latticesemi.com/forums/forum/messageview.cfm?catid=133&threadid=4509&enterthread=y

-- Gabor

Article: 153252
Subject: Re: VCD to power consumption trace
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 18 Jan 2012 11:19:13 -0500
Links: << >>  << T >>  << A >>
KJ wrote:
> On Jan 17, 9:36 am, Martin Klein <patrick.batema...@googlemail.com>
> wrote:
>> Hi all,
>>
>> I have captured the toggle counts of my design in a VCD file and I
>> wonder if there are now any tools available that
>> allow me to plot a nice estimate of the  dynamic power consumption of
>> my design over time. Maybe there exists a tool that also always me to
>> assign weights to the different nodes?
>>
>> Many thanks for your help!
> 
> If this is a design that is synthesized in Altera devices, then you
> would use Quartus' Power Analyzer tool.  That tool uses the VCD file
> as input and it generates an output report breaking things down by I/O
> or core, by voltage, etc.
> 
> If your design is targeting a device from some other supplier, then
> presumably they will also have a similar type of tool.
> 
> Kevin Jennings

Xpower from Xilinx does something similar, but you don't get any
indication of power as function of time.  The .vcd file is used
as a "steady state" indication of power consumption, so you only
get a single number for each type of usage representing the average
usage over the time period simulated.

I suppose you could break the vcd into time segments and run the tools
through with each segment to see how power changes over time at a
crude scale.  You might miss some narrow peaks, though.

-- Gabor

Article: 153253
Subject: Re: balancing IIR filter (after adding extra registers)
From: Tim Wescott <tim@seemywebsite.please>
Date: Wed, 18 Jan 2012 11:45:05 -0600
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2012 07:16:23 -0800, Mawa_fugo wrote:

> On Jan 12, 6:49 am, "zak" <kazimayob2@n_o_s_p_a_m.aol.com> wrote:
>> I designed a low pass IIR filter in starix iv but I got speed problem.
>> I need to run it on 245MHz but can only achieve about 180. I was
>> advised by experts to insert extra registers and this improved speed
>> but the output of filter went wrong.
>>
>> I was advised to balance the filter since I inserted extra registers.
>> But how ?
>>
>> I did some modeling and realized with a surprise that it seems just not
>> possible that I can balance any IIR filter(but can with FIR filter).
>>
>> Has anybody any idea about balancing IIR filters. The difficulty is in
>> the feedback terms.
>>
>> The filter I am using is Yn = (1-alpha)*Xn + alpha*Yn-1
>>
>> Thanks in advance
>>
>> --------------------------------------- Posted
>> throughhttp://www.FPGARelated.com
> 
> Classic problem: need for speed
> 
> * Add registers : to reduce delay due to your logic (someone's better
> than others)
> 
> * Manual routing ...yeah: man vs. machine
> 
> * Split the process: if we can't do it in 254 MHz we will do it in 254/2
> MHz

The OP understands that.  The complication is that he's trying to 
implement an IIR filter, which in its simplest form requires that you use 
data that depends on the state of a computation that is only one clock 
old.  Taken at face value, this means that you can't use pipelining.

I have offered him a couple of different suggestions on how to get around 
this problem, but he does not seem interested in them.  I'm not sure if 
he is failing to understand that they are valid solutions, or if he is 
just more comfortable moaning about the problem being "impossible" rather 
than being willing to address it as difficult.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Article: 153254
Subject: Re: balancing IIR filter (after adding extra registers)
From: davew <david.wooff@gmail.com>
Date: Wed, 18 Jan 2012 10:49:02 -0800 (PST)
Links: << >>  << T >>  << A >>
(Hi Tim,)
sorry I must admit I waded straight in myself without reading all of
the thread however:

> Let c_{n-3} = a_{n-3}, which we can do by definition because a is good at
> the beginning of the 3rd clock.
I'm not sure I follow this.  Please continue.

As we have one sample per clock cycle on a single channel stream,
x{0}, x{1}, x{2} etc. what we want is:

y{0} = A * x{-1} + B * y{-1}

But the best we can do at the desired clock rate (assuming we have a
pipeline delay of 3) is:

y{0} = A * x{-3} + B * y{-3}

Is this doable?

Article: 153255
Subject: Re: balancing IIR filter (after adding extra registers)
From: davew <david.wooff@gmail.com>
Date: Wed, 18 Jan 2012 10:53:09 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 6:49=A0pm, davew <david.wo...@gmail.com> wrote:
> (Hi Tim,)
> sorry I must admit I waded straight in myself without reading all of
> the thread however:
>
> > Let c_{n-3} =3D a_{n-3}, which we can do by definition because a is goo=
d at
> > the beginning of the 3rd clock.
>
> I'm not sure I follow this. =A0Please continue.
>
> As we have one sample per clock cycle on a single channel stream,
> x{0}, x{1}, x{2} etc. what we want is:
>
> y{0} =3D A * x{-1} + B * y{-1}
>
> But the best we can do at the desired clock rate (assuming we have a
> pipeline delay of 3) is:
>
> y{0} =3D A * x{-3} + B * y{-3}
>
> Is this doable?

Or to put it in words, if it takes 3 clocks to produce an output y
from x, but you need y on the next clock cycle to combine with the
next value of x then you simply can't have it, or can you?

Article: 153256
Subject: Re: balancing IIR filter (after adding extra registers)
From: Tim Wescott <tim@seemywebsite.please>
Date: Wed, 18 Jan 2012 23:22:28 -0600
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:

> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
>> (Hi Tim,)
>> sorry I must admit I waded straight in myself without reading all of
>> the thread however:
>>
>> > Let c_{n-3} = a_{n-3}, which we can do by definition because a is
>> > good at the beginning of the 3rd clock.
>>
>> I'm not sure I follow this.  Please continue.
>>
>> As we have one sample per clock cycle on a single channel stream, x{0},
>> x{1}, x{2} etc. what we want is:
>>
>> y{0} = A * x{-1} + B * y{-1}
>>
>> But the best we can do at the desired clock rate (assuming we have a
>> pipeline delay of 3) is:
>>
>> y{0} = A * x{-3} + B * y{-3}
>>
>> Is this doable?
> 
> Or to put it in words, if it takes 3 clocks to produce an output y from
> x, but you need y on the next clock cycle to combine with the next value
> of x then you simply can't have it, or can you?

Pretty much.

So I was trying to elucidate what you _can_ do if you have some imposed 
delay, which is to make a stable IIR filter that happens to work for 
minimum delays that are greater than 1.

There are limits, the two chief ones being bandwidth and delay.  Your 
answer is going to have some pretty healthy delays both because of the 
computation of the feedback portion of the filter (which is limited to 
delays of N or more) and the feed-forward part of your filter (which 
needs to have at least N terms if you're going to get a sensible 
frequency response).  A your bandwidth (as a proportion to your sample 
rate) that you can sensibly "ask for" gets ever narrower as your delays 
get greater (really, it's probably better to say that your bandwidth in 
real terms reaches a plateau above which it's hard to get).

In amongst all the math don't miss the point that I also made, that you 
can pre-filter with something easy like a CIC, then decimate, then either 
be done or follow that with an IIR filter.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Article: 153257
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: "SonnyAnd" <SonnyAnderson@n_o_s_p_a_m.gmx.net>
Date: Thu, 19 Jan 2012 08:36:03 -0600
Links: << >>  << T >>  << A >>
>
>"scrts" <hidden@email.com> wrote in message 
>news:jb76og$2t8$1@dont-email.me...
>>> For a perfect copy you probably going to pay 30USD
>>>
>>> Here is an example:
>>>
http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-cable-/280506472755?pt=LH_DefaultDomain_0&hash=item414f7d1933#ht_3351wt_1163
>>
>> Who cares if that cheaper one works 100% the same as original one?
>
>You should all be careful and buy one with proper antistatic protection on

>the jtag wires. Ive blown quite a few of the Altera byteblaster clones.
>
>
>

@ Petter

I bought this Digilent HS1 cable end of December and it took also some time
until I recognized their installation procedure. 
Maybe following description could help you:

After you copied all the files as it is described in Xilinx plugin
documentation, you have to go into Impact -> "cable setup", you usually
will get an error message. Now check the checkbox at "Cable plugin" and
write into the field "digilent_plugin". After you now hit ok, the Impact
software will access your JTGA-HS1 cable (which should be plugged into USB
and some device connected to it). 
On my first tries I did not really recognize that you have to write this
"string" into Impact software as I thought after plugin was installed,
Impact would recognize it itself. May it solves your question, too....

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153258
Subject: Re: balancing IIR filter (after adding extra registers)
From: Gabor <gabor@szakacs.invalid>
Date: Thu, 19 Jan 2012 10:43:22 -0500
Links: << >>  << T >>  << A >>
Tim Wescott wrote:
> On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:
> 
>> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
>>> (Hi Tim,)
>>> sorry I must admit I waded straight in myself without reading all of
>>> the thread however:
>>>
>>>> Let c_{n-3} = a_{n-3}, which we can do by definition because a is
>>>> good at the beginning of the 3rd clock.
>>> I'm not sure I follow this.  Please continue.
>>>
>>> As we have one sample per clock cycle on a single channel stream, x{0},
>>> x{1}, x{2} etc. what we want is:
>>>
>>> y{0} = A * x{-1} + B * y{-1}
>>>
>>> But the best we can do at the desired clock rate (assuming we have a
>>> pipeline delay of 3) is:
>>>
>>> y{0} = A * x{-3} + B * y{-3}
>>>
>>> Is this doable?
>> Or to put it in words, if it takes 3 clocks to produce an output y from
>> x, but you need y on the next clock cycle to combine with the next value
>> of x then you simply can't have it, or can you?
> 
> Pretty much.
> 
> So I was trying to elucidate what you _can_ do if you have some imposed 
> delay, which is to make a stable IIR filter that happens to work for 
> minimum delays that are greater than 1.
> 
> There are limits, the two chief ones being bandwidth and delay.  Your 
> answer is going to have some pretty healthy delays both because of the 
> computation of the feedback portion of the filter (which is limited to 
> delays of N or more) and the feed-forward part of your filter (which 
> needs to have at least N terms if you're going to get a sensible 
> frequency response).  A your bandwidth (as a proportion to your sample 
> rate) that you can sensibly "ask for" gets ever narrower as your delays 
> get greater (really, it's probably better to say that your bandwidth in 
> real terms reaches a plateau above which it's hard to get).
> 
> In amongst all the math don't miss the point that I also made, that you 
> can pre-filter with something easy like a CIC, then decimate, then either 
> be done or follow that with an IIR filter.
> 

From:

y{0} = A * x{-3} + B * y{-3}

A point that should not be missed is that you really have three
interleaved IIR filters each running at 1/3 the sample rate.  If
the signal bandwidth is high enough, there will be a significant
output component at 1/3 the sample rate due to this.  As a worst
case, an input with a lot of energy at 1/3 the sample rate would
be almost unfiltered.

-- Gabor

Article: 153259
Subject: Re: balancing IIR filter (after adding extra registers)
From: davew <david.wooff@gmail.com>
Date: Thu, 19 Jan 2012 08:50:13 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 19, 3:43=A0pm, Gabor <ga...@szakacs.invalid> wrote:
> Tim Wescott wrote:
> > On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:
>
> >> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
> >>> (Hi Tim,)
> >>> sorry I must admit I waded straight in myself without reading all of
> >>> the thread however:
>
> >>>> Let c_{n-3} =3D a_{n-3}, which we can do by definition because a is
> >>>> good at the beginning of the 3rd clock.
> >>> I'm not sure I follow this. =A0Please continue.
>
> >>> As we have one sample per clock cycle on a single channel stream, x{0=
},
> >>> x{1}, x{2} etc. what we want is:
>
> >>> y{0} =3D A * x{-1} + B * y{-1}
>
> >>> But the best we can do at the desired clock rate (assuming we have a
> >>> pipeline delay of 3) is:
>
> >>> y{0} =3D A * x{-3} + B * y{-3}
>
> >>> Is this doable?
> >> Or to put it in words, if it takes 3 clocks to produce an output y fro=
m
> >> x, but you need y on the next clock cycle to combine with the next val=
ue
> >> of x then you simply can't have it, or can you?
>
> > Pretty much.
>
> > So I was trying to elucidate what you _can_ do if you have some imposed
> > delay, which is to make a stable IIR filter that happens to work for
> > minimum delays that are greater than 1.
>
> > There are limits, the two chief ones being bandwidth and delay. =A0Your
> > answer is going to have some pretty healthy delays both because of the
> > computation of the feedback portion of the filter (which is limited to
> > delays of N or more) and the feed-forward part of your filter (which
> > needs to have at least N terms if you're going to get a sensible
> > frequency response). =A0A your bandwidth (as a proportion to your sampl=
e
> > rate) that you can sensibly "ask for" gets ever narrower as your delays
> > get greater (really, it's probably better to say that your bandwidth in
> > real terms reaches a plateau above which it's hard to get).
>
> > In amongst all the math don't miss the point that I also made, that you
> > can pre-filter with something easy like a CIC, then decimate, then eith=
er
> > be done or follow that with an IIR filter.
>
> From:
>
> y{0} =3D A * x{-3} + B * y{-3}
>
> A point that should not be missed is that you really have three
> interleaved IIR filters each running at 1/3 the sample rate. =A0If
> the signal bandwidth is high enough, there will be a significant
> output component at 1/3 the sample rate due to this. =A0As a worst
> case, an input with a lot of energy at 1/3 the sample rate would
> be almost unfiltered.
>
> -- Gabor

You're mixing up samples and clock cycles.

Article: 153260
Subject: Re: balancing IIR filter (after adding extra registers)
From: Tim Wescott <tim@seemywebsite.com>
Date: Thu, 19 Jan 2012 11:51:45 -0600
Links: << >>  << T >>  << A >>
On Thu, 19 Jan 2012 10:43:22 -0500, Gabor wrote:

> Tim Wescott wrote:
>> On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:
>> 
>>> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
>>>> (Hi Tim,)
>>>> sorry I must admit I waded straight in myself without reading all of
>>>> the thread however:
>>>>
>>>>> Let c_{n-3} = a_{n-3}, which we can do by definition because a is
>>>>> good at the beginning of the 3rd clock.
>>>> I'm not sure I follow this.  Please continue.
>>>>
>>>> As we have one sample per clock cycle on a single channel stream,
>>>> x{0}, x{1}, x{2} etc. what we want is:
>>>>
>>>> y{0} = A * x{-1} + B * y{-1}
>>>>
>>>> But the best we can do at the desired clock rate (assuming we have a
>>>> pipeline delay of 3) is:
>>>>
>>>> y{0} = A * x{-3} + B * y{-3}
>>>>
>>>> Is this doable?
>>> Or to put it in words, if it takes 3 clocks to produce an output y
>>> from x, but you need y on the next clock cycle to combine with the
>>> next value of x then you simply can't have it, or can you?
>> 
>> Pretty much.
>> 
>> So I was trying to elucidate what you _can_ do if you have some imposed
>> delay, which is to make a stable IIR filter that happens to work for
>> minimum delays that are greater than 1.
>> 
>> There are limits, the two chief ones being bandwidth and delay.  Your
>> answer is going to have some pretty healthy delays both because of the
>> computation of the feedback portion of the filter (which is limited to
>> delays of N or more) and the feed-forward part of your filter (which
>> needs to have at least N terms if you're going to get a sensible
>> frequency response).  A your bandwidth (as a proportion to your sample
>> rate) that you can sensibly "ask for" gets ever narrower as your delays
>> get greater (really, it's probably better to say that your bandwidth in
>> real terms reaches a plateau above which it's hard to get).
>> 
>> In amongst all the math don't miss the point that I also made, that you
>> can pre-filter with something easy like a CIC, then decimate, then
>> either be done or follow that with an IIR filter.
>> 
>> 
> From:
> 
> y{0} = A * x{-3} + B * y{-3}
> 
> A point that should not be missed is that you really have three
> interleaved IIR filters each running at 1/3 the sample rate.  If the
> signal bandwidth is high enough, there will be a significant output
> component at 1/3 the sample rate due to this.  As a worst case, an input
> with a lot of energy at 1/3 the sample rate would be almost unfiltered.

Which is why, in my original recommendation, I suggested that the filter 
be something like

y{0} = A * (x{-3} + x{-4} + x{-5}) + B * y{-3}

(Actually I left out the extra delay in the forward path in the equation, 
but mentioned it in the text -- and you may need still more).

The feedforward path then has deep nulls right at the points where the 
feedback path tends to blow up, and the overall frequency response looks 
pretty good.

I'm still not sure that -- if you're going to have a CIC filter in there 
anyway -- it isn't better to just do CIC -> decimate -> filter -> 
reconstruct if necessary.  But, the OP hasn't chimed in with much real 
information pertinent to my suggestions, so we're deep into hypothetical 
territory anyway.

-- 
What if there were no hypothetical questions?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Article: 153261
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: Thomas Entner <thomas.entner99@gmail.com>
Date: Thu, 19 Jan 2012 16:01:47 -0800 (PST)
Links: << >>  << T >>  << A >>
On 1 Dez. 2011, 16:08, "Morten Leikvoll" <mleik...@yahoo.nospam>
wrote:
> "scrts" <hid...@email.com> wrote in message
>
> news:jb76og$2t8$1@dont-email.me...
>
> >> For a perfect copy you probably going to pay 30USD
>
> >> Here is an example:
> >>http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-...
>
> > Who cares if that cheaper one works 100% the same as original one?
>
> You should all be careful and buy one with proper antistatic protection on
> the jtag wires. Ive blown quite a few of the Altera byteblaster clones.

Especially for people in Europe, our EEBlaster (http://www.entner-
electronics.com/tl/index.php/eeblaster.html) is a good option. It has
some improvements over the original USB-Blaster and costs EUR 49,-.

Regards,

Thomas

www.entner-electronics.com

Article: 153262
Subject: Compatible Altera USB Cable
From: Thomas Entner <thomas.entner99@gmail.com>
Date: Thu, 19 Jan 2012 16:11:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On 20 Jan., 01:01, Thomas Entner <thomas.entne...@gmail.com> wrote:
> On 1 Dez. 2011, 16:08, "Morten Leikvoll" <mleik...@yahoo.nospam>
> wrote:
>
> > "scrts" <hid...@email.com> wrote in message
>
> >news:jb76og$2t8$1@dont-email.me...
>
> > >> For a perfect copy you probably going to pay 30USD
>
> > >> Here is an example:
> > >>http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-...
>
> > > Who cares if that cheaper one works 100% the same as original one?
>
> > You should all be careful and buy one with proper antistatic protection on
> > the jtag wires. Ive blown quite a few of the Altera byteblaster clones.
>
> Especially for people in Europe, our EEBlaster (http://www.entner-
> electronics.com/tl/index.php/eeblaster.html) is a good option. It has
> some improvements over the original USB-Blaster and costs EUR 49,-.
>
> Regards,
>
> Thomas
>
> www.entner-electronics.com

Here is the link again:
http://www.entner-electronics.com/tl/index.php/eeblaster.html

Article: 153263
Subject: What is value of scale_sch for FFT5.0 IP core for IFFT
From: "varun_agr" <VARUN_AGR@n_o_s_p_a_m.n_o_s_p_a_m.YAHOO.COM>
Date: Fri, 20 Jan 2012 04:45:06 -0600
Links: << >>  << T >>  << A >>
We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2
burst mode,natural order,scaling(so get same o/p size as i/p size), i/p
data 8 bit and expected o/p data also 8 bit. For this we scale for FFT
in FFT5.0 IP CORE using trial method and using scale_sch="010101010101"
in this case no overflow and for scale_sch="010101010100" it is overflow
But when we give o/p of FFT to I/p of IFFT (as we want to reuse same
core) then in every scale_sch value there is no overflow. So what should
be vaule of scale_sch for IFFT. Can anybody suggest me?
Before FFT I am using 50 hz sine wave using ADC and after IFFT I am
using DAC and I want to remove all noise except 50 Hz component. Can
anybody suggest me the process after FFT.

varun	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153264
Subject: Re: Xilinx virtex-5 pitfalls
From: John Miles <jmiles@gmail.com>
Date: Fri, 20 Jan 2012 18:30:38 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 23 2011, 6:05=A0am, "Finn S. Nielsen"
<removethis_finnsta...@gmail.com> wrote:
> Hello People.
> ...
> There's also a whole story about the spartan-6. But it will be another da=
y..

I'd like to hear that one!

-- john


Article: 153265
Subject: clock enable question
From: Jim <james.knoll@gmail.com>
Date: Sat, 21 Jan 2012 11:46:05 -0800 (PST)
Links: << >>  << T >>  << A >>
I created the following clock enable block:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_enable is
    generic (
        OUTPUT_CLOCK_ENABLE_PERIOD : time;
        INPUT_CLOCK_ENABLE_PERIOD : time
    );
    port (
        clk : in  std_logic;
        reset : in  std_logic;
        enable : in  std_logic;
        clock_enable : out std_logic
    );
end clock_enable;

architecture behavioral of clock_enable is
    constant CE_CLOCK_ENABLE_TIMEOUT_COUNT : natural :=
OUTPUT_CLOCK_ENABLE_PERIOD / INPUT_CLOCK_ENABLE_PERIOD;
    signal clock_enable_i : std_logic := '0';
begin
    clock_enable <= clock_enable_i;

    pr_clock_enable_counter: process (clk, reset)
        variable v_count : natural range 0 to
CE_CLOCK_ENABLE_TIMEOUT_COUNT;
    begin
        if reset = '1' then
            clock_enable_i <= '0';
            v_count := 0;
        elsif rising_edge(clk) then
            clock_enable_i <= '0';

            if enable = '1' then
                v_count := v_count + 1;

                if v_count = CE_CLOCK_ENABLE_TIMEOUT_COUNT then
                    v_count := 0;
                    clock_enable_i <= '1';
                end if;
            end if;
        end if;
    end process pr_clock_enable_counter;
end architecture behavioral;

I am trying to use it as follows:

entity clock_enables is
    port (
        clk : in  std_logic;
        reset : in  std_logic;
        clock_enable_1_us : out std_logic;
        clock_enable_1_ms : out std_logic
    );
end clock_enables;

architecture structural of clock_enables is
    signal clock_enable_1_us_i : std_logic;
begin
    clock_enable_1_us <= clock_enable_1_us_i;

    clock_enable_1_us_component : entity work.clock_enable generic map
(
        OUTPUT_CLOCK_ENABLE_PERIOD => 1 ms,
        INPUT_CLOCK_ENABLE_PERIOD => SYSCLOCK_PERIOD
    ) port map (
        clk => clk,
        reset => reset,
        enable => '1',
        clock_enable => clock_enable_1_us_i
    );
    clock_enable_1_ms_component : entity work.clock_enable generic map
(
        OUTPUT_CLOCK_ENABLE_PERIOD => 1 ms,
        INPUT_CLOCK_ENABLE_PERIOD => 1 us
    ) port map (
        clk => clk,
        reset => reset,
        enable => clock_enable_1_us_i,
        clock_enable => clock_enable_1_ms
    );
end architecture structural;

The 1 us enable is correct, but the 1 ms clock enable that uses the 1
us clock enable is at the wrong frequency.  When I look at the
synthesis output, the same size counter (7 bits) is used for the 1 ms
clock enable as for the 1 us clock enable.  Does anyone have any ideas
what I am doing incorrectly?

Thanks,

Jim

Article: 153266
Subject: MicroBlaze MCS Error.
From: =?UTF-8?B?44OQ44K144Ot?= <basaro.k@gmail.com>
Date: Sun, 22 Jan 2012 07:01:34 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all.
I'm T.Koyama.

I download ISE 13.4 and make IP Microblze mcs.
I could make IP and bitstream,and I make ELF file under SDK
So I will download to FPGA, but Error ocuuer.

Error meaaseg is "ERROR:Data2MEM:47 - Not all BitLanes in
ADDRESS_SPACE 'mb_mcs.lmb_bram' have BMM location constraints."

Do you know What happend.

T . Koyama.

Article: 153267
Subject: Re: clock enable question
From: KJ <kkjennings@sbcglobal.net>
Date: Sun, 22 Jan 2012 12:14:56 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 21, 2:46=A0pm, Jim <james.kn...@gmail.com> wrote:

>
> The 1 us enable is correct, but the 1 ms clock enable that uses the 1
> us clock enable is at the wrong frequency. =A0When I look at the
> synthesis output, the same size counter (7 bits) is used for the 1 ms
> clock enable as for the 1 us clock enable.

Your counters are not the right size...your 1 ms counter will need to
count to 1000 so it should take 10 bits, not 8.  Since you didn't
specify what the system clock period is that drives the 1 us timer
it's not clear how many bits wide that should be.  In any case, you
should consider using a simulator to detect the cause of functional
problems, not a synthesis report.

> Does anyone have any ideas
> what I am doing incorrectly?
>

The generic that specifies the output clock period of your 1us timer
is set to 1 ms instead of 1 us.
    clock_enable_1_us_component : entity work.clock_enable generic map
(
        OUTPUT_CLOCK_ENABLE_PERIOD =3D> 1 ms,

Kevin Jennings

Article: 153268
Subject: Re: clock enable question
From: Jim <james.knoll@gmail.com>
Date: Sun, 22 Jan 2012 14:41:33 -0800 (PST)
Links: << >>  << T >>  << A >>
> The generic that specifies the output clock period of your 1us timer
> is set to 1 ms instead of 1 us.
> =A0 =A0 clock_enable_1_us_component : entity work.clock_enable generic ma=
p
> (
> =A0 =A0 =A0 =A0 OUTPUT_CLOCK_ENABLE_PERIOD =3D> 1 ms,
>
> Kevin Jennings

Thanks, Kevin.  The 1 ms was really 1 us.  I changed that while
debugging.  The 1 us component works and the module simulates
correctly for 1 us and 1 ms clock enables.  I am under the impression
that when you set the range for the natural type the correct size
logic vector will be synthesized.  Is that correct?

I changed the vhdl to pass in a generic name MAX_COUNT as a natural
and that works.  I call the module as follows:

clock_enable_1_us_component : entity work.clock_enable generic map
(
    MAX_COUNT =3D> 1 us / SYSCLOCK_PERIOD
) port map (
    clk =3D> clk,
    reset =3D> reset,
    enable =3D> '1',
    clock_enable =3D> clock_enable_1_us_i
);

clock_enable_1_ms_component : entity work.clock_enable generic map
(
    MAX_COUNT =3D> 1 ms / 1 us
) port map (
    clk =3D> clk,
    reset =3D> reset,
    enable =3D> clock_enable_1_us_i,
    clock_enable =3D> clock_enable_1_ms
);

I just don't understand why it works this way, but not the original
way.

Article: 153269
Subject: Re: clock enable question
From: KJ <kkjennings@sbcglobal.net>
Date: Sun, 22 Jan 2012 16:13:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 22, 5:41=A0pm, Jim <james.kn...@gmail.com> wrote:
> > The generic that specifies the output clock period of your 1us timer
> > is set to 1 ms instead of 1 us.
> > =A0 =A0 clock_enable_1_us_component : entity work.clock_enable generic =
map
> > (
> > =A0 =A0 =A0 =A0 OUTPUT_CLOCK_ENABLE_PERIOD =3D> 1 ms,
>
> > Kevin Jennings
>
> Thanks, Kevin. =A0The 1 ms was really 1 us. =A0I changed that while
> debugging. =A0The 1 us component works and the module simulates
> correctly for 1 us and 1 ms clock enables. =A0I am under the impression
> that when you set the range for the natural type the correct size
> logic vector will be synthesized. =A0Is that correct?

Yes.  I pass generics of type time into entities all of the time and
use them in the same fashion as you showed in your post.  It works and
using 'time' more clearly specifies the intention on the interface.
The conversion to constants happens in the architecture and is used to
define the upper end of the integer range (again same as the code you
posted).  One thing to keep in mind if you need to be as accurate as
possible is that the division of two 'time' types I don't think will
round off, instead I think it's a truncate.  In your usage this won't
be a problem, but as a general solution I have a 'round' function that
takes as input two 'times', does the division and returns an integer
(function round(A:time; B: time) return integer;)

>
> I changed the vhdl to pass in a generic name MAX_COUNT as a natural
> and that works. =A0I call the module as follows:
>
> clock_enable_1_us_component : entity work.clock_enable generic map
> (
> =A0 =A0 MAX_COUNT =3D> 1 us / SYSCLOCK_PERIOD
> ) port map (
> =A0 =A0 clk =3D> clk,
> =A0 =A0 reset =3D> reset,
> =A0 =A0 enable =3D> '1',
> =A0 =A0 clock_enable =3D> clock_enable_1_us_i
> );
>
> clock_enable_1_ms_component : entity work.clock_enable generic map
> (
> =A0 =A0 MAX_COUNT =3D> 1 ms / 1 us
> ) port map (
> =A0 =A0 clk =3D> clk,
> =A0 =A0 reset =3D> reset,
> =A0 =A0 enable =3D> clock_enable_1_us_i,
> =A0 =A0 clock_enable =3D> clock_enable_1_ms
> );
>
> I just don't understand why it works this way, but not the original
> way.

Since you said at the start of this post "The 1 ms was really 1 us.  I
changed that while debugging.", it's not clear just what is not
working and what are you actually getting when you use 'time'
generics.  Also, since you changed the code, one can't help much since
we don't know what you have.  Does it work in sim, but not in actual
hardware?  My usages of using type 'time' have been with Quartus,
maybe other tools don't handle 'time' as well.

Kevin Jennings

Article: 153270
Subject: Re: MicroBlaze MCS Error.
From: Goran_Bilski <goran.bilski@xilinx.com>
Date: Mon, 23 Jan 2012 05:18:01 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 22, 4:01=C2=A0pm, =E3=83=90=E3=82=B5=E3=83=AD <basar...@gmail.com> w=
rote:
> Hi all.
> I'm T.Koyama.
>
> I download ISE 13.4 and make IP Microblze mcs.
> I could make IP and bitstream,and I make ELF file under SDK
> So I will download to FPGA, but Error ocuuer.
>
> Error meaaseg is "ERROR:Data2MEM:47 - Not all BitLanes in
> ADDRESS_SPACE 'mb_mcs.lmb_bram' have BMM location constraints."
>
> Do you know What happend.
>
> T . Koyama.

Hi,

When you built the bitstream did you add the MicroBlaze MCS.bmm file
to the ngdbuild(translate) command?

G=C3=B6ran

Article: 153271
Subject: Semi-OT: Good Tcl Book
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Mon, 23 Jan 2012 11:36:08 -0800
Links: << >>  << T >>  << A >>
More and more I find myself needing to write Tcl.  My simulator gets far easier to work with if I've got it scripted than going clicking around.  Likewise, all of my configuration and control files under Quartus are Tcl based.

I've poked around through web reference after web reference, and managed to cobble together an approximation of an understanding of Tcl, but I still find myself spending more time playing the "Was that it?" game than I should.

Has anyone got a recommendation for a good Tcl book in dead tree form?

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 153272
Subject: Re: balancing IIR filter (after adding extra registers)
From: Gabor <gabor@szakacs.invalid>
Date: Mon, 23 Jan 2012 15:38:23 -0500
Links: << >>  << T >>  << A >>
Tim Wescott wrote:
> On Thu, 19 Jan 2012 10:43:22 -0500, Gabor wrote:
> 
>> Tim Wescott wrote:
>>> On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:
>>>
>>>> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
>>>>> (Hi Tim,)
>>>>> sorry I must admit I waded straight in myself without reading all of
>>>>> the thread however:
>>>>>
>>>>>> Let c_{n-3} = a_{n-3}, which we can do by definition because a is
>>>>>> good at the beginning of the 3rd clock.
>>>>> I'm not sure I follow this.  Please continue.
>>>>>
>>>>> As we have one sample per clock cycle on a single channel stream,
>>>>> x{0}, x{1}, x{2} etc. what we want is:
>>>>>
>>>>> y{0} = A * x{-1} + B * y{-1}
>>>>>
>>>>> But the best we can do at the desired clock rate (assuming we have a
>>>>> pipeline delay of 3) is:
>>>>>
>>>>> y{0} = A * x{-3} + B * y{-3}
>>>>>
>>>>> Is this doable?
>>>> Or to put it in words, if it takes 3 clocks to produce an output y
>>>> from x, but you need y on the next clock cycle to combine with the
>>>> next value of x then you simply can't have it, or can you?
>>> Pretty much.
>>>
>>> So I was trying to elucidate what you _can_ do if you have some imposed
>>> delay, which is to make a stable IIR filter that happens to work for
>>> minimum delays that are greater than 1.
>>>
>>> There are limits, the two chief ones being bandwidth and delay.  Your
>>> answer is going to have some pretty healthy delays both because of the
>>> computation of the feedback portion of the filter (which is limited to
>>> delays of N or more) and the feed-forward part of your filter (which
>>> needs to have at least N terms if you're going to get a sensible
>>> frequency response).  A your bandwidth (as a proportion to your sample
>>> rate) that you can sensibly "ask for" gets ever narrower as your delays
>>> get greater (really, it's probably better to say that your bandwidth in
>>> real terms reaches a plateau above which it's hard to get).
>>>
>>> In amongst all the math don't miss the point that I also made, that you
>>> can pre-filter with something easy like a CIC, then decimate, then
>>> either be done or follow that with an IIR filter.
>>>
>>>
>> From:
>>
>> y{0} = A * x{-3} + B * y{-3}
>>
>> A point that should not be missed is that you really have three
>> interleaved IIR filters each running at 1/3 the sample rate.  If the
>> signal bandwidth is high enough, there will be a significant output
>> component at 1/3 the sample rate due to this.  As a worst case, an input
>> with a lot of energy at 1/3 the sample rate would be almost unfiltered.
> 
> Which is why, in my original recommendation, I suggested that the filter 
> be something like
> 
> y{0} = A * (x{-3} + x{-4} + x{-5}) + B * y{-3}
> 
> (Actually I left out the extra delay in the forward path in the equation, 
> but mentioned it in the text -- and you may need still more).
> 
> The feedforward path then has deep nulls right at the points where the 
> feedback path tends to blow up, and the overall frequency response looks 
> pretty good.
> 
> I'm still not sure that -- if you're going to have a CIC filter in there 
> anyway -- it isn't better to just do CIC -> decimate -> filter -> 
> reconstruct if necessary.  But, the OP hasn't chimed in with much real 
> information pertinent to my suggestions, so we're deep into hypothetical 
> territory anyway.
> 

I haven't proved it to myself yet, but it seems that the idea of making
the "multiple IIR filters at a lower rate," i.e. your original equation
could be followed by a short FIR filter and end up with the same effect
as an IIR filter with just more latency.  For example the equation:

y{0} = A * x{-3} + B * y{-3}

Could be followed by a 3-term FIR filter to reconstruct the original
IIR (A and B are not the original A and B, though).

The usual reason to use IIR rather than FIR filters is that you use
a lot fewer storage elements (both for intermediate results and for
coefficients.  A FIR filter with enough terms to satisfy the required
resolution could emulate an IIR filter.  How many terms depends on the
resolution of the data and the values of A and B.  Smaller A would
result in shorter FIR filters.  Once you dump the IIR approach any
amount of pipelining can be added, as long as you have the latency
budget for it.

The last time I used an IIR filter was in a microprocessor-based LORAN
receiver, and that was just a matter of not having enough storage for
a FIR filter of reasonable length.

-- Gabor

Article: 153273
Subject: Re: Semi-OT: Good Tcl Book
From: Michael Keith <mjkeith@gmx.de>
Date: Mon, 23 Jan 2012 22:06:55 +0100
Links: << >>  << T >>  << A >>
On Mon, 23 Jan 2012 11:36:08 -0800, Rob Gaddi
<rgaddi@technologyhighland.invalid> wrote:

>More and more I find myself needing to write Tcl.  My simulator gets far easier to work with if I've got it scripted than going clicking around.  Likewise, all of my configuration and control files under Quartus are Tcl based.
>
>I've poked around through web reference after web reference, and managed to cobble together an approximation of an understanding of Tcl, but I still find myself spending more time playing the "Was that it?" game than I should.
>
>Has anyone got a recommendation for a good Tcl book in dead tree form?
Hi Rob,
Brent B. Welch: Practical Programming in Tcl and Tk
Be sure to get the latest edition (from 2010 ?) to cover the changes
up to Tcl 8.5.
IIRC the main  part of the book is about Tk, however - not
astonishing, given the simplicity of Tcl.

Not a dead tree book, but anyway: Are you aware of Tcl Tutor (links at
http://wiki.tcl.tk/1681). It's an interactive tutorial just about Tcl:
You can modify the examples any way you like, and have them execute
immediately. Highly recommended.

HTH
M.J. Keith

Article: 153274
Subject: Re: balancing IIR filter (after adding extra registers)
From: Tim Wescott <tim@seemywebsite.please>
Date: Tue, 24 Jan 2012 01:26:55 -0600
Links: << >>  << T >>  << A >>
On Mon, 23 Jan 2012 15:38:23 -0500, Gabor wrote:

> Tim Wescott wrote:
>> On Thu, 19 Jan 2012 10:43:22 -0500, Gabor wrote:
>> 
>>> Tim Wescott wrote:
>>>> On Wed, 18 Jan 2012 10:53:09 -0800, davew wrote:
>>>>
>>>>> On Jan 18, 6:49 pm, davew <david.wo...@gmail.com> wrote:
>>>>>> (Hi Tim,)
>>>>>> sorry I must admit I waded straight in myself without reading all
>>>>>> of the thread however:
>>>>>>
>>>>>>> Let c_{n-3} = a_{n-3}, which we can do by definition because a is
>>>>>>> good at the beginning of the 3rd clock.
>>>>>> I'm not sure I follow this.  Please continue.
>>>>>>
>>>>>> As we have one sample per clock cycle on a single channel stream,
>>>>>> x{0}, x{1}, x{2} etc. what we want is:
>>>>>>
>>>>>> y{0} = A * x{-1} + B * y{-1}
>>>>>>
>>>>>> But the best we can do at the desired clock rate (assuming we have
>>>>>> a pipeline delay of 3) is:
>>>>>>
>>>>>> y{0} = A * x{-3} + B * y{-3}
>>>>>>
>>>>>> Is this doable?
>>>>> Or to put it in words, if it takes 3 clocks to produce an output y
>>>>> from x, but you need y on the next clock cycle to combine with the
>>>>> next value of x then you simply can't have it, or can you?
>>>> Pretty much.
>>>>
>>>> So I was trying to elucidate what you _can_ do if you have some
>>>> imposed delay, which is to make a stable IIR filter that happens to
>>>> work for minimum delays that are greater than 1.
>>>>
>>>> There are limits, the two chief ones being bandwidth and delay.  Your
>>>> answer is going to have some pretty healthy delays both because of
>>>> the computation of the feedback portion of the filter (which is
>>>> limited to delays of N or more) and the feed-forward part of your
>>>> filter (which needs to have at least N terms if you're going to get a
>>>> sensible frequency response).  A your bandwidth (as a proportion to
>>>> your sample rate) that you can sensibly "ask for" gets ever narrower
>>>> as your delays get greater (really, it's probably better to say that
>>>> your bandwidth in real terms reaches a plateau above which it's hard
>>>> to get).
>>>>
>>>> In amongst all the math don't miss the point that I also made, that
>>>> you can pre-filter with something easy like a CIC, then decimate,
>>>> then either be done or follow that with an IIR filter.
>>>>
>>>>
>>> From:
>>>
>>> y{0} = A * x{-3} + B * y{-3}
>>>
>>> A point that should not be missed is that you really have three
>>> interleaved IIR filters each running at 1/3 the sample rate.  If the
>>> signal bandwidth is high enough, there will be a significant output
>>> component at 1/3 the sample rate due to this.  As a worst case, an
>>> input with a lot of energy at 1/3 the sample rate would be almost
>>> unfiltered.
>> 
>> Which is why, in my original recommendation, I suggested that the
>> filter be something like
>> 
>> y{0} = A * (x{-3} + x{-4} + x{-5}) + B * y{-3}
>> 
>> (Actually I left out the extra delay in the forward path in the
>> equation, but mentioned it in the text -- and you may need still more).
>> 
>> The feedforward path then has deep nulls right at the points where the
>> feedback path tends to blow up, and the overall frequency response
>> looks pretty good.
>> 
>> I'm still not sure that -- if you're going to have a CIC filter in
>> there anyway -- it isn't better to just do CIC -> decimate -> filter ->
>> reconstruct if necessary.  But, the OP hasn't chimed in with much real
>> information pertinent to my suggestions, so we're deep into
>> hypothetical territory anyway.
>> 
>> 
> I haven't proved it to myself yet, but it seems that the idea of making
> the "multiple IIR filters at a lower rate," i.e. your original equation
> could be followed by a short FIR filter and end up with the same effect
> as an IIR filter with just more latency.  For example the equation:
> 
> y{0} = A * x{-3} + B * y{-3}
> 
> Could be followed by a 3-term FIR filter to reconstruct the original IIR
> (A and B are not the original A and B, though).
> 
> The usual reason to use IIR rather than FIR filters is that you use a
> lot fewer storage elements (both for intermediate results and for
> coefficients.  A FIR filter with enough terms to satisfy the required
> resolution could emulate an IIR filter.  How many terms depends on the
> resolution of the data and the values of A and B.  Smaller A would
> result in shorter FIR filters.  Once you dump the IIR approach any
> amount of pipelining can be added, as long as you have the latency
> budget for it.
> 
> The last time I used an IIR filter was in a microprocessor-based LORAN
> receiver, and that was just a matter of not having enough storage for a
> FIR filter of reasonable length.

Well, mostly, with the exception of nit-picky little details like 
quantization noise.

The IIR portion of the filter will have three poles, at the roots of 
z^3 - B = 0; one of these is the desired one, the two will generate an 
unwanted peak at Fs/3.  Pairing that up with a FIR filter with zeros to 
match the unwanted poles will give you the effect -- assuming you have 
enough numerical precision -- of the original IIR filter you wanted.

But: the OP was just asking for a cruddy old 1st-order lowpass in the 
first place.  That's hardly ever what you really want in a signal 
processing problem, so the IIR portion followed by a four-stage CIC 
filter would be loads easier to compute (no multiplies, just an addition, 
some delays, and a subtraction), that you probably wouldn't want to go 
beyond that.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com



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