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Messages from 153100

Article: 153100
Subject: Re: Classic Disk Drive simulation and binary file IO.
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 30 Nov 2011 11:54:17 +0000
Links: << >>  << T >>  << A >>
Rob Doyle <radioengr@gmail.com> writes:

> On 11/29/2011 3:52 AM, Martin Thompson wrote:
>> You might find simulations quicker if you make the big array a variable
>> within a process rather than a signal, but if you only write to it
>> rarely, it might not make much difference.
>
> Both Xilinx ISE and GHDL hang if the 'big array' is signal.  I had to reboot the
> PC to get control back from ISE...  The mouse barely moved, the disk drive lite
> was on continuously, and I couldn't even get into Task Manager to kill ISE.  I
> manually aborted GHDL after a while.
>
> It looks like I *can* use a shared variable for the 'big array' - that
> way I can access the 'big array' from multiple processes.  Again, this
> works for both ISE and GHDL - and the performance is pretty good.
>

You are using a protected type for your shared variable aren't you?  If
not, you are asking for problems from race-conditions.  Your code below
is probably going to work alright, but it you start reading and writing
to the shared variable from multiple processes you are likely to find
life gets annoyingly interesting...

Either keep your variable to a single process and create a RAM-like
model with address and data lines and control signals, or create a
protected type with read and write functions to mediate access to it.
The latter might not work in ISE.  I think GHDL supports protected
types.

Both of those options have well-defined access semantics.

>> Finally, reading binary can be a pain in VHDL, some simulators behave
>> differently to others.  It can sometimes be easier to convert the binary
>> file to a huge list of the same numbers but rendered in ASCII.
>
> The disk image is little-endian. I read the disk image a character at
> at time and built the 16-bit "words" properly.  I believe this to be
> portable to different simulators.  The disk image, however, is probably
> not portable to big-endian systems.

One problem I have had in the past (with GHDL IIRC) was that an EOF
character within the file caused it to report end-of-file and return no
more data.  And the ISE simulator (at one point, not sure if it still
does) required a special header on binary files before it would read
them.


> I really really appreciate the assistance and good ideas from everyone.
> The PDP8 thing isn't my day job.

But fun, right :)

<snip>

> ------------------------------- simulation results -------------------
>
> $ time ghdl -r -g --workdir=work --ieee=synopsys test_disk

I'd recommend against -ieee=synopsys, especially given you are using numeric_std already.

> Reading Disk Image...
> Done Reading Disk Image.
> Read 3325952 bytes
> ----> 007F

I don't think there's any guarantee that the process which prints the 7F
will run after the file is read.  It might depend on the order the
processes come in the source file, or it might be completely random.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 153101
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 30 Nov 2011 09:40:16 -0600
Links: << >>  << T >>  << A >>

>I use Altera USB Blaster clone from eBay for ~10USD. Works perfectly: 
>drivers are exact the same as for original device, programming speed is
also 
>the same, but the best thing is that the clone is nearly 3-4 times smaller

>and has mini-USB connector.
>
>"Giuseppe Marullo" <giuseppe.marullonospam@iname.com> wrote in message 
>news:javm1e$nm0$1@speranza.aioe.org...


Actually the 10 USD USB Blaster sold at ebay are not 100% perfect copy. In
order to make a cheaper device they use a Cypress chip to emulate the
FTDI+CPLD of the USB Blaster. 

For a perfect copy you probably going to pay 30USD

Here is an example:
http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-cable-/280506472755?pt=LH_DefaultDomain_0&hash=item414f7d1933#ht_3351wt_1163

Cya	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153102
Subject: Re: Classic Disk Drive simulation and binary file IO.
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 30 Nov 2011 10:23:10 -0600
Links: << >>  << T >>  << A >>
"You are using a protected type for your shared variable aren't you?"

Clearly, he is not, he is using the VHDL-93 style of shared variable.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153103
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: "scrts" <hidden@email.com>
Date: Thu, 1 Dec 2011 08:27:40 +0200
Links: << >>  << T >>  << A >>
> For a perfect copy you probably going to pay 30USD
>
> Here is an example:
> http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-cable-/280506472755?pt=LH_DefaultDomain_0&hash=item414f7d1933#ht_3351wt_1163

Who cares if that cheaper one works 100% the same as original one? 



Article: 153104
Subject: Re: Classic Disk Drive simulation and binary file IO.
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Thu, 01 Dec 2011 11:38:04 +0000
Links: << >>  << T >>  << A >>
"RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes:

> "You are using a protected type for your shared variable aren't you?"
>
> Clearly, he is not, he is using the VHDL-93 style of shared variable.
>

Yes, I noticed the code later, but neglected to change that comment!

Sorry about that all!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 153105
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Thu, 01 Dec 2011 14:14:32 +0100
Links: << >>  << T >>  << A >>
Steve B <sbattazzo@gmail.com> writes:

> For the Digilent-specific ones, you need to install the Digilent
> Plugin for Xilinx Tools, which they kindly offer for Linux as well as
> Windows:
>
> http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN
>
> Have you done this? If not, I guess that would explain why it doesn't
> work with impact.

Thank you Steve. I was not aware that you needed a plugin. I thought
it was a Xilinx compatible cable.

However, I can not get it to work. I've downloaded the tar file and
installed the so and xml file as shown in the documentation:

ls -1  $XILINX/lib/lin64/plugins/Digilent/libCseDigilent.* | cut -c27-
v13.3i/ISE/lib/lin64/plugins/Digilent/libCseDigilent.so
v13.3i/ISE/lib/lin64/plugins/Digilent/libCseDigilent.xml

Also I would like to do this in batch mode. But I can't get it to work
in batch either. I'm uncertain about the setCable -target syntax as I
can't find any documentation other than I've have to supply
target_parameters:


>setMode -bs
>setCable -target digilent_plugin
>addDevice -p 1  -file top-par.bit
...
INFO:iMPACT - Using CseAdapterBSDevice
...
>program -p 1 -verify
ERROR:iMPACT:1075 - setCable must be set before this operation.

Any idas?

Are there anywhere I can find more detailed documentation on the
plugin mode, e.g. documentation on the API as well as documentation on
the server mode?

Also is it possible to install the plugin somewhere else and point to
it using an environment variable or similar? In some environment one
does not have write access to the ISE installation.

//Petter
-- 
.sig removed by request. 

Article: 153106
Subject: Re: Compatible Xilinx USB Cables: worth to bother?
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 1 Dec 2011 16:08:55 +0100
Links: << >>  << T >>  << A >>

"scrts" <hidden@email.com> wrote in message 
news:jb76og$2t8$1@dont-email.me...
>> For a perfect copy you probably going to pay 30USD
>>
>> Here is an example:
>> http://www.ebay.com/itm/Altera-FPGA-CPLD-USB-Blaster-programmer-JTAG-cable-/280506472755?pt=LH_DefaultDomain_0&hash=item414f7d1933#ht_3351wt_1163
>
> Who cares if that cheaper one works 100% the same as original one?

You should all be careful and buy one with proper antistatic protection on 
the jtag wires. Ive blown quite a few of the Altera byteblaster clones.



Article: 153107
Subject: Re: XC7V2000T, the perfect Thanksgiving gift
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Fri, 02 Dec 2011 07:59:11 +0100
Links: << >>  << T >>  << A >>
Hi,

Matthias Alles skrev 2011-11-28 12:24:
> Am 24.11.2011 12:33, schrieb Tim:
>> These prices come up on Avnet Express. I searched via www.findchips.com.
>>
>> Low end: XC7V2000T-1FH1761C  -  $29897.06
>> High end: XC7V2000T-G2FLG1925E  -  $67150.00
>>
>> Does that make the the XC7V2000 the most expensive "standard production"
>> chip in the history of the galaxy?
>>
>> Of course, it's probably pretty cheap in terms of transistors per
>> dollar. Heroic engineering, but I'm glad I am not a stockholder.
>
>
> Think of how much money you have to invest, in order to fill 2.4 million
> LUTs with useful logic. Then the price appears in another light.
>
> Matthias
>
>
That DĀ“depends on how you code :)

Imagine using a schematic tool and primitives only exept for a few ROMs 
for microcode THEN the V7 price becomes a bargain;)

/michael



Article: 153108
Subject: Is it possible to save the FPGA state periodically?
From: Test01 <cpandya@yahoo.com>
Date: Fri, 2 Dec 2011 09:31:56 -0800 (PST)
Links: << >>  << T >>  << A >>
Can Xilinx or Altera FPGA support scan feature to save the state?  Any
details will be great.

Article: 153109
Subject: Re: Is it possible to save the FPGA state periodically?
From: "Phil Everett" <phile@hotnots.rot>
Date: Fri, 2 Dec 2011 18:08:23 -0000
Links: << >>  << T >>  << A >>

"Test01" <cpandya@yahoo.com> wrote in message 
news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com...
> Can Xilinx or Altera FPGA support scan feature to save the state?  Any
> details will be great.

Assuming you are not using PLL's - stop the clock 



Article: 153110
Subject: Re: Is it possible to save the FPGA state periodically?
From: Test01 <cpandya@yahoo.com>
Date: Fri, 2 Dec 2011 12:07:41 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 2, 12:08=A0pm, "Phil Everett" <ph...@hotnots.rot> wrote:
> "Test01" <cpan...@yahoo.com> wrote in message
>
> news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com...
>
> > Can Xilinx or Altera FPGA support scan feature to save the state? =A0An=
y
> > details will be great.
>
> Assuming you are not using PLL's - stop the clock

But I need the ability save the state then power off the fpga board
and then restore the state at some other time.  Thus I need to store
the fpga state in flash storage device.  I was curious if the JTAG
tool that comes with the FPGA software will provide such capability.

Article: 153111
Subject: Re: Is it possible to save the FPGA state periodically?
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Fri, 2 Dec 2011 16:29:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On 2 Dez., 21:07, Test01 <cpan...@yahoo.com> wrote:
> On Dec 2, 12:08=A0pm, "Phil Everett" <ph...@hotnots.rot> wrote:
>
> > "Test01" <cpan...@yahoo.com> wrote in message
>
> >news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com..=
.
>
> > > Can Xilinx or Altera FPGA support scan feature to save the state? =A0=
Any
> > > details will be great.
>
> > Assuming you are not using PLL's - stop the clock
>
> But I need the ability save the state then power off the fpga board
> and then restore the state at some other time. =A0Thus I need to store
> the fpga state in flash storage device. =A0I was curious if the JTAG
> tool that comes with the FPGA software will provide such capability.

As far as I know there no ready to use tools that support this, but
newer xilinx part
can read out flop-flop state via the configuration port if the design
suports this. (Readback Capture)

I am not sure, but I believe that BRAM content can't be read out this
way, so you need even more application
support, such as making sure that FIFOs are emptied, caches are
invalided and other RAMs are read out by
the application before powering down.

I guess it can be done without any principal problems but will be very
challenging in practice.

Regards,

Kolja Sulimma
cronologic

Article: 153112
Subject: Re: Is it possible to save the FPGA state periodically?
From: backhus <goouse99@googlemail.com>
Date: Sun, 4 Dec 2011 22:20:22 -0800 (PST)
Links: << >>  << T >>  << A >>
On 2 Dez., 21:07, Test01 <cpan...@yahoo.com> wrote:
> On Dec 2, 12:08=A0pm, "Phil Everett" <ph...@hotnots.rot> wrote:
>
> > "Test01" <cpan...@yahoo.com> wrote in message
>
> >news:16087c47-a88a-454a-b55a-11097c206490@q30g2000yqj.googlegroups.com..=
.
>
> > > Can Xilinx or Altera FPGA support scan feature to save the state? =A0=
Any
> > > details will be great.
>
> > Assuming you are not using PLL's - stop the clock
>
> But I need the ability save the state then power off the fpga board
> and then restore the state at some other time. =A0Thus I need to store
> the fpga state in flash storage device. =A0I was curious if the JTAG
> tool that comes with the FPGA software will provide such capability.

Hi,
early Xilinx FPGA Families (X3000) had a power down feature with
battery backup.
thus the State of the FPGA is saved in itself when powering off the
board.
Since todays FPGAs are also SRAM based, it might still be possible to
to do something like that.

Have a nice synthesis
  Eilert

Article: 153113
Subject: Re: Is it possible to save the FPGA state periodically?
From: Jan Coombs <jan_2011-02@murray-microft.co.uk>
Date: Mon, 05 Dec 2011 09:13:53 +0000
Links: << >>  << T >>  << A >>
On 05/12/11 06:20, backhus wrote:
> On 2 Dez., 21:07, Test01<cpan...@yahoo.com>  wrote:

>>>> Can Xilinx or Altera FPGA support scan feature to save the state?  Any
>>>> details will be great.

> early Xilinx FPGA Families (X3000) had a power down feature with
> battery backup.
> thus the State of the FPGA is saved in itself when powering off the
> board.
> Since todays FPGAs are also SRAM based, it might still be possible to
> to do something like that.

Actel Igloo have a pin to freeze operation and maintain state at 
close to zero power.

Jan Coombs

Article: 153114
Subject: Re: Is it possible to save the FPGA state periodically?
From: Andy <jonesandy@comcast.net>
Date: Mon, 5 Dec 2011 08:22:47 -0800 (PST)
Links: << >>  << T >>  << A >>

IIRC, the ram (block and distributed) data are part of the
configuration stream. So, if your FPGA logic can store and retrieve
its state to block rams, all you have to do is store the state to
block ram and read back the configuration. Then use that configuration
(instead of the normal one) when you power back up. Naturally, your
FPGA has to be able to initialize state from rams, which  means the
original configuration needs to have the "cold reset" state data for
the rams.

Andy

Article: 153115
Subject: Re: Is it possible to save the FPGA state periodically?
From: Gabor <gabor@szakacs.invalid>
Date: Mon, 05 Dec 2011 17:00:14 -0500
Links: << >>  << T >>  << A >>
Andy wrote:
> IIRC, the ram (block and distributed) data are part of the
> configuration stream. So, if your FPGA logic can store and retrieve
> its state to block rams, all you have to do is store the state to
> block ram and read back the configuration. Then use that configuration
> (instead of the normal one) when you power back up. Naturally, your
> FPGA has to be able to initialize state from rams, which  means the
> original configuration needs to have the "cold reset" state data for
> the rams.
> 
> Andy

There was a thread on this topic in the Xilinx forums recently.  The
block RAM readback uses the same ports as your logic.  So you can't
really do it with a running design.  If you have a way to freeze the
operation (like de-asserting the global write enable), then presumably
you can do this.  There are "startup" blocks on most of the newer
devices that allow you to muck with the global signals, but you might
have other issues, not the least of which is that the global start-up
signals have significant skew over the FPGA fabric, so you might also
need to gate off your clocks.  All in all, I think this would be a
pretty ambitious project to get working.

-- Gabor

Article: 153116
Subject: Re: Is it possible to save the FPGA state periodically?
From: Andy <jonesandy@comcast.net>
Date: Tue, 6 Dec 2011 06:06:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 5, 4:00=A0pm, Gabor <ga...@szakacs.invalid> wrote:
>
> There was a thread on this topic in the Xilinx forums recently. =A0The
> block RAM readback uses the same ports as your logic. =A0So you can't
> really do it with a running design. =A0If you have a way to freeze the
> operation (like de-asserting the global write enable), then presumably
> you can do this. =A0There are "startup" blocks on most of the newer
> devices that allow you to muck with the global signals, but you might
> have other issues, not the least of which is that the global start-up
> signals have significant skew over the FPGA fabric, so you might also
> need to gate off your clocks. =A0All in all, I think this would be a
> pretty ambitious project to get working.
>
> -- Gabor

Excellent points. I took it as granted that a snapshot (to be used for
recovery) of a design would necessarily have to be taken while the
operational logic was frozen anyway, for the snapshot to have any
coherency.

Given that some portions of the FPGA would have to remain working to
transfer register contents into rams, use of a global clock/write
enable to freeze the design would not be possible. Of course those
portions used for the transfer to/from ram at shutdown/startup would
have to use conventional initialization mechanisms (reset/preset).

There would likely also be external interfaces, etc. that would need
to have special re-initialization behavior to restart communications
with external systems that may or may not have experienced the same
event.

Andy

Article: 153117
Subject: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 07 Dec 2011 08:49:06 -0800
Links: << >>  << T >>  << A >>

We are looking for simulation models for the Xilinx 7 series
FPGA PCIe core. We use Icarus Verilog models extensively, but
the models that Xilinx provides are encrypted, so locked in to
a small set of other simulators. We are hoping that we are not
the only ones with this problem and we can share simulation
models for their core.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Article: 153118
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 7 Dec 2011 09:17:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 7, 8:49=A0am, Stephen Williams <spamt...@icarus.com> wrote:
> We are looking for simulation models for the Xilinx 7 series
> FPGA PCIe core. We use Icarus Verilog models extensively, but
> the models that Xilinx provides are encrypted, so locked in to
> a small set of other simulators. We are hoping that we are not
> the only ones with this problem and we can share simulation
> models for their core.
> --
> Steve Williams =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"The woods are lovely, dark=
 and deep.
> steve at icarus.com =A0 =A0 =A0 =A0 =A0 But I have promises to keep,http:=
//www.icarus.com=A0 =A0 =A0 =A0 and lines to code before I sleep,http://www=
.picturel.com=A0 =A0 =A0 And lines to code before I sleep."

The PCIe embedded hard block is a very complicated design and the
simulation models are released as encrypted models to protect the IP.
Simulation is supported in the free Xilinx iSim simulator as well as
ModelTech and I belive VCS simulators.

There is no support for Icarus.

Ed McGettigan
--
Xilinx Inc.

Article: 153119
Subject: Horsepower On Tap
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Wed, 7 Dec 2011 17:54:56 +0000 (UTC)
Links: << >>  << T >>  << A >>
I was waiting for Quartus to finish crunching my latest build, and poking 
around idly on NewEgg trying to see what it would cost to get a machine 
with a little more juice to it.  I started thinking what a shame it was to 
have to keep upgrading to the latest and greatest machine in order to 
squeeze out some more clock cycles for big builds.  And then I started 
thinking about Amazon EC2.

The idea behind EC2 is that Amazon runs virtual machines for you, and you 
pay them by the hour for their use.  Use of an "Extra Large High-Memory 
Instance" running RHEL would run $0.63 an hour.  It's the new spin on the 
old "timeshare the supercomputer" concept.  This seems like a handy way to 
get a beast of a computer when I need to do big builds and/or long 
simulation runs without having to keep upgrading my core machine.

Has anyone tried this out to see if it works in practice?  http://
moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's 
from a year ago.  Ideally, anyone with experience trying this with Quartus, 
but ISE, Modelsim, Rivera, etc would all be interesting.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 153120
Subject: Re: Horsepower On Tap
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 07 Dec 2011 13:34:15 -0600
Links: << >>  << T >>  << A >>
On 12/07/2011 11:54 AM, Rob Gaddi wrote:
> I was waiting for Quartus to finish crunching my latest build, and poking
> around idly on NewEgg trying to see what it would cost to get a machine
> with a little more juice to it.  I started thinking what a shame it was to
> have to keep upgrading to the latest and greatest machine in order to
> squeeze out some more clock cycles for big builds.  And then I started
> thinking about Amazon EC2.
>
> The idea behind EC2 is that Amazon runs virtual machines for you, and you
> pay them by the hour for their use.  Use of an "Extra Large High-Memory
> Instance" running RHEL would run $0.63 an hour.  It's the new spin on the
> old "timeshare the supercomputer" concept.  This seems like a handy way to
> get a beast of a computer when I need to do big builds and/or long
> simulation runs without having to keep upgrading my core machine.
>
> Has anyone tried this out to see if it works in practice?  http://
> moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's
> from a year ago.  Ideally, anyone with experience trying this with Quartus,
> but ISE, Modelsim, Rivera, etc would all be interesting.
>

There certainly could be some license issues with installing software
licensed to you on a machine that is not under your control.
If you do this on a regular basis, it seems it would make more sense to
just buy a bare-bones machine with huge memory rather than go through 
all the remote setup hassles.  but, if you only do this very rarely, 
maybe it makes sense.

Jon

Article: 153121
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 07 Dec 2011 12:19:38 -0800
Links: << >>  << T >>  << A >>
On 12/07/2011 09:17 AM, Ed McGettigan wrote:
> On Dec 7, 8:49 am, Stephen Williams <spamt...@icarus.com> wrote:
>> We are looking for simulation models for the Xilinx 7 series
>> FPGA PCIe core. We use Icarus Verilog models extensively, but
>> the models that Xilinx provides are encrypted, so locked in to
>> a small set of other simulators. We are hoping that we are not
>> the only ones with this problem and we can share simulation
>> models for their core.
>> --
>> Steve Williams                "The woods are lovely, dark and deep.
>> steve at icarus.com           But I have promises to keep,http://www.icarus.com        and lines to code before I sleep,http://www.picturel.com      And lines to code before I sleep."
> 
> The PCIe embedded hard block is a very complicated design and the
> simulation models are released as encrypted models to protect the IP.
> Simulation is supported in the free Xilinx iSim simulator as well as
> ModelTech and I belive VCS simulators.
> 
> There is no support for Icarus.

That is very awkward for us since we use a fair amount of VPI
code in our system level simulations. We are basically being forced
to either come up with our own simulation of the PCIe hard core,
or port our simulation environment to a "blessed" simulator.

At one time I talked with some of your engineers about adding the
necessary encryption support into Icarus Verilog, but it was not
clear to me which encryption method you used, and whether it would
have been viable to have an open source implementation of it. I
think we concluded no.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Article: 153122
Subject: store data file in DDR2-SDRAM
From: "fifi" <ghorbel.agnes@n_o_s_p_a_m.gmail.com>
Date: Wed, 07 Dec 2011 15:24:33 -0600
Links: << >>  << T >>  << A >>
Hi

How can I load a data file to the DDR2-SDRAM. I'm use virtex 5 Ml507.
I try to download my file with the XMD but when i try to read the data I
obtained  wrong values.
Any suggestions plz 

	   
					
---------------------------------------		
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Article: 153123
Subject: DDR2 read interface
From: "Sachin" <sachins.chadha@n_o_s_p_a_m.gmail.com>
Date: Wed, 07 Dec 2011 15:25:02 -0600
Links: << >>  << T >>  << A >>
Hello,
I have a question regarding DDR2 memory controller. In a read operation
from DDR2 based on strobe, do one need to shift the strobe by 90' in order
to capture the valid data, or is there any pther way for it ?



	   
					
---------------------------------------		
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Article: 153124
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Thu, 08 Dec 2011 07:43:43 +0100
Links: << >>  << T >>  << A >>
HI,
Stephen Williams skrev 2011-12-07 21:19:
> On 12/07/2011 09:17 AM, Ed McGettigan wrote:
>> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com>  wrote:
>>> We are looking for simulation models for the Xilinx 7 series
>>> FPGA PCIe core. We use Icarus Verilog models extensively, but
>>> the models that Xilinx provides are encrypted, so locked in to
>>> a small set of other simulators. We are hoping that we are not
>>> the only ones with this problem and we can share simulation
>>> models for their core.
>>> --
>>> Steve Williams                "The woods are lovely, dark and deep.
>>> steve at icarus.com           But I have promises to keep,http://www.icarus.com        and lines to code before I sleep,http://www.picturel.com      And lines to code before I sleep."
>>
>> The PCIe embedded hard block is a very complicated design and the
>> simulation models are released as encrypted models to protect the IP.
>> Simulation is supported in the free Xilinx iSim simulator as well as
>> ModelTech and I belive VCS simulators.
>>
>> There is no support for Icarus.
>
> That is very awkward for us since we use a fair amount of VPI
> code in our system level simulations. We are basically being forced
> to either come up with our own simulation of the PCIe hard core,
> or port our simulation environment to a "blessed" simulator.
>
> At one time I talked with some of your engineers about adding the
> necessary encryption support into Icarus Verilog, but it was not
> clear to me which encryption method you used, and whether it would
> have been viable to have an open source implementation of it. I
> think we concluded no.
>
Synopsys have their own smartmodels but Xilinx moved to SecureIP for 
some reasons, more open?

http://www.xilinx.com/support/answers/33275.htm


/michael

/michael



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