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On Nov 3, 2:29=A0pm, fatalist <simfid...@gmail.com> wrote: > On Nov 3, 1:18=A0pm, brent <buleg...@columbus.rr.com> wrote: > > > > > > > > > > > On Oct 31, 12:40=A0am, Dude Whocares <ipisg...@gmail.com> wrote: > > > > US Patent 7,124,075 =93Methods and apparatus for pitch determination= =94 > > > will be auctioned as Lot 147 at the upcoming ICAP Patent Brokerage > > > Live IP Action on November 17, 2011 at The Ritz Carlton, San > > > Francisco. > > > The patent addresses a core problem of signal processing in general, > > > and speech signal processing in particular: period (fundamental > > > frequency) determination of a (quasi)-periodic signal, or pitch > > > detection problem in speech/audio signal processing. > > > Patented nonlinear signal processing techniques originate from chaos > > > theory and address known limitations of traditional linear signal > > > processing methods like FFT or correlation. > > > Patented methods are amenable to efficient implementation in both > > > software and hardware (FPGAs, ASICs). > > > Forward citations include Microsoft, Mitsubishi Space Software, > > > Broadcom, Sharp and Teradata. > > > Visit ICAP=92s website for more information:http://icappatentbrokerag= e.com/forsale > > > Ideas, it turns out, are a dime a dozen. =A0Committing to an idea and > > putting massive energy into the idea , with the realization that the > > work may not even pay off... that is where the money is (or not)- Hide = quoted text - > > > - Show quoted text - > > "Ideas" are not patentable > novel and non-obvious workable solutions to long-standing industry > problems are. > > As far as quitting your job and mortgaging your house to fully > "commit" to an "idea": you are more than welcome to do it yourself (if > your wife doesn't mind...) > > thanks but no thanks exactlyArticle: 152951
>>>> Visit ICAP’s website for more information:http://icappatentbrokerage.com/forsale Have you looked at some of the "patents" this site has for sale !!! Look at "AUC 003", this nut case was given a patent for an "Illuminated License Plate". Google "Illuminated License Plate" and you get "About 3,310,000 results (0.30 seconds)" !! But, if you Google "lighted license plates" you get "About 4,610,000 results (0.22 seconds)" !! WAIT !! You get more hits in less time for a slight difference in search parameters. What was the patent examiner thinking !! He looked out his window, saw a bunch of cars with "lighted" license plates, and said, they are not "Illuminated" license plate and decided there was no prior art. Where is it all going...... SHS (Shacking Head Slowly) hamiltonArticle: 152952
Hi, I'm looking for an FPGA-based PCI Express development board which is capable of transmitting data at about 1.4 GByte/sec to the host computer (PCIe Gen1 x8 or Gen2 x4/x8). Further considerations: 1. included IDE license 2. included PCIe IP core license, which is also valid for other designs based on the same FPGA 3. minimal HW complexity (i.e., the smaller the FPGA, the better) 4. price My current candidate is the Altera Arria II GX FPGA Development Kit (although I'm not sure if the IP core license which comes with it is not only for evaluation). http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html I would appreciate some information about your development experience with this board or other boards which satisfy the above requirements. Thank you for your time! Regards, ZsoltArticle: 152953
There are, several PCI cores on Opencores. The one used in the Ethernet NIC project is "PCI Bridge", and the core used by Anatol is "pci32tlite". The last one, is thought for simple PCI peripherals. It's small and without FIFO. >On 2011-09-27, scrts <hidden@email.com> wrote: >> "fpgaiua" <fpga@n_o_s_p_a_m.i.ua> wrote in message >> news:j-mdnQ-uufQUDx3TnZ2dnUVZ_sadnZ2d@giganews.com... >>> Good day, >>> I'm working now with Spartan3 PCI project using the pci32tlite core. >> >> Small question: is the pci core from opencores works fine? > >We used it in an Ethernet NIC project a long time ago and it worked well. >Unfortunately it had severe performance issues with repeated burst reads >and writes. The problem was that the FIFO:s in the PCI bridge didn't >implement any sort of high watermark/low watermark system. So as soon as >the FIFO was full you could only fill the FIFO with a transaction that was >one word long. At this point the performance of the system could not be >recovered if the injection rate did not decrease significantly. > >More information about our experiences can be found here: >ihttp://liu.diva-portal.org/smash/get/diva2:22746/FULLTEXT01 > >regards >/Andreas > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152954
hamilton <hamilton@nothere.com> wrote: > >What was the patent examiner thinking !! > >He looked out his window, saw a bunch of cars with "lighted" license >plates, and said, they are not "Illuminated" license plate and decided >there was no prior art. That is the basic problem with the USPTO today. There are huge numbers of patents coming in, and not a lot of money, so they hire some pretty clueless examiners. Consequently a whole lot of totally useless patents get approved, but once they get approved, they stay in the system. We have now come to a time when just having a patent is not enough to be useful because a patent is no longer automatically presumed to be valid just because it was issued. >Where is it all going...... SHS (Shacking Head Slowly) Personally, I liked the ham sandwich patent best, although Microsoft's patent on the ring buffer is even more hilarious. The software patents are really the worst, because hiring people who actually know something about the history of programming is difficult and so consequently the software examiners tend to know even less about the state of the field they are approving patents in. --scott -- "C'est un Nagra. C'est suisse, et tres, tres precis."Article: 152955
On 11/4/11 9:58 AM, Scott Dorsey wrote: > hamilton<hamilton@nothere.com> wrote: >> >> What was the patent examiner thinking !! >> >> He looked out his window, saw a bunch of cars with "lighted" license >> plates, and said, they are not "Illuminated" license plate and decided >> there was no prior art. > > That is the basic problem with the USPTO today. There are huge numbers of > patents coming in, and not a lot of money, so they hire some pretty clueless > examiners. NPR planet money did some, recent, interesting investigation into the patent world. In one segment they indicated that the patent office is one of the only government offices that operates at a net positive (bring in more money than they spend). But they are not allowed to use that money for hiring etc. They are given a fixed budget each year and the gross proceeds are used by congress for other pet projects. They eluded this is one of the problems with patent reform, because it is a source of income. .chris > > Consequently a whole lot of totally useless patents get approved, but once > they get approved, they stay in the system. We have now come to a time when > just having a patent is not enough to be useful because a patent is no longer > automatically presumed to be valid just because it was issued. > >> Where is it all going...... SHS (Shacking Head Slowly) > > Personally, I liked the ham sandwich patent best, although Microsoft's > patent on the ring buffer is even more hilarious. The software patents are > really the worst, because hiring people who actually know something about > the history of programming is difficult and so consequently the software > examiners tend to know even less about the state of the field they are > approving patents in. > --scott >Article: 152956
I'm not sure if our product Broaddown3 would worth looking at as you didn't specify other features that are needed. Broaddown3 is aimed at FPGA acceleration / HPC markets so is limited in features like I/O. We announced this product some time ago but it has something of a concept makeover so the new version is now just going into production. This board comes in a Webpack capable version using Xilinx Virtex-6 XC6VLX75T parts and this can be a single FPGA with just the PCIe and Ethernet interfaces or the full blown version with 5 Virtex-6 FPGAs. More information on this board and the other 2 new major products, Merrick3 and Lamachan2, that also launch this week, will appear on our website in the next few days. We are also hoping to be able to show all of these on our stand at SC11 in 10 days time for anyone attending that show. John Adair Enterpoint Ltd. On Nov 4, 11:15=A0am, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com> wrote: > Hi, > > I'm looking for an FPGA-based PCI Express development board which is > capable of transmitting data at about 1.4 GByte/sec to the host > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > Further considerations: > 1. included IDE license > 2. included PCIe IP core license, which is also valid for other > designs based on the same FPGA > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > 4. price > > My current candidate is the Altera Arria II GX FPGA Development Kit > (although I'm not sure if the IP core license which comes with it is > not only for evaluation).http://www.altera.com/products/devkits/altera/ki= t-aiigx-pcie.html > > I would appreciate some information about your development experience > with this board or other boards which satisfy the above requirements. > Thank you for your time! > > Regards, > ZsoltArticle: 152957
On Nov 4, 7:58=A0am, klu...@panix.com (Scott Dorsey) wrote: > hamilton =A0<hamil...@nothere.com> wrote: > > >What was the patent examiner thinking !! > > >He looked out his window, saw a bunch of cars with "lighted" license > >plates, and said, they are not "Illuminated" license plate and decided > >there was no prior art. > > That is the basic problem with the USPTO today. =A0There are huge numbers= of > patents coming in, and not a lot of money, so they hire some pretty cluel= ess > examiners. <snip> No idea if this was true but I was told that the in European system, patents are granted more as an official record of who did what when. That is, they weren't as rigorously examined as was the case for US patents prior to ~1980. The resolution of infringement was to battle it out in court using the patents as little more then official documentation. Regardless of the facts, someone somewhere apparently decided, I bet it was a lawyer, the US should adopt that model. Heck, for a lawyer it makes sense. I mean you were only getting 1/3 of all civil liability cases and OJ's Superbowl Ring. With the new system you get 1/3 of everything made sold or bartered in the US! You would be as big as the US government. RickArticle: 152958
Hi All, I am starting a new project for a software defined radio using FPGA. I plan to use simulink and HDL coder with model based design. So far I have narrowed down the hardware to cyclone II EP2C70 or Spartan-3A XC3SD3400A. Here is information I have collected: Cost: Cyclone II, board: DE2-70, $329 (education), EP2C70: 256$ or more minimum order of 1 (from Digi-key). Spartan 3A, can't find a board with XC3SD3400A. Closest one would be XtremeDSP Development platform board: 1695$ (Board only), chip $67 or more with minimum order of 84 (from Digi-key) My question is what is the true cost of Cyclone II and Spartan 3A in volume of 1000? Software: I also welcome comments on the experiences using simulink with Xilinx and Altera software. I also plan to use their Nios II or Microblaze. Any comment on the performance? Thanks a lot in advance, Everett Everett Wang Ph.D. Professor, College of Information Engineering Guangdong University of Technology Guangzhou, ChinaArticle: 152959
On 04/11/2011 11:15, zsolt.garamvolgyi wrote: > Hi, > > I'm looking for an FPGA-based PCI Express development board which is > capable of transmitting data at about 1.4 GByte/sec to the host > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > Further considerations: > 1. included IDE license > 2. included PCIe IP core license, which is also valid for other > designs based on the same FPGA > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > 4. price > > My current candidate is the Altera Arria II GX FPGA Development Kit > (although I'm not sure if the IP core license which comes with it is > not only for evaluation). > http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html > > I would appreciate some information about your development experience > with this board or other boards which satisfy the above requirements. > Thank you for your time! > > Regards, > Zsolt Look at Lattice "ECP3 VERSA DEVELOPMENT KIT" http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm $262 on their webshop. I don't know the license cost for production - you would need to check with Lattice. They say that their chips are cheaper than Alter - but you had better check that too. Michael KellettArticle: 152960
Everett Have a look at Hollybush2 http://enterpoint.co.uk/products/spartan-3-develo= pment-boards/hollybush-2/ and our XC3SD3400A Coprocessor Module http://enterpoint.co.uk/products/spartan-3-development-boards/xc3s3400a-cop= rocessor-board/ for XC3SD3400A based boards. Our Merrick1 also has this chip but it's a bit of an extreme board for your application. As to chip pricing that will vary a lot and the only way to be sure is to get pricing from your local distributor. John Adair Enterpoint Ltd. On Nov 5, 3:06=A0am, Everett <ever...@gmail.com> wrote: > Hi All, > > I am starting a new project for a software defined radio using FPGA. I > plan to use simulink and HDL coder with model based design. So far I > have narrowed down the hardware to cyclone II EP2C70 or Spartan-3A > XC3SD3400A. > > Here is information I have collected: > > Cost: > Cyclone II, =A0board: DE2-70, =A0$329 (education), =A0EP2C70: 256$ or mor= e > minimum order of 1 (from Digi-key). > > Spartan 3A, can't find a board with XC3SD3400A. Closest one would be > XtremeDSP Development platform board: 1695$ (Board only), chip $67 or > more with minimum order of 84 (from Digi-key) > > My question is what is the true cost of Cyclone II and Spartan 3A in > volume of 1000? > > Software: > I also welcome comments on the experiences using simulink with Xilinx > and Altera software. I also > plan to use their Nios II or Microblaze. Any comment on the > performance? > > Thanks a lot in advance, > > Everett > > Everett Wang Ph.D. > Professor, > College of Information Engineering > Guangdong University of Technology > Guangzhou, ChinaArticle: 152961
On nov. 4, 22:20, John Adair <g...@enterpoint.co.uk> wrote: > I'm not sure if our product Broaddown3 would worth looking at as you > didn't specify other features that are needed. Broaddown3 is aimed at > FPGA acceleration / HPC markets so is limited in features like I/O. > > We announced this product some time ago but it has something of a > concept makeover so the new version is now just going into production. > This board comes in a Webpack capable version using Xilinx Virtex-6 > XC6VLX75T parts and this can be a single FPGA with just the PCIe and > Ethernet interfaces or the full blown version with 5 Virtex-6 FPGAs. > > More information on this board and the other 2 new major products, > Merrick3 and Lamachan2, that also launch this week, will appear on our > website in the next few days. We are also hoping to be able to show > all of these on our stand at SC11 in 10 days time for anyone attending > that show. > > John Adair > Enterpoint Ltd. > > On Nov 4, 11:15=A0am, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com> > wrote: > > > > > > > > > Hi, > > > I'm looking for an FPGA-based PCI Express development board which is > > capable of transmitting data at about 1.4 GByte/sec to the host > > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > > Further considerations: > > 1. included IDE license > > 2. included PCIe IP core license, which is also valid for other > > designs based on the same FPGA > > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > > 4. price > > > My current candidate is the Altera Arria II GX FPGA Development Kit > > (although I'm not sure if the IP core license which comes with it is > > not only for evaluation).http://www.altera.com/products/devkits/altera/= kit-aiigx-pcie.html > > > I would appreciate some information about your development experience > > with this board or other boards which satisfy the above requirements. > > Thank you for your time! > > > Regards, > > Zsolt Thank you for your reply. I'll check out these boards on your website as soon as they're available. Regards, ZsoltArticle: 152962
On nov. 5, 09:36, MK <m...@nospam.co.uk> wrote: > On 04/11/2011 11:15, zsolt.garamvolgyi wrote: > > > > > > > > > > > Hi, > > > I'm looking for an FPGA-based PCI Express development board which is > > capable of transmitting data at about 1.4 GByte/sec to the host > > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > > Further considerations: > > 1. included IDE license > > 2. included PCIe IP core license, which is also valid for other > > designs based on the same FPGA > > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > > 4. price > > > My current candidate is the Altera Arria II GX FPGA Development Kit > > (although I'm not sure if the IP core license which comes with it is > > not only for evaluation). > >http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html > > > I would appreciate some information about your development experience > > with this board or other boards which satisfy the above requirements. > > Thank you for your time! > > > Regards, > > Zsolt > > Look at Lattice "ECP3 VERSA DEVELOPMENT KIT" > > http://www.latticesemi.com/products/developmenthardware/developmentki... > > $262 on their webshop. > > I don't know the license cost for production - you would need to check > with Lattice. > They say that their chips are cheaper than Alter - but you had better > check that too. > > Michael Kellett Unfortunately, this kit won't fit the throughput requirements of my design (only PCIe x1). Thank you, anyway. Regards, ZsoltArticle: 152963
On 5 Nov., 09:36, MK <m...@nospam.co.uk> wrote: > On 04/11/2011 11:15, zsolt.garamvolgyi wrote: > > > > > > > > > > > Hi, > > > I'm looking for an FPGA-based PCI Express development board which is > > capable of transmitting data at about 1.4 GByte/sec to the host > > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > > Further considerations: > > 1. included IDE license > > 2. included PCIe IP core license, which is also valid for other > > designs based on the same FPGA > > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > > 4. price > > > My current candidate is the Altera Arria II GX FPGA Development Kit > > (although I'm not sure if the IP core license which comes with it is > > not only for evaluation). > >http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html > > > I would appreciate some information about your development experience > > with this board or other boards which satisfy the above requirements. > > Thank you for your time! > > > Regards, > > Zsolt > > Look at Lattice "ECP3 VERSA DEVELOPMENT KIT" > > http://www.latticesemi.com/products/developmenthardware/developmentki... > > $262 on their webshop. That is only 1 PCIe, the OP needs 8 lanes. We have a 8x board with available soon with 4 channel 125Msps 14 Bit ADC. There is no documentation ready yet, so please contact me to discuss your detailed requirements: http://www.cronologic.de/contact/ Regards, KoljaArticle: 152964
On 11/4/2011 4:15 AM, zsolt.garamvolgyi wrote: > Hi, > > I'm looking for an FPGA-based PCI Express development board which is > capable of transmitting data at about 1.4 GByte/sec to the host > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > Further considerations: > 1. included IDE license > 2. included PCIe IP core license, which is also valid for other > designs based on the same FPGA > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > 4. price > > My current candidate is the Altera Arria II GX FPGA Development Kit > (although I'm not sure if the IP core license which comes with it is > not only for evaluation). > http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html > > I would appreciate some information about your development experience > with this board or other boards which satisfy the above requirements. > Thank you for your time! I did a project with this eval board a couple of years ago. The IP license for the PCIe core is for evaluation only, you have to keep the programmer cable connected for the core to operate. It will run for about 20 minutes (I think) after you disconnect the cable. Also, when we bought the eval kit, Altera had released a later version of the Quartus tool chain. Unfortunately, all of the example projects that were available were for the previous version of Quartus and would not build in the new version. We were on an aggressive schedule and the only option was to use the example project as a starting point and modify it for our project. It took a substantial amount of work from the Altera FAE to get their example project to build at all with the new tools. We got the project running and delivered. For a very expensive eval board ($2600 US) that was sold as a PCIe development system, I was very unimpressed with Altera's handling of this. BobHArticle: 152965
On nov. 5, 15:49, BobH <wanderingmetalhead.nospam.ple...@yahoo.com> wrote: > On 11/4/2011 4:15 AM, zsolt.garamvolgyi wrote: > > > > > > > > > > > Hi, > > > I'm looking for an FPGA-based PCI Express development board which is > > capable of transmitting data at about 1.4 GByte/sec to the host > > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > > Further considerations: > > 1. included IDE license > > 2. included PCIe IP core license, which is also valid for other > > designs based on the same FPGA > > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > > 4. price > > > My current candidate is the Altera Arria II GX FPGA Development Kit > > (although I'm not sure if the IP core license which comes with it is > > not only for evaluation). > >http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html > > > I would appreciate some information about your development experience > > with this board or other boards which satisfy the above requirements. > > Thank you for your time! > > I did a project with this eval board a couple of years ago. The IP > license for the PCIe core is for evaluation only, you have to keep the > programmer cable connected for the core to operate. It will run for > about 20 minutes (I think) after you disconnect the cable. > > Also, when we bought the eval kit, Altera had released a later version > of the Quartus tool chain. Unfortunately, all of the example projects > that were available were for the previous version of Quartus and would > not build in the new version. We were on an aggressive schedule and the > only option was to use the example project as a starting point and > modify it for our project. It took a substantial amount of work from the > Altera FAE to get their example project to build at all with the new > tools. We got the project running and delivered. For a very expensive > eval board ($2600 US) that was sold as a PCIe development system, I was > very unimpressed with Altera's handling of this. > > BobH Thank you for sharing your observations! Are you sure you've been working with the very same (Arria II GX) eval. board? The Arria II GX has a hard PCIe IP core and the documentation for the PCI Express Compiler says: "OpenCore Plus hardware evaluation is not applicable to the hard IP implementation of the IP Compiler for PCI Express. You can use the hard IP implementation of this IP core without a separate license." Can you tell me which Quartus version did you use for your project? I've been working on another PCI Express project with an Altera Stratix II GX eval. board using Quartus II 9.0 and setting up the example design was relatively painless. Unfortunately, that kit is no longer available. Regards, ZsoltArticle: 152966
On Nov 5, 5:06=A0am, Everett <ever...@gmail.com> wrote: > Hi All, > > I am starting a new project for a software defined radio using FPGA. I > plan to use simulink and HDL coder with model based design. So far I > have narrowed down the hardware to cyclone II EP2C70 or Spartan-3A > XC3SD3400A. > Why so old parts? You can get development board with 5-6 times higher DSP power (considering the differences in attainable frequency) for about the same price: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&Catego= ryNo=3D139&No=3D502 Cyclone II still may be (just may be) valuable at very low end (EP2C5 and EP2C8), but certainly not at 70K LEs size. At that size Cyclone III is plain better. Not sure how Cyclone III and Cyclone IV E compare to each other.Article: 152967
You guys missed a really great discussion today. We had to expert presenters and two representatives from the Patent Office. They discussed a lot of issues that have been raised here. I only wish I had taken better notes. I did get the chance to speak directly with Dr Lee Hollaar who spoke of several ways to deep six a patent. One is to file (free) with the patent office a notice of a publication which would represent prior art. This is attached at an application or even a granted patent. If the patent holder tries to enforce the patent by filing suit in court the lawyer would be guilty of filing not in good faith or some such legal term and would be in deep sneakers with the court. There were other things that can be done and they don't require you to be a lawyer or use one. I was very impressed with the knowledge of the presenters as well as the USPTO representatives. Probably the most useful thing that was said was that there are many views of the new law but it is the law. Those who are most aware of it and use it are the ones who will most profit. Getting an attitude about it accomplishes nothing. BTW, many of the provisions don't take effect for over a year. So it is just like an election, file early and file often! Rick On Oct 24, 3:59=A0pm, rickman <gnu...@gmail.com> wrote: > Co-sponsored by > IEEE NCA Consultants Network, > Baltimore Consultants Network, > Society on Social Implications of Technology, > Baltimore and NoVA/Wash. Computer Society, > and Region 2 PACE Committee > > Congress has enacted sweeping patent reform that is adverse to small > inventors and entrepreneurs. How will this affect you? Let=92s explore > what the future holds with our panel of experts. Lunch and networking > reception are included. Student members may bring a guest at no > additional cost. Door prizes! Additional details at the link below. > > When: Saturday, November 5 10am-2pm > > Where: Loyola University Graduate Centers Room 260 > 8890 McGaw Road Columbia, MD 21045 USA > > Cost: $10 IEEE members (advance), $20 general > > Web Page:www.ieee-consultants.org > > Registration:http://meetings.vtools.ieee.org/meeting_view/list_meeting/87= 71 > > Panelists: Dr. Lee Hollaar, Dr. Amelia Morani > > We are still looking for a panelist who is a consultant able to speak > regarding the impact of this new law. =A0Anyone available in the area?Article: 152968
On 11/5/2011 9:18 AM, zsolt.garamvolgyi wrote: > On nov. 5, 15:49, BobH<wanderingmetalhead.nospam.ple...@yahoo.com> > wrote: >> On 11/4/2011 4:15 AM, zsolt.garamvolgyi wrote: >>> Hi, >> >>> I'm looking for an FPGA-based PCI Express development board which is >>> capable of transmitting data at about 1.4 GByte/sec to the host >>> computer (PCIe Gen1 x8 or Gen2 x4/x8). >> >>> Further considerations: >>> 1. included IDE license >>> 2. included PCIe IP core license, which is also valid for other >>> designs based on the same FPGA >>> 3. minimal HW complexity (i.e., the smaller the FPGA, the better) >>> 4. price >> >>> My current candidate is the Altera Arria II GX FPGA Development Kit >>> (although I'm not sure if the IP core license which comes with it is >>> not only for evaluation). >>> http://www.altera.com/products/devkits/altera/kit-aiigx-pcie.html >> >>> I would appreciate some information about your development experience >>> with this board or other boards which satisfy the above requirements. >>> Thank you for your time! >> >> I did a project with this eval board a couple of years ago. The IP >> license for the PCIe core is for evaluation only, you have to keep the >> programmer cable connected for the core to operate. It will run for >> about 20 minutes (I think) after you disconnect the cable. >> >> Also, when we bought the eval kit, Altera had released a later version >> of the Quartus tool chain. Unfortunately, all of the example projects >> that were available were for the previous version of Quartus and would >> not build in the new version. We were on an aggressive schedule and the >> only option was to use the example project as a starting point and >> modify it for our project. It took a substantial amount of work from the >> Altera FAE to get their example project to build at all with the new >> tools. We got the project running and delivered. For a very expensive >> eval board ($2600 US) that was sold as a PCIe development system, I was >> very unimpressed with Altera's handling of this. >> >> BobH > > Thank you for sharing your observations! > > Are you sure you've been working with the very same (Arria II GX) > eval. board? The Arria II GX has a hard PCIe IP core and the > documentation for the PCI Express Compiler says: > > "OpenCore Plus hardware evaluation is not applicable to the hard IP > implementation > of the IP Compiler for PCI Express. You can use the hard IP > implementation of this IP > core without a separate license." > > Can you tell me which Quartus version did you use for your project? > I've been working on another PCI Express project with an Altera > Stratix II GX eval. board using Quartus II 9.0 and setting up the > example design was relatively painless. Unfortunately, that kit is no > longer available. You are correct, it was the Stratix II GX with the PCIe soft core. This project was done in the spring of 2009 and my memory is not great. I have changed jobs and have been working with Xilinx mostly in my new role. I think, and I am not sure on this, but I think that the Quartus transition was 8.x to 9.0. Once the correct IP was obtained, the project went OK, but the demo project for the 8.x would not function with the 9.0 Quartus without significant thrashing. The demo stuff that shipped with the kit was definitely for the older version. Sorry for the confusion, BobHArticle: 152969
On Nov 4, 1:15=A0pm, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com> wrote: > Hi, > > I'm looking for an FPGA-based PCI Express development board which is > capable of transmitting data at about 1.4 GByte/sec to the host > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > Further considerations: > 1. included IDE license > 2. included PCIe IP core license, which is also valid for other > designs based on the same FPGA > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > 4. price > > My current candidate is the Altera Arria II GX FPGA Development Kit > (although I'm not sure if the IP core license which comes with it is > not only for evaluation).http://www.altera.com/products/devkits/altera/ki= t-aiigx-pcie.html > > I would appreciate some information about your development experience > with this board or other boards which satisfy the above requirements. > Thank you for your time! > > Regards, > Zsolt In our experience Altera's hard IP PCIe core present in StratixIV GX and in ArriaII GX is broken rather badly. That is, you can find certain hosts where it appears to work most of the time, but that's exception rather than rule. Soft IP core in these devices works relatively better, but still badly violates power up timing specifications defined in the PCIe standard, so we generally prefer to plug it into slots that support hot plug, since such slots are typically more tolerant to this sort of timing violations. Unfortunately for you, you want x8 slot. x8 slots with support for hot plug are significantly rarer than x4/x1 slots. Overall, if you decided to go with Altera, the most robust combination is old StatixII GX + soft PCIe core + Quartus 9.1 Sp1 or Sp2. BTW, even on x8 Gen1, hitting 1.4 GB/s in the read direction will be very very hard (but it sounds like you don't need it). Hitting 1.4 GB/ s in in write direction is significantly easier, but still non- trivial, esp. if you want to work with default 256B packets size.Article: 152970
On Sat, 5 Nov 2011 16:46:03 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >You guys missed a really great discussion today. We had to expert >presenters and two representatives from the Patent Office. They >discussed a lot of issues that have been raised here. I only wish I >had taken better notes. I did get the chance to speak directly with >Dr Lee Hollaar who spoke of several ways to deep six a patent. One is >to file (free) with the patent office a notice of a publication which >would represent prior art. This is attached at an application or even >a granted patent. If the patent holder tries to enforce the patent by >filing suit in court the lawyer would be guilty of filing not in good >faith or some such legal term and would be in deep sneakers with the >court. There were other things that can be done and they don't >require you to be a lawyer or use one. > >I was very impressed with the knowledge of the presenters as well as >the USPTO representatives. Probably the most useful thing that was >said was that there are many views of the new law but it is the law. >Those who are most aware of it and use it are the ones who will most >profit. Getting an attitude about it accomplishes nothing. > >BTW, many of the provisions don't take effect for over a year. So it >is just like an election, file early and file often! > >Rick Thanks for the update. I wish I could have been there. Regarding the ability for the public to file prior art notice of publication, was there any discussion about how that is checked or processed? What's to stop someone from filing something only marginally related as "prior art" to be attached to a patent? Sounds like a strategy that could be used by someone nefariously trying to kill a good patent. Eric Jacobsen Anchor Hill Communications www.anchorhill.comArticle: 152971
On Nov 5, 12:21=A0am, Rick <richardcort...@gmail.com> wrote: > On Nov 4, 7:58=A0am, klu...@panix.com (Scott Dorsey) wrote:> hamilton =A0= <hamil...@nothere.com> wrote: > > > >What was the patent examiner thinking !! > > > >He looked out his window, saw a bunch of cars with "lighted" license > > >plates, and said, they are not "Illuminated" license plate and decided > > >there was no prior art. > > > That is the basic problem with the USPTO today. =A0There are huge numbe= rs of > > patents coming in, and not a lot of money, so they hire some pretty clu= eless > > examiners. > > <snip> > > No idea if this was true but I was told that the in European system, > patents are granted more as an official record of who did what when. > That is, they weren't as rigorously examined as was the case for US > patents prior to ~1980. The resolution of infringement was to battle > it out in court using the patents as little more then official > documentation. > > Regardless of the facts, someone somewhere apparently decided, I bet > it was a lawyer, the US should adopt that model. Heck, for a lawyer it > makes sense. I mean you were only getting 1/3 of all civil liability > cases and OJ's Superbowl Ring. With the new system you get 1/3 of > everything made sold or bartered in the US! You would be as big as the > US government. > > Rick The EPO has been created in 1973... And since then, although it may not be perfect (I'm sure you could find "stupid" grants at the EPO too), the quality of search reports and legal certainty of granted patents is generally recognised. Back to the origin of this thread, I'd advise a potential buyer to read the EPO search report beforehand...Article: 152972
On Nov 6, 1:10=A0pm, Michael S <already5cho...@yahoo.com> wrote: > On Nov 4, 1:15=A0pm, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com> > wrote: > > > > > > > > > > > Hi, > > > I'm looking for an FPGA-based PCI Express development board which is > > capable of transmitting data at about 1.4 GByte/sec to the host > > computer (PCIe Gen1 x8 or Gen2 x4/x8). > > > Further considerations: > > 1. included IDE license > > 2. included PCIe IP core license, which is also valid for other > > designs based on the same FPGA > > 3. minimal HW complexity (i.e., the smaller the FPGA, the better) > > 4. price > > > My current candidate is the Altera Arria II GX FPGA Development Kit > > (although I'm not sure if the IP core license which comes with it is > > not only for evaluation).http://www.altera.com/products/devkits/altera/= kit-aiigx-pcie.html > > > I would appreciate some information about your development experience > > with this board or other boards which satisfy the above requirements. > > Thank you for your time! > > > Regards, > > Zsolt > > In our experience Altera's hard IP PCIe core present in StratixIV GX > and in ArriaII GX is broken rather badly. > That is, you can find certain hosts where it appears to work most of > the time, but that's exception rather than rule. > Soft IP core in these devices works relatively better, but still badly > violates power up timing specifications defined in the PCIe standard, > so we generally prefer to plug it into slots that support hot plug, > since such slots are typically more tolerant to this sort of timing > violations. Unfortunately for you, you want x8 slot. x8 slots with > support for hot plug are significantly rarer than x4/x1 slots. > This is really interesting. Can you tell me, exactly which hosts (if any) did you manage to get the hard IP core work with correctly? > Overall, if you decided to go with Altera, the most robust combination > is old StatixII GX + soft PCIe core + Quartus 9.1 Sp1 or Sp2. > I would prefer using an Altera device as I have more experience with their design tools. As the Stratix II GX board is obsolete, I think I could use the Arria II GX board with the soft IP core, too, with the drawbacks of additional license cost and FPGA resource usage. The Arria II GX + hard IP combination is quite compelling (at least on paper). Do you have experience with other vendors' PCIe boards/IP cores? Is there a more robust solution available? > BTW, even on x8 Gen1, hitting 1.4 GB/s =A0in the read direction will be > very very hard =A0(but it sounds like you don't need it). Hitting 1.4 GB/ > s in =A0in write direction is significantly easier, but still non- > trivial, esp. if you want to work with default 256B packets size. Yes, I'm aware of these limitations, but 1. downstream data transfer is not a concern, 2. 1.4 GB/s is an absolute worst case data rate estimation, and most probably will be relaxed in the final specification. It's not impossible that even a PCIe x4 board will fit the requirements. Regards, ZsoltArticle: 152973
I still have that Stratix II GX PCI-e development kit, but the FPGA doesn't have hard PCI-e block, even if there are 4 lanes of the bus, so the core is instantiated as software mode PCI-e. If the author is interested in Stratix II GX, I am ready for negotiations :) > Can you tell me which Quartus version did you use for your project? > I've been working on another PCI Express project with an Altera > Stratix II GX eval. board using Quartus II 9.0 and setting up the > example design was relatively painless. Unfortunately, that kit is no > longer available.Article: 152974
>I still have that Stratix II GX PCI-e development kit, but the FPGA doesn't > have hard PCI-e block, even if there are 4 lanes of the bus, so the core > is instantiated as software mode PCI-e. If the author is interested in > Stratix II GX, I am ready for negotiations :) Oh my bad, it's x8, not x4. The board I have is this one: http://www.altera.com/products/devkits/altera/kit-pciexpress_s2gx.html
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