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HI, Rob Gaddi skrev 2011-12-07 18:54: > I was waiting for Quartus to finish crunching my latest build, and poking > around idly on NewEgg trying to see what it would cost to get a machine > with a little more juice to it. I started thinking what a shame it was to > have to keep upgrading to the latest and greatest machine in order to > squeeze out some more clock cycles for big builds. And then I started > thinking about Amazon EC2. > > The idea behind EC2 is that Amazon runs virtual machines for you, and you > pay them by the hour for their use. Use of an "Extra Large High-Memory > Instance" running RHEL would run $0.63 an hour. It's the new spin on the > old "timeshare the supercomputer" concept. This seems like a handy way to > get a beast of a computer when I need to do big builds and/or long > simulation runs without having to keep upgrading my core machine. > > Has anyone tried this out to see if it works in practice? http:// > moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's > from a year ago. Ideally, anyone with experience trying this with Quartus, > but ISE, Modelsim, Rivera, etc would all be interesting. > Sun tried that for a number of years ago in their huge build/simulation center, but I think it failed when you need licensed software. /michaelArticle: 153126
>Hello, >I have a question regarding DDR2 memory controller. In a read operation >from DDR2 based on strobe, do one need to shift the strobe by 90' in order >to capture the valid data, or is there any pther way for it ? > The optimal phase shift will depend on the 2-way track delay between the Controller IC (e.g. your FPGA) and the SDRAM (clock out, data back). Taking the DDR2 SDRAM Controllers generated by the Xilinx MIG tool as an example, they go through a training period working out the best phase shift relative to the FPGA-internal clock to sample the read data. Alternatively, you could route the SDRAM clock back to the FPGA, and use that. Neither is easy. Therefore use your FPGA vendor's IP if at all possible. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153127
On 12/7/2011 11:54 AM, Rob Gaddi wrote: > I was waiting for Quartus to finish crunching my latest build, and poking > around idly on NewEgg trying to see what it would cost to get a machine > with a little more juice to it. I started thinking what a shame it was to > have to keep upgrading to the latest and greatest machine in order to > squeeze out some more clock cycles for big builds. And then I started > thinking about Amazon EC2. > > The idea behind EC2 is that Amazon runs virtual machines for you, and you > pay them by the hour for their use. Use of an "Extra Large High-Memory > Instance" running RHEL would run $0.63 an hour. It's the new spin on the > old "timeshare the supercomputer" concept. This seems like a handy way to > get a beast of a computer when I need to do big builds and/or long > simulation runs without having to keep upgrading my core machine. > > Has anyone tried this out to see if it works in practice? http:// > moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's > from a year ago. Ideally, anyone with experience trying this with Quartus, > but ISE, Modelsim, Rivera, etc would all be interesting. > You can provide some feedback here, http://bit.ly/rFONhB, that you would like cloud FPGA P&R.Article: 153128
On Dec 7, 10:43=A0pm, Michael Laajanen <michael_laaja...@yahoo.com> wrote: > HI, > Stephen Williams skrev 2011-12-07 21:19: > > > > > On 12/07/2011 09:17 AM, Ed McGettigan wrote: > >> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com> =A0wrote: > >>> We are looking for simulation models for the Xilinx 7 series > >>> FPGA PCIe core. We use Icarus Verilog models extensively, but > >>> the models that Xilinx provides are encrypted, so locked in to > >>> a small set of other simulators. We are hoping that we are not > >>> the only ones with this problem and we can share simulation > >>> models for their core. > >>> -- > >>> Steve Williams =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"The woods are lovely, = dark and deep. > >>> steve at icarus.com =A0 =A0 =A0 =A0 =A0 But I have promises to keep,h= ttp://www.icarus.com=A0 =A0 =A0 =A0and lines to code before I sleep,http://= www.picturel.com=A0 =A0 =A0And lines to code before I sleep." > > >> The PCIe embedded hard block is a very complicated design and the > >> simulation models are released as encrypted models to protect the IP. > >> Simulation is supported in the free Xilinx iSim simulator as well as > >> ModelTech and I belive VCS simulators. > > >> There is no support for Icarus. > > > That is very awkward for us since we use a fair amount of VPI > > code in our system level simulations. We are basically being forced > > to either come up with our own simulation of the PCIe hard core, > > or port our simulation environment to a "blessed" simulator. > > > At one time I talked with some of your engineers about adding the > > necessary encryption support into Icarus Verilog, but it was not > > clear to me which encryption method you used, and whether it would > > have been viable to have an open source implementation of it. I > > think we concluded no. > > Synopsys have their own smartmodels but Xilinx moved to SecureIP for > some reasons, more open? > > http://www.xilinx.com/support/answers/33275.htm > > /michael > > /michael- Hide quoted text - > > - Show quoted text - Move away from SmartModels was primarily due to a lack of continuing support from Synopsys for the latest OS and simulator versions. The SecureIP models are supported in a wide range of simulators as the answer record shows. Ed McGettigan -- Xilinx Inc.Article: 153129
Hi, Rob Gaddi skrev 2011-12-07 18:54: > I was waiting for Quartus to finish crunching my latest build, and poking > around idly on NewEgg trying to see what it would cost to get a machine > with a little more juice to it. I started thinking what a shame it was to > have to keep upgrading to the latest and greatest machine in order to > squeeze out some more clock cycles for big builds. And then I started > thinking about Amazon EC2. > > The idea behind EC2 is that Amazon runs virtual machines for you, and you > pay them by the hour for their use. Use of an "Extra Large High-Memory > Instance" running RHEL would run $0.63 an hour. It's the new spin on the > old "timeshare the supercomputer" concept. This seems like a handy way to > get a beast of a computer when I need to do big builds and/or long > simulation runs without having to keep upgrading my core machine. > > Has anyone tried this out to see if it works in practice? http:// > moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's > from a year ago. Ideally, anyone with experience trying this with Quartus, > but ISE, Modelsim, Rivera, etc would all be interesting. > One other drawback is that you will have to pay per P&R or simulation run, this was how it was in the minicomputer era(VAX and more) then came Unix workstations suddenly you did not have to think about the cost for a simulation run it was your own desktop workstation. No, I think flatrate(you pay for your own box and run) is best, you will not have flat rate in a elastic clound :) You can pay on demand for licenses but that is not nice either! Just my experiences /michaelArticle: 153130
Hi, Ed McGettigan skrev 2011-12-08 17:26: > On Dec 7, 10:43 pm, Michael Laajanen<michael_laaja...@yahoo.com> > wrote: >> HI, >> Stephen Williams skrev 2011-12-07 21:19: >> >> >> >>> On 12/07/2011 09:17 AM, Ed McGettigan wrote: >>>> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com> wrote: >>>>> We are looking for simulation models for the Xilinx 7 series >>>>> FPGA PCIe core. We use Icarus Verilog models extensively, but >>>>> the models that Xilinx provides are encrypted, so locked in to >>>>> a small set of other simulators. We are hoping that we are not >>>>> the only ones with this problem and we can share simulation >>>>> models for their core. >>>>> -- >>>>> Steve Williams "The woods are lovely, dark and deep. >>>>> steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep." >> >>>> The PCIe embedded hard block is a very complicated design and the >>>> simulation models are released as encrypted models to protect the IP. >>>> Simulation is supported in the free Xilinx iSim simulator as well as >>>> ModelTech and I belive VCS simulators. >> >>>> There is no support for Icarus. >> >>> That is very awkward for us since we use a fair amount of VPI >>> code in our system level simulations. We are basically being forced >>> to either come up with our own simulation of the PCIe hard core, >>> or port our simulation environment to a "blessed" simulator. >> >>> At one time I talked with some of your engineers about adding the >>> necessary encryption support into Icarus Verilog, but it was not >>> clear to me which encryption method you used, and whether it would >>> have been viable to have an open source implementation of it. I >>> think we concluded no. >> >> Synopsys have their own smartmodels but Xilinx moved to SecureIP for >> some reasons, more open? >> >> http://www.xilinx.com/support/answers/33275.htm >> >> /michael >> >> /michael- Hide quoted text - >> >> - Show quoted text - > > Move away from SmartModels was primarily due to a lack of continuing > support from Synopsys for the latest OS and simulator versions. > > The SecureIP models are supported in a wide range of simulators as the > answer record shows. > > Ed McGettigan > -- > Xilinx Inc. Speaking of Synopsys, since they now since a couple of years fully supports Solaris on x64 has Xilinx any plans/discussions about that to? /michaelArticle: 153131
On Dec 8, 9:54=A0am, Michael Laajanen <michael_laaja...@yahoo.com> wrote: > Hi, > Ed McGettigan skrev 2011-12-08 17:26: > > > > > On Dec 7, 10:43 pm, Michael Laajanen<michael_laaja...@yahoo.com> > > wrote: > >> HI, > >> Stephen Williams skrev 2011-12-07 21:19: > > >>> On 12/07/2011 09:17 AM, Ed McGettigan wrote: > >>>> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com> =A0 =A0wrot= e: > >>>>> We are looking for simulation models for the Xilinx 7 series > >>>>> FPGA PCIe core. We use Icarus Verilog models extensively, but > >>>>> the models that Xilinx provides are encrypted, so locked in to > >>>>> a small set of other simulators. We are hoping that we are not > >>>>> the only ones with this problem and we can share simulation > >>>>> models for their core. > >>>>> -- > >>>>> Steve Williams =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"The woods are lovely= , dark and deep. > >>>>> steve at icarus.com =A0 =A0 =A0 =A0 =A0 But I have promises to keep= ,http://www.icarus.com=A0 =A0 =A0 and lines to code before I sleep,http://w= ww.picturel.com=A0 =A0 And lines to code before I sleep." > > >>>> The PCIe embedded hard block is a very complicated design and the > >>>> simulation models are released as encrypted models to protect the IP= . > >>>> Simulation is supported in the free Xilinx iSim simulator as well as > >>>> ModelTech and I belive VCS simulators. > > >>>> There is no support for Icarus. > > >>> That is very awkward for us since we use a fair amount of VPI > >>> code in our system level simulations. We are basically being forced > >>> to either come up with our own simulation of the PCIe hard core, > >>> or port our simulation environment to a "blessed" simulator. > > >>> At one time I talked with some of your engineers about adding the > >>> necessary encryption support into Icarus Verilog, but it was not > >>> clear to me which encryption method you used, and whether it would > >>> have been viable to have an open source implementation of it. I > >>> think we concluded no. > > >> Synopsys have their own smartmodels but Xilinx moved to SecureIP for > >> some reasons, more open? > > >>http://www.xilinx.com/support/answers/33275.htm > > >> /michael > > >> /michael- Hide quoted text - > > >> - Show quoted text - > > > Move away from SmartModels was primarily due to a lack of continuing > > support from Synopsys for the latest OS and simulator versions. > > > The SecureIP models are supported in a wide range of simulators as the > > answer record shows. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Speaking of Synopsys, since they now since a couple of years fully > supports Solaris on x64 has Xilinx any plans/discussions about that to? > > /michael- Hide quoted text - > > - Show quoted text - Support for operating systems beyond Linux and Windows are not on our product roadmaps. Ed McGettigan -- Xilinx Inc.Article: 153132
Wasn't there a short lived push by EDA companies about 10 years ago to provide internet services in which the number crunching was done by their server while you entered and submitted your design using their software? I seem to remember that it was back in the day when we paid huge amounts of money for complete design and build tools and did it all ourselves. It was the pay as you go model. Perhaps the need has resurfaced. It seems to me if you can get a build 10 times faster for a buck or two a run, it'll be cost effective. JJS "Rob Gaddi" wrote in message news:jbo99g$652$1@dont-email.me... I was waiting for Quartus to finish crunching my latest build, and poking around idly on NewEgg trying to see what it would cost to get a machine with a little more juice to it. I started thinking what a shame it was to have to keep upgrading to the latest and greatest machine in order to squeeze out some more clock cycles for big builds. And then I started thinking about Amazon EC2. The idea behind EC2 is that Amazon runs virtual machines for you, and you pay them by the hour for their use. Use of an "Extra Large High-Memory Instance" running RHEL would run $0.63 an hour. It's the new spin on the old "timeshare the supercomputer" concept. This seems like a handy way to get a beast of a computer when I need to do big builds and/or long simulation runs without having to keep upgrading my core machine. Has anyone tried this out to see if it works in practice? http:// moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's from a year ago. Ideally, anyone with experience trying this with Quartus, but ISE, Modelsim, Rivera, etc would all be interesting. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 153133
>Wasn't there a short lived push by EDA companies about 10 years ago to >provide internet services in which the number crunching was done by their >server while you entered and submitted your design using their software? I >seem to remember that it was back in the day when we paid huge amounts of >money for complete design and build tools and did it all ourselves. It was >the pay as you go model. Perhaps the need has resurfaced. It seems to me if >you can get a build 10 times faster for a buck or two a run, it'll be cost >effective. > >JJS > > Yes, It ended when all of their customers told them that they would would never let them see any of their IP. The problem with running in the cloud is that they have to create a image and run it with root access open to the world so that the customer can control it. Well so can anyone else who can guess it's password. It's really nice if root has to be sitting by the box in order to get it. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153134
Hi, jt_eaton skrev 2011-12-09 05:46: >> Wasn't there a short lived push by EDA companies about 10 years ago to >> provide internet services in which the number crunching was done by their > >> server while you entered and submitted your design using their software? > I >> seem to remember that it was back in the day when we paid huge amounts of > >> money for complete design and build tools and did it all ourselves. It > was >> the pay as you go model. Perhaps the need has resurfaced. It seems to me > if >> you can get a build 10 times faster for a buck or two a run, it'll be cost > >> effective. >> >> JJS >> >> > > Yes, It ended when all of their customers told them that they would would > never let them see any of their IP. > > The problem with running in the cloud is that they have to create a image > and > run it with root access open to the world so that the customer can control > it. > > Well so can anyone else who can guess it's password. It's really nice if > root > has to be sitting by the box in order to get it. > > > John Eaton > That you dont have to do, why do you say so? /michaelArticle: 153135
HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My customer has given me the following requirements: Carrier board has 144 bidirectional signals configurable as both LVDS xmitters and LVDS receivers. They want to loop back 72 signals as Soource synch. xmitters tied to the other 72 as receivers.Then they want to flip the whole works and flow the data in the opposite direction to validate that all signals will function both as receivers or transmitters. Unfortunately this thing needs to operate at 1.6Ghz clock rate. Flipping the direction must be done via signal, since I cant touch the board because it will be in an environmental chamber. Also making 2 versions to cover both directions is undesirable. Other encouraging goodies: 1) I can not use an FPGA. 2) This thing has to fit on a 2.4 * 2.7 inch board 3) the signals already have to go thru a connector and have stubs, some as long as 16mm on the carrier side. so I'm looking to keep any stubs down. Ive been looking at Crosspoint switches but am concerned that I really should reclock the data, not just hope the cross point switch cleans it up. Any Ideas (any) are greatly appreciated. Thanks Folks; C.W. ThomasArticle: 153136
I think this will be one of the more significant semiconductor acquisitions of the year. http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-siliconblue-62-million I've been using Lattice parts for the last few years and I plan to be using SiBlue parts this coming year. I see that a SiBlue part is being used in a watch by Citizen. http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--First-FPGA-in-a-watch- I believe the ultimate market for FPGAs will be low cost, high volume devices like this. Sooner or later this low power technology will be combined with the analog functionality of the Cypress and Actel devices. RickArticle: 153137
On Dec 10, 1:30=A0pm, rickman <gnu...@gmail.com> wrote: > I think this will be one of the more significant semiconductor > acquisitions of the year. > > http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-silic... > > I've been using Lattice parts for the last few years and I plan to be > using SiBlue parts this coming year. > > I see that a SiBlue part is being used in a watch by Citizen. > > http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--F... > > I believe the ultimate market for FPGAs will be low cost, high volume > devices like this. =A0Sooner or later this low power technology will be > combined with the analog functionality of the Cypress and Actel > devices. > > Rick Certainly an Interesting move. Lattice have been slow releasing their MachXO2 family, and have just added one MLF package. Their smallest MachXO2 BGA package certainly indicates a small die, so we would like to see more MLF packages. Prices indicated on the smaller siblings of the MachXo2 are also higher than the Logic ratio would infer Could take a while to merge the two offerings, and quite a but of overlap. -jgArticle: 153138
On Dec 10, 12:15=A0am, Jim Granville <j.m.granvi...@gmail.com> wrote: > On Dec 10, 1:30=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > > > > > > > I think this will be one of the more significant semiconductor > > acquisitions of the year. > > >http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-silic... > > > I've been using Lattice parts for the last few years and I plan to be > > using SiBlue parts this coming year. > > > I see that a SiBlue part is being used in a watch by Citizen. > > >http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--F... > > > I believe the ultimate market for FPGAs will be low cost, high volume > > devices like this. =A0Sooner or later this low power technology will be > > combined with the analog functionality of the Cypress and Actel > > devices. > > > Rick > > Certainly an Interesting move. > Lattice have been slow releasing their MachXO2 family, and have just > added one MLF package. > Their smallest MachXO2 BGA package certainly indicates a small die, so > we would like to see more MLF packages. > Prices indicated on the smaller siblings of the MachXo2 are also > higher than the Logic ratio would infer > > Could take a while to merge the two offerings, and quite a but of > overlap. > > -jg I don't expect they will push to merge product lines. Those products were conceived as viable products competing with the market as a whole and I expect they will continue them as such. I guess you are really suggesting that the next generation might be a combined family combining the best features of each. That may be. I don't know what compromises SiBlue had to make to get the low power. I know their part is ram backed up with one time programmable memory rather than flash. That certainly has good utility, but flash is always better. Any board I design with the SiBlue part will have an SPI flash on it while my designs with the Lattice XP parts don't. Otherwise I don't know what shortcomings the SiBlue parts have. RickArticle: 153139
Sorry for the naive question, but how do I capture a schematic with a D and J-K FF that do have negated Q? I tried to draw the schematic with WebISE 13.3 and there is not such a thing readily available. TIA. Giuseppe MarulloArticle: 153140
> >1) I can not use an FPGA. > Then this thread is completely Off-Topic! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153141
You might be more likely to get an answer if you post this question at the Xilinx forums, for example: http://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153142
On Dec 12, 3:32=A0am, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Sorry for the naive question, but how do I capture a schematic with a D > and J-K FF that do have negated Q? I tried to draw the schematic with > WebISE 13.3 and there is not such a thing readily available. > TIA. > > Giuseppe Marullo Use an inverter on the clock net. It will get absorbed into the FFs. AndyArticle: 153143
Hi, Giuseppe Marullo skrev 2011-12-12 10:32: > Sorry for the naive question, but how do I capture a schematic with a D > and J-K FF that do have negated Q? I tried to draw the schematic with > WebISE 13.3 and there is not such a thing readily available. > TIA. > > Giuseppe Marullo When you run P&R the optimizing will reduce your design whenever possible. Check the output of the build process and see what it says. Or make a very tiny design then you can see in fpga_editor what the P&R did do. /michaelArticle: 153144
On Dec 12, 6:51=A0am, Andy <jonesa...@comcast.net> wrote: > On Dec 12, 3:32=A0am, Giuseppe Marullo > > <giuseppe.marullonos...@iname.com> wrote: > > Sorry for the naive question, but how do I capture a schematic with a D > > and J-K FF that do have negated Q? I tried to draw the schematic with > > WebISE 13.3 and there is not such a thing readily available. > > TIA. > > > Giuseppe Marullo > > Use an inverter on the clock net. It will get absorbed into the FFs. > > Andy The OP asked for a "negated Q", which I would interpert as being an invertor on the Q output and not on the CLK input. Ed McGettigan -- Xilinx Inc.Article: 153145
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: (snip, someone wrote) >> Use an inverter on the clock net. It will get absorbed into the FFs. > The OP asked for a "negated Q", which I would interpert as being an > invertor on the Q output and not on the CLK input. In any case, the inverter should be absorbed where possible, and included elsewhere. In the TTL days, it was usual for FF's to have Q and Qbar outputs, with no extra inverter delay in the Qbar case. But even more, the OP didn't ask about the logic, but how to draw it. (Even though I don't especially like schematic capture.) I suppose the schematic capture tools could add a Qbar output and generate an inverter. Maybe they allow for inverting outputs by adding circles. It is a tools question, not a logic question. -- glenArticle: 153146
> adding circles. It is a tools question, not a logic question. > > -- glen Glen, exactly. I need to do the capture thing because it is not so trivial to convert the schematic into verilog at first glance, and the FF uses both Q and Qbar. I was thinking it was a fault from my understanding of the tool, but qbar are missing on all FF i found in the tool. The other way would it be to write a custom block where inside a verilog would implement the desired FF but maybe there is a simpler way. Giuseppe MarulloArticle: 153147
On 12/12/2011 12:45 PM, RCIngham wrote: > You might be more likely to get an answer if you post this question at the > Xilinx forums, for example: > http://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD Touche! I have posted the same question there.Article: 153148
On 12/12/2011 04:31 PM, Giuseppe Marullo wrote: >> adding circles. It is a tools question, not a logic question. >> >> -- glen > Glen, exactly. I need to do the capture thing because it is not so > trivial to convert the schematic into verilog at first glance, and the > FF uses both Q and Qbar. I was thinking it was a fault from my > understanding of the tool, but qbar are missing on all FF i found in the > tool. > > The other way would it be to write a custom block where inside a verilog > would implement the desired FF but maybe there is a simpler way. > > Giuseppe Marullo > If you are going to be using schematic entry, then it is quite easy to build all the primitives you need out of simpler primitives and make a custom library of them. I still do this on some CPLD interface projects where simple definitions in schematic form are more concise. I build N-way tristate buffers and tristate FFs and such that way. JonArticle: 153149
Giuseppe Marullo <giuseppe.marullonospam@iname.com> wrote: >> adding circles. It is a tools question, not a logic question. > Glen, exactly. I need to do the capture thing because it is not so > trivial to convert the schematic into verilog at first glance, and the > FF uses both Q and Qbar. Personally, I think I can write verilog faster than I can get the lines drawn for schematic capture, but others may be different. > I was thinking it was a fault from my understanding of the tool, > but qbar are missing on all FF i found in the tool. For FPGAs, inverters will usually be moved into the logic before or after, changing bits in the appropriate LUT. So no delay difference. That wasn't true in TTL. So, now the reason for them is gone, and the tools don't support them. > The other way would it be to write a custom block where inside a verilog > would implement the desired FF but maybe there is a simpler way. On some, you can draw your own symbol, including the circles. -- glen
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