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Messages from 105575

Article: 105575
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 26 Jul 2006 15:27:20 +0200
Links: << >>  << T >>  << A >>
Jim Granville schrieb:

>>>> With MHz to burn, and FPGA, why not use a
>>>> Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking
>>>> Up/down coounter on the index.
>>>> It can be 100% digital, and the tracking speed becomes the PLL-LPF.

This is what the 74xx297 is doing with a minimum logic count.

> Measure 50Hz (half?) period. appx 50KHz timebase resolves to 0.1%
> eg gets 20.2ms : Trim and Scale the result, into a lookup table, that

Why so shy? Why not using a "true high speed" clock (like the 30 MHz) to 
measure the (half)period? Also, 0.1% is not very accurate for a clock 
(yeah, yeah I know, we have a new result after every cycle).

> then loads the 2KHz divider.
> ( Suppose you target improve of +/- 1% to +/- 0.1%, that is a ~20 entry 
> table.
> 
> Keeping to 0.1%, 2KHz to 0.1% is 2MHz Clock, with ~1000 divider values.
> 
> Table/ROM has 20 entries, of 11 bit binary values.
> 
> Each new cycle uses the last cycles period, to get a best fit of 40 
> '2Khz' clocks.
> 
>  Tracking counter Method :
> Count the 2KHz clocks you actually get, in a 50Hz period.
> 
>  For 2KHz, create an 11 bit Divider(from 2MHz), fed from an 11 bit Up/Dn 
> counter.
>  If the Counts_2Khz is ABOVE 40, then Increment the Up/Dn counter, if it
> is BELOW 40, decrement the Up/Dn counter.
> ( for higher precision, you might count higher in the divider than 2Khz 
> - you have not given desired jitter/precision values )

Sounds very much like 74xx297.

> Most main systems will reset/load the 2KHz on zero cross, to phase lock
> that. You also want to freqency lock, to have a known phase stepping.

I always wonder how people distinuish between a PLL (PHASE lock) and so 
called FLL (Frequeny lock).
My humble opinion is, that it is nonsense to seperarte phase lock from 
frequncy lock, since they are mathematical the integral/deviation of 
each other.

Regards
Falk

Article: 105576
Subject: Re: Virtex 4 ACE Compact Flash configuration problem
From: "EEngineer" <maricic@gmail.com>
Date: 26 Jul 2006 06:38:15 -0700
Links: << >>  << T >>  << A >>
IOs on the parallel port are TTL and 3.3V should be enough for
receiveing according to TTL specs?

Ed McGettigan wrote:
> EEngineer wrote:
> > Finally after two weeks I have configured the board for the first time.
> > I was misled that software update was performed every time I start the
> > ISE with WebUpdate, but that was not the case - after you mentioned SP
> > (it was not the one for Windows XP) I went to the update section of the
> > web site and installed SP 3. I am able to generate ACE files that work.
> >
> > Can I interface the board's J6 header single ended  signal connections
> > with the parallel port on the PC with no buffer and what constrains
> > should be asserted for those pins?
> >
>
> I'm glad that you are moving forward with your design work.
>
> On the second item the answer is no as a parallel port is 5V and the
> IOs on the headers are 2.5V (or 3.3V if you move a jumper).
> 
> Ed McGettigan
> --
> Xilinx Inc.


Article: 105577
Subject: Re: How to phase align a 10MHz clock using V4LX60 DCM
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 26 Jul 2006 06:38:57 -0700
Links: << >>  << T >>  << A >>

Gabor wrote:
> When you multiply a clock and then divide it, there is no common
> phase relationship of the output unless you reference the original
> signal.  I would suggest sampling the input clock using a flip-flop
> clocked by the 10x clock.  The output of this flip-flop should have
> a constant (somewhat delayed) phase relationship to the original.
> Additional 10x clock delays can then be added to adjust the clock
> to the desired phase.
>
>
Hi I am Subins collegue,
  What we are trying to do is advance the input clock by 4 to 6 ns not
to delay it.


Article: 105578
Subject: Re: Virtex 4 ACE Compact Flash configuration problem
From: "EEngineer" <maricic@gmail.com>
Date: 26 Jul 2006 06:41:02 -0700
Links: << >>  << T >>  << A >>
I have just received USB platform cable, (I ordered it as I was not
sure if I was going to be able to program the board with CF), is it
possible to write and read the fpga IOs through it. In that case I
would not need a parallel port to interface it?

Dan

Ed McGettigan wrote:
> EEngineer wrote:
> > Finally after two weeks I have configured the board for the first time.
> > I was misled that software update was performed every time I start the
> > ISE with WebUpdate, but that was not the case - after you mentioned SP
> > (it was not the one for Windows XP) I went to the update section of the
> > web site and installed SP 3. I am able to generate ACE files that work.
> >
> > Can I interface the board's J6 header single ended  signal connections
> > with the parallel port on the PC with no buffer and what constrains
> > should be asserted for those pins?
> >
>
> I'm glad that you are moving forward with your design work.
>
> On the second item the answer is no as a parallel port is 5V and the
> IOs on the headers are 2.5V (or 3.3V if you move a jumper).
> 
> Ed McGettigan
> --
> Xilinx Inc.


Article: 105579
Subject: Re: Spartan 3 clock to output tristate timing
From: "Symon" <symon_brewer@hotmail.com>
Date: 26 Jul 2006 15:54:23 +0200
Links: << >>  << T >>  << A >>
Hi Rick,
I agree with Rob, it sounds as though the FPGA supervisor should be asking 
you what to put in the UCF file. And it should be something involving 
'OFFSET'. In between browsing monster.com, have a look in the Xilinx 
constraints guide and read up on the OFFSET constraint. I think it's what 
you're looking for.
Yours &c, Syms.



Article: 105580
Subject: Re: How to phase align a 10MHz clock using V4LX60 DCM
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Wed, 26 Jul 2006 15:03:40 +0100
Links: << >>  << T >>  << A >>
vssumesh wrote:

>Gabor wrote:
>  
>
>>When you multiply a clock and then divide it, there is no common
>>phase relationship of the output unless you reference the original
>>signal.  I would suggest sampling the input clock using a flip-flop
>>clocked by the 10x clock.  The output of this flip-flop should have
>>a constant (somewhat delayed) phase relationship to the original.
>>Additional 10x clock delays can then be added to adjust the clock
>>to the desired phase.
>>
>>
>>    
>>
>Hi I am Subins collegue,
>  What we are trying to do is advance the input clock by 4 to 6 ns not
>to delay it.
>
>  
>
pretty much the same thing, if you are considering that the delayed 
version, it's an "early" version against the next transition..., 
otherwise just wait for soeone to invent a time machine.
Aurash

-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 105581
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: panteltje@yahoo.com
Date: 26 Jul 2006 07:29:49 -0700
Links: << >>  << T >>  << A >>

Falk Brunner schreef:


> I always wonder how people distinuish between a PLL (PHASE lock) and so
> called FLL (Frequeny lock).
> My humble opinion is, that it is nonsense to seperarte phase lock from
> frequncy lock, since they are mathematical the integral/deviation of
> each other.
>
> Regards
> Falk


Maybe because if your watch runs the same speed as mine, but 10 seconds
late,
it is in frequency lock, but not phase lock.
In 'phase lock' some edge of one signal should be very accurately
aligned with
some edge of an other.

You can do it both with a 'phase comparator', but there is more to it.
Sometimes systems are used that first use a wide bandwidth to lock in
[frequency], then switch to (or switch in) a higher gain narrow
bandwidth phase loop.
This in case mechanical servos for example [for] video head placement.
Sometimes multiple stages are used to get ever better precision.


Article: 105582
Subject: Re: Spartan 3 clock to output tristate timing
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 26 Jul 2006 14:47:39 GMT
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> wrote:

>I've got a problem at work where the FPGA group is at war with the
>hardware group and I am sick and tired of ducking the punches.  I
>designed the board although there was not a lot of original design.  I
>was told what main chips to use since they had done a similar design
>before.  So I pretty much copied the design which uses an XC3S400-4 and
>a TMS320VC5510 with a combined SRAM/Flash chip.  I am being asked for a
>proper bus timing analysis and I need the data on the FPGA.  That is
>where the punches start flying!

Can't you shove the whole problem upwards? And see what is falling
down again? It seems to me you'll need to know how the FPGA's IOBs are
used in order to know what timing to expect. 

However, based on your statement that the clock period is approx 10ns,
they must have used the flipflops inside the IOB. Each IOB has 6
flipflops. 2 to control the output enable, 2 to control the output and
2 to capture the input. The reason why there are 2 flipflops for each
function is to be able to use the IOB at double datarate (DDR). The
flipflops can be programmed so that one will act on the rising edges
and the other one will act on the falling edges.

The timing path from these flipflops to the actual pin is well
documented. However, you'll still need to know whether they switched
IOB_DELAY on or off for the input path.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 105583
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: "RobJ" <rob@abc.net>
Date: Wed, 26 Jul 2006 14:56:30 GMT
Links: << >>  << T >>  << A >>
"raso" <rasit.sahin@yahoo.co.uk> wrote in message 
news:1153838749.560177.182570@b28g2000cwb.googlegroups.com...
> Dear Jan,
>
> This part is not a problem at all.
>
> What I need to do is to keep the number of 2Khz pulses
> same as the main 50Hz changes. In perfect condition
> there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
> When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
> chance accordingly to stay in lock.
>
> My system clock is 60MHz. I implemented a JK phase detector, a
> K-counter and a DCO in order to generate 2KHz pulses and this system
> operates at system clock. The
> output locks to exact 50Hz very quickly (fed from signal generator),
> but when I change the reference clock to, lets say, 50.1Hz it starts
> drifting.
>
> Any help appreciated.
>
> Many thanks,
> Rasit
>

I don't know all of your requirements, but something I've done before to 
multiply a slow "clock" like this is to measure each cycle of the slow clock 
with a much faster reference clock (60MHz in your case) and use the 
measurement to generate the multiplied clock until the next measurement is 
available. For your application this would mean measuring each 50Hz 
(nominally) cycle time in 60MHz ticks (just use a counter). Then divide that 
measurement result by 40 (easy with shifts and adds) to set the period of 
your 2kHz clock until the next measurement. The measurement is updated each 
50Hz cycle, so the 2kHz clock will always track. The only nasty is that you 
will have to stretch or shrink the last 2kHz period as the 50Hz period 
measurement is updated. If you can tolerate this jitter then this is 
probably the easiest way to generate the locked 2kHz.

A variation of this would be to accumulate several 50Hz period measurements 
and average them to smooth things out. If you do need a PLL, with a 60MHz 
clock available you should not have to (or want to) use any analog loop 
filtering. All digital is the way to go. Or better yet, put the loop filter 
in software if you have a processor available.

Good luck.

Rob 



Article: 105584
Subject: Re: Hardware book like "Code Complete"?
From: "Andy" <jonesandy@comcast.net>
Date: 26 Jul 2006 07:59:02 -0700
Links: << >>  << T >>  << A >>
Of course there are multiple functionally equivalent methods (i.e. they
synthesize to the same hardware) of describing a given architecture,
but some methods (e.g. using integers, variables and clocked processes,
while minimizing slv, signals, combinatorial processes and concurrent
assignments) simulate much more efficiently (approaching cycle based
performance) than others.  The more clock cycles I can simulate, the
more bugs I can find, and the more quickly I can verify alternate
architectures. It may not make a big difference on small projects, but
on larger projects, the performance difference is huge.

Andy

KJ wrote:
> Andy wrote:
> > Yes, but...
> >
> > Assuming the signals that those concurrent assignments depend on are
> > driven from clocked processes, they do not update until after the
> > clock, which means they are the registered (delayed) values.
>
> So what?  I typically don't care about waiting a delta cycle delay,
> when you put them up on a wave window to debug they all happen at the
> same time.
>
> <snip>
> > Note that both out1 and out2 have the same cycle-accurate behavior.
> > Note also that if both out1 and out2 exist, Synplify will combine them
> > and use out1 for both.
>
> And this can be written in a functionally equivalent manner using a
> process and concurrent assignments and it will synthesize to the exact
> same thing....equivalent.
> 
> KJ


Article: 105585
Subject: Re: Virtex 4 ACE Compact Flash configuration problem
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 26 Jul 2006 08:19:12 -0700
Links: << >>  << T >>  << A >>
EEngineer wrote:
> I have just received USB platform cable, (I ordered it as I was not
> sure if I was going to be able to program the board with CF), is it
> possible to write and read the fpga IOs through it. In that case I
> would not need a parallel port to interface it?
> 

Go and download an evaluation version of ChipScope Pro
http://www.xilinx.com/chipscope and try out the Virtual I/O (VIO)
core to handle your communication needs.  You can set this up to
support many inputs and outputs into your design and in the GUI
you can group the signals in to buses with different radix types
including, binary, octal, hex, integer (with scaling factors), leds,
push buttons, toggle buttons and pulse chains for easy visuals.

The VIO core works well for limited data transfers, but if you need
more than try out the logic analyzer (ILA) core.  This will work
will for capturing large amounts of data.

Ed McGettigan
--
Xilinx Inc.

Article: 105586
Subject: Re: An idea for a product (FPGA/ASIC based)
From: "Brannon" <brannonking@yahoo.com>
Date: 26 Jul 2006 08:36:15 -0700
Links: << >>  << T >>  << A >>
> Just curious: How would one connect two PCIe 4x ports in one card?
>
> Or would PICe 8x (or PCI 16x) be a better way to go?

Last I checked, you couldn't just buy an PCIe 8x controller chip. For
example, the Dini board ( http://www.dinigroup.com/DN8000k10pcie-8.php
) has two 4-lane PHYs and they expect all the DMA logic to be coded in
the connecting chip (using cores from
http://www.asic-architectinc.com).

I don't understand what is so hard about building an 8-lane PHY with a
DMA channel for each lane and putting it all in a little chip that
comes with some nice driver code base for the host machine and LVDS
output on the far end. I guess that's asking too much. (But it has been
done for PCI...)


Article: 105587
Subject: Re: An idea for a product (FPGA/ASIC based)
From: "Brannon" <brannonking@yahoo.com>
Date: 26 Jul 2006 08:44:10 -0700
Links: << >>  << T >>  << A >>
> Fully custom encoders are incredibly complex beasts - professional ones
> often have tens of DSP's and FPGA's on board.
>
> I think a board which accelerated motion estimation and left residual
> coding (and thus the rate distortion optimisation process and the
> majority of differences between codec standards) up to the CPU would be
> a reasonable solution.

I fully agree. The existing boards are too complex because they do too
much. This is where "reconfigurable" computing really comes into play.
Consider JPEG: you can first configure the board to do DCT. Then you
stream all your data through on a high speed connection and get your
DCT'd code back into host memory. Then you configure the board to do
quantization and Z-ordering, then run the huffman analysis on the host
machine, then configure the board to do bit packing load it with the
new huffman codes, etc. Most people that do huffman encoding in FPGA
just use predetermined lookup tables because to do a full huffman
analysis requires some significant DSP code. Don't code that in FPGA!
Use the FPGA for what it is good at (i.e., pipelined DCT).


Article: 105588
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 26 Jul 2006 18:03:25 +0200
Links: << >>  << T >>  << A >>
raso schrieb:
> Hi Jon,
> 
> Falk Brunner sent me his VHDL implementation of 74LS297. I modified it
> so that K-counter and I/D counter (DCO) run at system clock which is
> 30MHz.

Wasn't it already this way?

> The system has following blocks;
> 
> - The first component is an JKFF based phase detector.
> - Then, there is a K-counter operating at 30MHz. With 30MHz clock, a
> full 50Hz
> period means M=30e6/50=600000 ticks. For minimum jitter, modulus of K
> counter is set M/2 which is 300000. The borrow pulse decreases the
> modulus of I/D counter (2KHz DCO) while carry pulse increases it by 1.
> So in locked condition, it generates 1 carry and 1 borrow pulse within
> one 50Hz period and they cancel each other.
> - I/D counter is a DCO (modulus counter). It operates  at 30MHz. When
> it is locked to 50Hz it has modulus of 15000. When 50Hz changes, the
> borrow and carry pulses should adjust the modulus of I/D counter (carry
> pulse increases the modulus by 1, and borrow decreases it by 1). By
> this way, period of 2kHz pulses is adjusted according to 50Hz input.
> - N-Counter which devides 2Khz clock by 40.
> 
> The only parameter that I can play with is the modulus of K counter.

More or less. Wait a tick. Look at the data sheet of the 74xx297, it 
says the lock range (pull range) of the PLL is

delta_f_max = fc * M / (2*K*N )

using your values

delta_f_max = 50 Hz * 600000 / (2* 300000 * 40) = 1.25 Hz

Hmm, this should be enought.

> I can't use direct implementation of 74LS297. Because, it syncronises
> f_in and f_out by inserting or deleting 2KHz pulses (I/D pulses). I

This is not true. It inserts master clock cycles, in your case, 30 MHz 
clocks. Which are 1/3000 of a 2 kHz period.

> can't tolerate inserting or deleting 2KHz pulses. It has to keep the
> number of 2kHz pulses as 40 in each 50Hz period.

Sure, otherwise you couldnt call it PLL ;-)

Regards
Falk

Article: 105589
Subject: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
From: "Nevo" <nevo_n@hotmail.com>
Date: 26 Jul 2006 09:04:40 -0700
Links: << >>  << T >>  << A >>
GaLaKtIkUs=99 wrote:
> Hi Per Jensen,
> All the schematics are converted to VHDL or Verilog (look at the
> source's properties dialog).
> You can see the generated HDL code by double-clicking the "View HDL
> functional model" in the "Design Utilities" in the process window.
> To add an instance of a schematic to an HDL code double-click on "View
> HDL instantiation tamplate" in the "Design Utilities" in the process
> window, copy, paste and modify the code to the destination module
> (verilog) or architecture (VHDL).
> To add an instance of a schematic to another schematic: close all
> schematic windows, in the processes window double-click the process
> "generate schematic symbol" in the "Design Utilities". than open a
> schematics and in the categories window there will be a new category
> with the path of your project as the name, enter this category and
> choose the needed generted by you symbol.
>
> I hope that this helped!
>

GaLaKtIkUs,

I am trying to do exactly that! I have created a schematic in Xilinx
WebPack 8.2 that I want to use as a building block in another
schematic.

However, I have these two schematics in separate projects.

How do I import my building block into my larger project?
Can I create a symbol library of my building blocks?

Any assistance you could provide this newbie would be very much
appreciated.

Thanks,

-Nevo


Article: 105590
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 26 Jul 2006 18:10:05 +0200
Links: << >>  << T >>  << A >>
panteltje@yahoo.com schrieb:

> Maybe because if your watch runs the same speed as mine, but 10 seconds
> late,
> it is in frequency lock, but not phase lock.
> In 'phase lock' some edge of one signal should be very accurately
> aligned with
> some edge of an other.

Got your point, but I still think the problem (mine?) is the uncertainty 
in language. Sounds like the common latch/flipflop mixup.

Regards
Falk

Article: 105591
Subject: Re: An idea for a product (FPGA/ASIC based)
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 26 Jul 2006 09:20:13 -0700
Links: << >>  << T >>  << A >>
Hi Brannon,
Can you explain further about a full huffman analysis for JPEG?

I have no any knowledge about JPEG and what books you recommend about
the topics?

Weng

Brannon wrote:
> > Fully custom encoders are incredibly complex beasts - professional ones
> > often have tens of DSP's and FPGA's on board.
> >
> > I think a board which accelerated motion estimation and left residual
> > coding (and thus the rate distortion optimisation process and the
> > majority of differences between codec standards) up to the CPU would be
> > a reasonable solution.
>
> I fully agree. The existing boards are too complex because they do too
> much. This is where "reconfigurable" computing really comes into play.
> Consider JPEG: you can first configure the board to do DCT. Then you
> stream all your data through on a high speed connection and get your
> DCT'd code back into host memory. Then you configure the board to do
> quantization and Z-ordering, then run the huffman analysis on the host
> machine, then configure the board to do bit packing load it with the
> new huffman codes, etc. Most people that do huffman encoding in FPGA
> just use predetermined lookup tables because to do a full huffman
> analysis requires some significant DSP code. Don't code that in FPGA!
> Use the FPGA for what it is good at (i.e., pipelined DCT).


Article: 105592
Subject: Re: uClinux on Virtex-4 Mini-Module
From: "Guru" <ales.gorkic@email.si>
Date: 26 Jul 2006 11:02:26 -0700
Links: << >>  << T >>  << A >>
Antti,

You are probably trying to say: buy hydraXC module and you will get a
fully configurable MB-uClinux and PPC-linux.
VMWare probably means that I can compile the OS using Windows and linux
in a virtual machine.
What about the memory management in PPC-linux?
What can the PPC-linux do besides networking (multithreading...)?
Is the GSRD2 LL_TEMAC driver included? If not, can I use the linux
driver made for normal linux (MV or tarball 2.16.)?

Cheers,

Guru



Antti wrote:
> Guru schrieb:
>
> > Antti,
> >
> > I can see you are personally involved in development, that's why you
> > have good info on this matter.
> > The modules look VERY good (full of features), only the price bothers
> > me.
> > I cannot move to another platform right now, because my hardware is
> > designed for Mini-Module.
> > I guess I will have to implement the PPC-uClinux by myself :(
> >
> > Cheers,
> >
> > Guru
>
> read what I wrote - PPC-linux (not uClinux) image is 1.3MB only
> so it would work on V4MM also.
>
> all hydraXC-xx modules come with support DVD that includes VMWare
> preconfigured environments so building a new MB-uclinux or PPC-linux
> kernel for the hydraXC modules is only the matter of typing
>
> make
>
> :)
>
> -- there is no PPC-uclinux ASFAIK and I see no reason on even working
> on it.
> 
> Antti


Article: 105593
Subject: Re: An idea for a product (FPGA/ASIC based)
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 26 Jul 2006 18:05:02 GMT
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> wrote in message 
news:1153928175.353206.250290@m73g2000cwd.googlegroups.com...
>> Just curious: How would one connect two PCIe 4x ports in one card?
>>
>> Or would PICe 8x (or PCI 16x) be a better way to go?
>
> Last I checked, you couldn't just buy an PCIe 8x controller chip. For
> example, the Dini board ( http://www.dinigroup.com/DN8000k10pcie-8.php
> ) has two 4-lane PHYs and they expect all the DMA logic to be coded in
> the connecting chip (using cores from
> http://www.asic-architectinc.com).
>
> I don't understand what is so hard about building an 8-lane PHY with a
> DMA channel for each lane and putting it all in a little chip that
> comes with some nice driver code base for the host machine and LVDS
> output on the far end. I guess that's asking too much. (But it has been
> done for PCI...)

Since I haven't designed a plugin board for PCIe yet, I haven't had to deal 
with this particular issue.  Perhaps the ability to split a PCIe 16x into 
(at least) two PCIe 4x ports is part of the standard.  I thought it would 
require more than one slot to implement more than one PCIe.

I'll look deeper into the spec to see what I might expect from plug-in 
cards.  It's a pretty fundamental change from the "one slot, one port" 
mentality I had.



Article: 105594
Subject: Re: Calculate CRC in Virtex-Spartan II bitstream
From: jbnote@gmail.com
Date: 26 Jul 2006 12:44:43 -0700
Links: << >>  << T >>  << A >>
Hello Francesco,

Francesco Verdicchio wrote:
> Hi,
>  I'm a student, I want calculate the CRC of a standard bitstream
> (Spartan II) Xilinx in C. I read xilinx's
> document( specially xapp176) and i'm applied the CRC algorithm at
> stream of 36 bit:
>

I have not gone into the details of CRC for the spartan-II but recently
implemented the CRC computation for virtex-II family. Some caveats:

> address register 4bit
> data stream 32 bit.

You must compute LSB first on these 36 bits (on virtex-II, there are 5
bits of register address, you may also want to check this).

You must be carefull that the CRC reset happens *after* CRC update by
the RCRC command write (which means that after the RCRC command, the
CRC register is actually zero, not the weird value computed from the
CMD addr + RCRC command).

On virtex-II at least, the contiguous writes to the FDRI must update
the CRC taking into account the FDRI address for each word (this is
clear from the app notes).

Then, on the Virtex-II at least, a successfull CRC write/check would
be:
1/ update the CRC according to the CRC reg addr + CRC write data
2/ check that the resulting CRC value is indeed zero

That is, never access the CRC register's value directly (except on CRC
reset), even in the case of a CRC register write...

The autoCRC word (if such a thing exists in the spartanII) must be
interpreted as a write to the CRC register (which should zero its
value).

JB


Article: 105595
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 27 Jul 2006 08:10:35 +1200
Links: << >>  << T >>  << A >>
Falk Brunner wrote:

> Jim Granville schrieb:
> 
>>>>> With MHz to burn, and FPGA, why not use a
>>>>> Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking
>>>>> Up/down coounter on the index.
>>>>> It can be 100% digital, and the tracking speed becomes the PLL-LPF.
> 
> 
> This is what the 74xx297 is doing with a minimum logic count.

It is close, but differs in the phase comparison area.
The Freq-table solution is actually frequency locked, and has instant
(next cycle) capture time.
Something that uses a Phase detector, has a lock time.

Thought: Is the OP using a lock detector, and waiting long enough
for the lock to occur ?

> 
>> Measure 50Hz (half?) period. appx 50KHz timebase resolves to 0.1%
>> eg gets 20.2ms : Trim and Scale the result, into a lookup table, that
> 
> 
> Why so shy? Why not using a "true high speed" clock (like the 30 MHz) to 
> measure the (half)period? Also, 0.1% is not very accurate for a clock 
> (yeah, yeah I know, we have a new result after every cycle).

For 'normal' clocks, you are right, but this is used to phase decimate 
(?) mains, which is at the 'crappy' end of the scale in phase/freq, so
I chose a simple example point.


> 
>> then loads the 2KHz divider.
>> ( Suppose you target improve of +/- 1% to +/- 0.1%, that is a ~20 
>> entry table.
>>
>> Keeping to 0.1%, 2KHz to 0.1% is 2MHz Clock, with ~1000 divider values.
>>
>> Table/ROM has 20 entries, of 11 bit binary values.
>>
>> Each new cycle uses the last cycles period, to get a best fit of 40 
>> '2Khz' clocks.
>>
>>  Tracking counter Method :
>> Count the 2KHz clocks you actually get, in a 50Hz period.
>>
>>  For 2KHz, create an 11 bit Divider(from 2MHz), fed from an 11 bit 
>> Up/Dn counter.
>>  If the Counts_2Khz is ABOVE 40, then Increment the Up/Dn counter, if it
>> is BELOW 40, decrement the Up/Dn counter.
>> ( for higher precision, you might count higher in the divider than 
>> 2Khz - you have not given desired jitter/precision values )
> 
> 
> Sounds very much like 74xx297.
> 
>> Most main systems will reset/load the 2KHz on zero cross, to phase lock
>> that. You also want to freqency lock, to have a known phase stepping.
> 
> 
> I always wonder how people distinuish between a PLL (PHASE lock) and so 
> called FLL (Frequeny lock).
> My humble opinion is, that it is nonsense to seperarte phase lock from 
> frequncy lock, since they are mathematical the integral/deviation of 
> each other.

Depends if you are an engineer, or a mathematician :)

You can have Frequency lock, and NOT have Phase lock.
If you work on the national grid, that subtle difference is vitally 
important.

A PLL has a lock-time, as it "hunts for lock" - FLLs have a different
trade off.

-jg



Article: 105596
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 26 Jul 2006 23:06:18 +0200
Links: << >>  << T >>  << A >>
Jim Granville schrieb:

> It is close, but differs in the phase comparison area.
> The Freq-table solution is actually frequency locked, and has instant
> (next cycle) capture time.
> Something that uses a Phase detector, has a lock time.

So has your solution. It's just faster. ;-)

> Thought: Is the OP using a lock detector, and waiting long enough
> for the lock to occur ?

Dunno. My code has none. I gues he uses just a scope to see if the two 
clocks are in lock. I hope he is triggering on the 50 Hz, not 2 kHz ;-)

>> I always wonder how people distinuish between a PLL (PHASE lock) and 
>> so called FLL (Frequeny lock).
>> My humble opinion is, that it is nonsense to seperarte phase lock from 
>> frequncy lock, since they are mathematical the integral/deviation of 
>> each other.
> 
> 
> Depends if you are an engineer, or a mathematician :)
> 
> You can have Frequency lock, and NOT have Phase lock.

As I said before, this sounds like a language problem for me. Even a 
(fixed) phase relation of other than zero degree is a phase lock.

> If you work on the national grid, that subtle difference is vitally 
> important.

???

> A PLL has a lock-time, as it "hunts for lock" - FLLs have a different
> trade off.

I don't believe in FLLs. The are IMHO "just" PLLs with different jitter 
properties (filtering, tolerance etc.)

Regards
Falk


Article: 105597
Subject: Re: How to phase align a 10MHz clock using V4LX60 DCM
From: "PeteS" <PeterSmith1954@googlemail.com>
Date: 26 Jul 2006 14:06:33 -0700
Links: << >>  << T >>  << A >>
Aurelian Lazarut wrote:
> vssumesh wrote:
>
> >Gabor wrote:
> >
> >
> >>When you multiply a clock and then divide it, there is no common
> >>phase relationship of the output unless you reference the original
> >>signal.  I would suggest sampling the input clock using a flip-flop
> >>clocked by the 10x clock.  The output of this flip-flop should have
> >>a constant (somewhat delayed) phase relationship to the original.
> >>Additional 10x clock delays can then be added to adjust the clock
> >>to the desired phase.
> >>
> >>
> >>
> >>
> >Hi I am Subins collegue,
> >  What we are trying to do is advance the input clock by 4 to 6 ns not
> >to delay it.
> >
> >
> >
> pretty much the same thing, if you are considering that the delayed
> version, it's an "early" version against the next transition...,
> otherwise just wait for soeone to invent a time machine.
> Aurash

Snort

The other possibility is to delay all the other signals on 1 metre of
FR4. That'll advance the clock relatively by 6 nS ;)

Cheers

PeteS


>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324


Article: 105598
Subject: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 27 Jul 2006 10:06:24 +1200
Links: << >>  << T >>  << A >>
Falk Brunner wrote:

>>> My humble opinion is, that it is nonsense to seperarte phase lock 
>>> from frequncy lock, since they are mathematical the 
>>> integral/deviation of each other.
>>
>>
>>
>> Depends if you are an engineer, or a mathematician :)
>>
>> You can have Frequency lock, and NOT have Phase lock.
> 
> 
> As I said before, this sounds like a language problem for me. Even a 
> (fixed) phase relation of other than zero degree is a phase lock.

A fixed phase relation is a phase offset, not a phase lock (=same 
angle). The offset may not be moving, but it is not a phase lock.

> 
>> If you work on the national grid, that subtle difference is vitally 
>> important.
> 
> ???

  There have been some spectacular mistakes made, where circuit's were
tripped between generators and the national power grids, when
the generator WAS frequemcy locked, but NOT with a small enough phase 
offset ( ie not phase locked, and here phase has magnitude and sign )
  - so it is a tad more than a language problem :)

-jg




Article: 105599
Subject: Re: uClinux on Virtex-4 Mini-Module
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 27 Jul 2006 00:24:01 +0200
Links: << >>  << T >>  << A >>
"Guru" <ales.gorkic@email.si> schrieb im Newsbeitrag 
news:1153936946.445885.78180@i42g2000cwa.googlegroups.com...
> Antti,
>
> You are probably trying to say: buy hydraXC module and you will get a
> fully configurable MB-uClinux and PPC-linux.
> VMWare probably means that I can compile the OS using Windows and linux
> in a virtual machine.
> What about the memory management in PPC-linux?
> What can the PPC-linux do besides networking (multithreading...)?
> Is the GSRD2 LL_TEMAC driver included? If not, can I use the linux
> driver made for normal linux (MV or tarball 2.16.)?
>
> Cheers,
>
> Guru

Hi

I was saying that
1) I do provide better support than Avnet/Memec does
2) hydraXC modules have 'added values' compared to say V4MM

VMWare means that there is a known good kernel compile environment
so need for the user todo any setup, its all prepared. Yes you double
click on .vmx file it starts linux in VMwar player, then type
make
and get your kernel.

the PPC-linux should be rather full linux with MMU, its configured
rathter minimal, with uart timer and opb_ethernet

as of using TEMAC drivers I do not know. I will be looking into
the EDK TEMAC but later currently we have no working designs
based on TEMAC only with opb_ethernet

Antti













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