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On Sat, 30 Sep 2000 20:55:39, Ray Andraka <ray@andraka.com> wrote: > best I could tell, synplify pro just has a bunch of bells and whistles I wasn't > going to use anyway. I'm sticking to 6.0 plus the RTL analyst. It looked like > pro gives you the analyst as part of the package, plus a different GUI, the > ability to sprinkle pipeline registers inside multipliers (Big Fat Hairy Deal if > you construct the logic you need anyway), ability to have two designs open at > once and a few other little things. Nothin I could see there justified the big > price difference. The Synplicity reps have been trying to persuade me to go to PRO too, but I just can't see it. I don't know if they're serious or not but the license upgrade from the base + anual maintenance is stunning. Yikes, I just paid for another year of maintenance. OTOH, Amplify looks great. After going though their PowerPoint widget, I'm not sure I need Synplify at all (at least for the Virtex). I am confused. I'll have to read the Amplify manual. Maybe one of their FAEs will decide to come visit again. ...now that I know something. ---- KeithArticle: 26026
Ahh, but in the FIR filter you can go to a partially transposed architecture and thereby absorb the delays as part of the sample delays you need anyway. There is **no_latency_penalty** if you do it right! It is not the intuitively obvious approach, though. Muzaffer Kal wrote: > > I am implementing a programmable FIR and latency is a very big > problem. So my definition of best is the fastest design with at most > one pipeline in the adder tree. Size of no importance. > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26027
No, last time I played with them the -2 part was all there was. IIRC, a 16 bit counter implemented as a sync. counter with a straight ripple carry chain was on the order of about 60 MHz. I seem to remember it taking about a ns per bit for the carry to propagate in the -2 parts. If there is a cell to cell timing in the data sheet, multiply that times the bits. I suspect they won't outright advertise a 16 bit counter performance because it doesn't compare very nicely with the chips that have a carry chain. The Atmel device really requires alot of the skills we used in the Xilinx 3K series when there was no carry chain. For example, using an LFSR for the count if at all possible. The 40K will work nicely in bit serial applications, but even there the more recent A and X parts will be faster. In just about any other application, you are giving up alot to have the partial reconfigurability. When the 40K came out (just before Xilinx announced the first spartan parts) it was targeted as a socket compatible xilinx replacement for the 4K parts, at what was to be a substantially lower price ($40 or so). The introduction of the spartan parts eliminated that, and the fact they overlooked the carry chain really limited the application. Since then, xilinx parts prices have dropped considerably, leaving the AT40K as a less capable, slower and now more expensive device compared to equivalent density Xilinx devices. Its a shame they left out the carry chain. It would have been a nice part with it. rickman wrote: > > Actually, I guess I was wrong about needing to partial configure the > part while running. With my current multichip design, I have to have the > main FPGA running to talk to the rest of the board. But with an all in > one chip approach, I can configure in sections in a complete reload of > the FPGA. I do still need partial configuration so that I can separately > develop and select the four sections of the chip. > > But I don't see where there is much support for the design side of > things. But I have not looked at their tools. As you say, the chips are > not the best architecture for many applications. And the cost is a > significant issue as well. > > Do you have any idea how fast a 16 bit counter might run in a -1 part? I > have not seen any info on this even in marketing material. In fact, the > AT40K40AL does not even have a data sheet on the Atmel web site. But it > is listed for sale at the Marshall web site. > > Ray Andraka wrote: > > > > Atmel's device handles partial reconfig really nicely. A reconfiguration can be > > specified for any rectangular area down to a 1x1 cell area, which means you can > > reconfigure just what you want, not a whole column like virtex. Atmel has some > > tools for using reconfiguration for changing constants, and they may have added > > more since I last played with it. The toolset and silicon (as of over 2 years > > ago) is more friendly to partial configuration than any of the xilinx > > tools/silicon up to v3.1. That said, the device weaknesses in arithmetic > > applications may make it a non-contender for your application anyway. Nobody > > really has suitable tools yet for handling all the intricacies of partial > > reconfiguration correctly (especially if it is to be done while the application > > clock is running). > > > > rickman wrote: > > > > > > I was looking at an Atmel FPSLIC ad today and it made me think about how > > > it might let me put one chip on my board instead of four. I use four > > > FPGAs for two reasons. One is that I need a total of about 350 IOs for > > > the whole board. But the real reason is that at least two sections of > > > the FPGA design are used as interface to add on daughter cards (AIO > > > modules). When the AIO module is detected at boot up, the appropriate > > > FPGA design is loaded to drive the module. This saves hardware on the > > > modules and (theoretically) saves me money. > > > > > > The problem is that I have to use two separate chips for the AIO > > > interfaces in addition to the main FPGA for the central board control. I > > > am expecting to split the main FPGA in two because there is also some > > > other board IO that I would like to make reconfigurable. > > > > > > If I could get one large FPGA with in circuit, partial > > > reconfigurability, I could replace four parts with one or two. But > > > looking at web pricing for the Atmel parts, it seems that it would still > > > cost me more for one or two AT40K parts than it does for four Lucent or > > > Xilinx parts. > > > > > > That still leaves the issue of how well Atmel supports partial > > > reconfiguration, both in the design stage and in the reconfiguration > > > stage. Anyone using these parts in a partial reconfiguration > > > application? > > > > > > Ray Andraka wrote: > > > > > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > > > fast carry chain. As a result, Altera and Xilinx implementations will run > > > > circles around anything done in Atmel for arithmetically heavy applications > > > > (that includes binary counters, folks!). If you can manage without carry > > > > chains, the parts are closer to equal, although Atmel does have the best partial > > > > reconfiguration out there right now. > > > > -- > > > > -Ray Andraka, P.E. > > > > President, the Andraka Consulting Group, Inc. > > > > 401/884-7930 Fax 401/884-7950 > > > > email ray@andraka.com > > > > http://www.andraka.com or http://www.fpga-guru.com > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design > > > > > > Arius > > > 4 King Ave > > > Frederick, MD 21701-3110 > > > 301-682-7772 Voice > > > 301-682-7666 FAX > > > > > > Internet URL http://www.arius.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26028
would you like to elaborate on this ? Any papers I can read related to this "partially transposed architecture" ? thanks, Muzaffer On Sun, 01 Oct 2000 03:47:16 GMT, Ray Andraka <ray@andraka.com> wrote: >Ahh, but in the FIR filter you can go to a partially transposed architecture and >thereby absorb the delays as part of the sample delays you need anyway. There >is **no_latency_penalty** if you do it right! It is not the intuitively obvious >approach, though. > >Muzaffer Kal wrote: >> >> I am implementing a programmable FIR and latency is a very big >> problem. So my definition of best is the fastest design with at most >> one pipeline in the adder tree. Size of no importance. >> >>Article: 26029
These parts are long over the hill (They were announced as end of life parts some 7 or 8 years ago). None of the current generation tools support it. The last xilinx tool set to support them was XACT6, which was replaced about 3 years ago (and in my case 2 machines ago) by the M1 tools. If you can find someone with a copy, and who is willing to give up the accompanying dongle you may still not be able to use the tools unless you resurrect an old machine too. XACT6 was a dos/windows3.1 toolset. It didn't work very well under windows95. At this point, if your goal is learning, I'd recommend spending the $200 or so for the XESS board plus the student edition of the current tools. The kit comes with labs and a text. In the end, I think you'll wind up spending less and you'll have current device experience. "news.gate.net" wrote: > > I'm a rather "advanced" hobbyist, looking to get into some FPGA design (for > starters, as some glue logic for an ISA PC Card). I recently stripped an > old videoconferencing system and it had about 50 XC2018-P84C chips on it > (also some XC3042's and a pair of XC3090's). It also has a lot of GALs, > 57C291's, 57C45's, and some various Altera stuff. In short, it is a > reprogrammable logic goldmine. > > But, many of the parts are out of production and finding development support > for them is difficult. I have Protel 99 SE and have a simple design input > into it (schematic). But, when I compile it, I get a message about missing > PLA2XNF.EXE. I'm assuming this is part of the Xilinx XACT tools? > > The problem I have is that nothing currently available from Xilinx seems to > support my XC2018 chips. I prefer to use the Xilinx stuff at this point, > because I can store the programming in an EPROM (I have a burner) rather > than having to program the actual chip (I don't have a burner capable of > doing any programmable logic burning). > > Does anyone have some pointers as to where I can find support for these > devices? (It appears that the student [and even professional] editions of > Xilinx' stuff are geared toward their newer parts). > > Thanx in advance! > Robert Garito > rgarito@gate.net -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26030
First of all, Altera makes CPLD's not FPGAs...minor technical distinction. I'm of the belief that recruiters who post technically accurate job listings get better technical candidates! > We are setting up a design center in new delhi, india. > > Pre-IPO company. > > Stock options in US parent company. > > www.forasic.com Have you considered listing your job postings under www.jobtrak.com?Article: 26031
Having used both XSE 1.3 and XSE 1.5 extensively, I feel compelled to inform the world about my initial impressions of XSE 2.1i. The old versions.... Xilinx has been bringing FPGA design closer and closer to the 'poor college student' (which I admit I am no longer...) Since 1.5, XSE has supported VHDL/Verilog synthesis with the included FPGA Express. I worked on one 'substantial' design using XSE1.3 and another one using XSE1.5. (The 1st project targeted an XC4005E, the second targeted an XC4010XL.) The schematic editor lets users 'draw circuits' using basic logic components as well as device-dpendent and user-defined macros. The editor itself feels like a Windows 3.1 application, doesn't support Win95 long-filenames, scrolling the schematic leaves behind graphical debris, and the annoying general protection fault. This is not a tool I'd be comfortable with, on a *large* scale design (i.e. 'system on a chip.') The finite-state-editor and HDL editor are both true Win32 apps. (The HDL editor is just a fancy text-editor with menu shortcuts to the FPGA-Express compiler.) I really liked the finite-state editor. Entering state-machines graphically is a perfect way to start learning digital design. Even better, the editor can even generate HDL code, with some caveats - the user must write state descriptions using statements which are syntactically correct in the target HDL (VHDL, Verilog, or ABEL.) I wish there were a way to arbitrarily put text boxes arbitrarily on the state-diagram sheet, but there isn't. The FPGA-express compiler, is another Win32 app. The compiler itself is fine, but integration with the Xilinx tool flow is another story. I had numerous problems trying to synthesize HDL code which used previously created HDL macros. Most of the time, resynthesizing the subhierarchy of HDL macros would 'refresh' their linkage within the project database. Other times, I had to manually delete the macro from the project library, then resynthesize. It was a minor annoyance. More serious problems had to dow ith the Logiblox generator. I used Logiblox to generate some RAM blocks, but I could not seem to make FPGA-Express see my RAM blocks. In the end, I had to put the memory signals onto the HDL module input/output list, then wire the RAM-block and HDL-macro inside the schematic editor. This was the case for 'schematic capture flow', I did not try 'hdl flow.' (When you initially create a new project, Xilinx forces you to choose a project design flow, HDL or schematic.) Oh and, the XSE1.5's FPGA-Express refused to run under Win2000. The flexlm system could not return my machine's ethernet ID. I downloaded more recent flexlm runtime libraries from www.globetrotter.com, but to no avail. FPGA-Express only runs with the older flexlm libraries included in XSE15. All these apps are glued together by the "project manager", a Win16 app which feels very out of place. No longfilenames, the familiar 'C:\PROGRA~1\...'! Over the course of my two projects, the project manager would just about hang and crash, every other day...the hallmark of a Win 3.x program. It even took down NT4 workstation on a few occasions. 1.3 was worse than 1.5, but 1.5 barked now and then. For all these faults, I did successfully complete my projects! The faults were annoying glitches, but not really showstoppers. ... Opening the XSE 2.1i package, I expected to find a polished "Design for Windows95" compliant application. Nope...project manager still does the 'C:\PROGRA~1\...' junk. On the plus side, the schematic editor now supports Win95 long filenames (yeah I know it's year 2000...and we're still worrying about this stuff.) But the waveform simulator doesn't... I've yet to work extensively with XSE 2.1i, but it looks like major parts of Xilinx Student Edition are still running legacy Win16 code. I guess this isn't a big deal, since the core implementation/synthesis engines are native Win32 modules. As if to make up for these shortcomings, Xilinx has *generously* added Virtex50 (XCV50) support to the student-edition. Spartan2-50 is also supported. And, they've lowered the base-price from $100 to $55 USD (the practical lab manual is no longer included.)Article: 26032
hi ray, for the case of an adder tree do you still believe that building the adders using carry logic is wise ?. The architecture is irregular and the adders are all vertical --Erika In article <39D6B380.3383A152@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > Ahh, but in the FIR filter you can go to a partially transposed architecture and > thereby absorb the delays as part of the sample delays you need anyway. There > is **no_latency_penalty** if you do it right! It is not the intuitively obvious > approach, though. > > Muzaffer Kal wrote: > > > > I am implementing a programmable FIR and latency is a very big > > problem. So my definition of best is the fastest design with at most > > one pipeline in the adder tree. Size of no importance. > > > > > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26033
I thought that Altera made "EPLDs" and CPLDs.
However, I thought that the Flex 10K/6K families are gate arrays,
thereby making them an FPGAs, technically.
Please correct me if I am wrong.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Netscape User" <your_email@here.net> wrote in message
news:39D6C2D8.CE6E3315@here.net...
> First of all, Altera makes CPLD's not FPGAs...minor technical
> distinction. I'm of the belief that recruiters who post technically
> accurate job listings get better technical candidates!
>
> > We are setting up a design center in new delhi, india.
> >
> > Pre-IPO company.
> >
> > Stock options in US parent company.
> >
> > www.forasic.com
>
> Have you considered listing your job postings under www.jobtrak.com?
>
Article: 26034snyderkena@my-deja.com wrote: > > I realize that I will have to spend $$ for a board and FPGA, but are > there any free software tools? I realize the tradeoff between $$ and > ease. I am not committed to a particular FPGA, and free tools would > weigh heavily. > There is a GPL verilog simulation & synthesis tool called Icarus Verilog (http://icarus.com/eda/verilog/index.html). It even outputs Xilinx netlists (xnf). cheer, aaronArticle: 26035
The Altera 10KE family is very much like Xilinx FPGA parts, ... they are sram based, have LUT's, block ram, serial and parallel configuration modes. Xilinx lets one use the LUT as RAM, where Altera does not. I read somewhere that Altera calls their parts something other than FPGA's, but I think that conceptually, the parts are very similar. Bob In article <NiHB5.7086$1H2.873605@typhoon.tampabay.rr.com>, "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote: > I thought that Altera made "EPLDs" and CPLDs. > However, I thought that the Flex 10K/6K families are gate arrays, > thereby making them an FPGAs, technically. > Please correct me if I am wrong. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > "Netscape User" <your_email@here.net> wrote in message > news:39D6C2D8.CE6E3315@here.net... > > First of all, Altera makes CPLD's not FPGAs...minor technical > > distinction. I'm of the belief that recruiters who post technically > > accurate job listings get better technical candidates! > > > > > We are setting up a design center in new delhi, india. > > > > > > Pre-IPO company. > > > > > > Stock options in US parent company. > > > > > > www.forasic.com > > > > Have you considered listing your job postings under www.jobtrak.com? > > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26036
Netscape User writes: > First of all, Altera makes CPLD's not FPGAs...minor technical > distinction. I'm of the belief that recruiters who post technically > accurate job listings get better technical candidates! Altera make FPGAs, but they call them CPLDs. The distinction? Trademark, marketing, patent or something like that. If Altera didn't make FPGAs, discussion of Alteras would be offtopic in this newsgroup :-) I'm of the belief that "FPGA" has become a generic term for "large many-times-reprogrammable logic device". Like hoovers. -- JamieArticle: 26037
Muzaffer Kal writes: > would you like to elaborate on this ? Any papers I can read related to > this "partially transposed architecture" ? I will, just for practice :-) An FIR consists of a series of multipliers (the taps) and an adder tree. You can pipeline that any way you like. Each multiplier consist of a series, or a tree, of adders/subtractors, pipelined any way you like. Each adder consists of a series, or a tree, of single-bit adders with optional carry lookahead logic. Again, pipeline if you like (though in an FPGA with fast carry chains you generally don't want to pipeline the carry). The whole thing is just a multidimensional lot of adders and delays. Feel free to place the delays differently, and to reorder the addition operations. I guess this would be called partial transposition. Sorry, no references or design advice :-) -- JamieArticle: 26038
I've got an old computer design that has a few PAL/GAL devices and some TTL as glue logic between a CPU and memory & some peripherals (SCSI controller, etc.). I'd like to update this design to use a single FPGA-type device. I've got all the schematics, timings and PAL programming info. What is the best path to convert this design? Is there a "input old TTL & PAL info -> output FPGA" tool out there (half kidding)? What tools have people used for this? Thanks for your input. Ken Ken Seefried, CTO & Founding Partner, DigitalMoJo Information Security Management, Consulting & TrainingArticle: 26039
transposed architecture presents the input sample simultaneously to all the coefficient moultipliers, and the delays are on the output side of the multipliers. If your delay between taps is more than 1 clock then, you need to add delays to the inherent 1 clock delay of the adder, which can be done in line with the adder, or on the input side of each multiplier. When the delay is split between the input and output sides, you have what I was calling a partially transposed architecture. Muzaffer Kal wrote: > > would you like to elaborate on this ? Any papers I can read related to > this "partially transposed architecture" ? > > thanks, > > Muzaffer > > On Sun, 01 Oct 2000 03:47:16 GMT, Ray Andraka <ray@andraka.com> wrote: > > >Ahh, but in the FIR filter you can go to a partially transposed architecture and > >thereby absorb the delays as part of the sample delays you need anyway. There > >is **no_latency_penalty** if you do it right! It is not the intuitively obvious > >approach, though. > > > >Muzaffer Kal wrote: > >> > >> I am implementing a programmable FIR and latency is a very big > >> problem. So my definition of best is the fastest design with at most > >> one pipeline in the adder tree. Size of no importance. > >> > >> -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26040
Absolutely! If you look at it carefully, the architecture is actually quite regular. Put the first level adders on every other column, then insert the second layer on every other interleaved column, the third on every other between them and so on. This is quite fast for small trees. When the tree gets large enough that the interconnect between levels is too long, you can add an extra register at the inputs of the next layer to break up the long critical path from the previous level through the carry chain. In the case of an FIR filter, using the partially transposed architecture to absorb the delays, you use an adder chain rather than a tree. That structure is good for an SDA filter with bit rates of more than 150 MHz in a Virtex-4 (slow speed grade). erika_uk@my-deja.com wrote: > > hi ray, > > for the case of an adder tree do you still believe that building the > adders using carry logic is wise ?. The architecture is irregular and > the adders are all vertical > > --Erika > > In article <39D6B380.3383A152@andraka.com>, > Ray Andraka <ray@andraka.com> wrote: > > Ahh, but in the FIR filter you can go to a partially transposed > architecture and > > thereby absorb the delays as part of the sample delays you need > anyway. There > > is **no_latency_penalty** if you do it right! It is not the > intuitively obvious > > approach, though. > > > > Muzaffer Kal wrote: > > > > > > I am implementing a programmable FIR and latency is a very big > > > problem. So my definition of best is the fastest design with at most > > > one pipeline in the adder tree. Size of no importance. > > > > > > > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26041
Actually I seem to remember something like this a few years ago. But I assume that the need for this has diminished over the last few years and the software is no longer available or supported. If you have the source code in ABEL or PALASM or even PLPL, you should be able to convert it all to ABEL which is still supported by Xilinx. I am not so sure about Altera, but they likley support ABEL as well. As to using an FPGA, you might do better using one of the larger CPLDs. The FPGAs use smaller blocks of logic and string them together for large functions. CPLDs use wide input AND arrays followed by a fixed OR array just like your PALs. Opps, I just noticed that you said you had "schematics". I guess you can use any vendor you wish as they all work OK from schematics. Hmmm... do Cypress and the other smaller CPLD vendors use schematic input? "K.J. Seefried III" wrote: > > I've got an old computer design that has a few PAL/GAL devices and > some TTL as glue logic between a CPU and memory & some peripherals > (SCSI controller, etc.). I'd like to update this design to use a > single FPGA-type device. I've got all the schematics, timings and PAL > programming info. > > What is the best path to convert this design? Is there a "input old > TTL & PAL info -> output FPGA" tool out there (half kidding)? What > tools have people used for this? > > Thanks for your input. > > Ken > > Ken Seefried, CTO & Founding Partner, DigitalMoJo > Information Security Management, Consulting & Training -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26042
I am a begineer in FPGA and VHDL. I want any help. I am using Mentor Graphics FPGA Advantage. Thanks In Advance. RAMI Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26043
Ray Andraka wrote: > Like I said, lots of bells and whistles, but nothing that I can see to justify > the extra $$$. > It's the special IPO release. The investors just got a bit freaked by the number of amateurs using the tool.Article: 26044
K.J. Seefried III wrote: > > I've got an old computer design that has a few PAL/GAL devices and > some TTL as glue logic between a CPU and memory & some peripherals > (SCSI controller, etc.). I'd like to update this design to use a > single FPGA-type device. I've got all the schematics, timings and PAL > programming info. > > What is the best path to convert this design? Is there a "input old > TTL & PAL info -> output FPGA" tool out there (half kidding)? What > tools have people used for this? This sounds more like a CPLD problem, than a FPGA problem. First task is to collate all the TTL.PAL devices, and get a count of Inputs/Outputs and appx number of nodes/registers. This will let you select the silicon. If you have the PAL Source codes ( not just the JED files ), then that is relatively easy, to merge the source files for eg 16V8's and some TTL, and create a 44-100 Pin CPLD design file. Some CPLD tools have TTL Macros, but you may find it easier to read these as a guideline, and then code the subset directly, rather than import as macros. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 26045
=========================
C A S E S 2 0 0 0
International Conference on Compilers, Architecture, and Synthesis
for Embedded Systems
(http://www.capsl.udel.edu/conferences/cases2000)
November 17-18, 2000
Doubletree Hotel
San Jose, California
U.S.A.
=========================
ADVANCED PROGRAM AND REGISTRATION INFORMATION
=========================
IMPORTANT DATES
---------------
CUTOFF DATE FOR ONLINE REGISTRATION:
NOVEMBER 10, 2000
(at http://www.capsl.udel.edu/conferences/cases2000)
ON-SITE REGISTRATION AT DOUBLETREE HOTEL:
NOVEMBER 16, 2000 (Thu) 7pm to 9pm
NOVEMBER 17, 2000 (Fri) 7.30am to 8.30am
CUTOFF DATE FOR HOTEL REGISTRATION: OCTOBER 26, 2000
(Normal rates only thereafter)
==========================
CONFERENCE HIGHLIGHTS
---
INVITED TALKS
November 17 (Fri) 9am to 10am
RIGOROUS DEVELOPMENT OF EMBEDDED SYSTEMS
Amir Pnueli, New York University and
The Weizmann Institute of Science
November 18 (Sat) 9am to 10am
THE ERA OF EMBEDDED COMPUTING
B. Ramakrishna (Bob) Rau, Hewlett-Packard Laboratories
---
PANEL DISCUSSION
November 18 (Sat) 4pm to 5.30pm
SYSTEM ON A CHIP: HARDWARE DREAM OR SOFTWARE NIGHTMARE?
Moderator: Patrick Devaney, Panasonic AVC American Labs
Panelists: Willie Anderson, Analog Devices
Jon Fields, Lucent Technologies
Joachim Kunkel, Synopsis
Kees Vissers, TriMedia Technologies
==========================
ADVANCED PROGRAM
NOVEMBER 16, 2000 (Thursday)
7pm-9pm Pre-registration
--------------------------
NOVEMBER 17, 2000 (Friday)
9am-10am Invited Talk
RIGOROUS DEVELOPMENT OF EMBEDDED SYSTEMS
Amir Pnueli, New York University and
The Weizmann Institute of Science
COFFEE BREAK - 10am - 10.30am
Session 1 (10:30am - 12:15pm)
* "Efficient Compilation of ESTEREL for Real-Time Embedded Systems"
Daniel Weil, Valerie Bertin, Etienne Closse, Michel Poize,
Patrick Venier, Jacques Pulou; France Telecom R&D, Laboratoire
d'Automatique de Grenoble, and Alcatel Business Systems
* "Eliminating External Fragmentation in a Non-Moving Garbage
Collector for Java"
Fridtjof Siebert; Universitat Karlsruhe
* "A Code Generation Framework for Java Component-based Designs"
Jeff Tsay, Christopher Hylands, and Edward A. Lee; University
of California, Berkeley
* "A Joined Architecture/Compiler Design Environment for ASIPs"
Jurgen Teich, and Ralph Weper; University of Paderborn
* "A Preprocessing Step for Global Loop Transformations for Data
Transfer and Storage Optimization"
Koen Danckaert, Francky Catthoor, and Hugo De Man; IMEC
LUNCH BREAK - 12.15pm - 1:45pm
Session 2 (1:45pm to 3.30pm)
* "PROMPT: A Mapping Environment for Telecom
Applications on "System-On-a-Chip""
Michel Barreteau, Thierry Grandpierre, Philippe Bonnot,
Juliette Mattioli, Christophe Lavarenne, Philippe Kajifasz,
Corinne Ancourt, Francois Irigoin, and Yves Sorel; Thomson-CSF,
INRIA, Ecole des Mines de Paris, and SIMULOG
* "Embedding SDL Implemented Protocols into DSP"
Antti Takko, Marko Hannikainen, Jarno Knuutila, Timo Hamalainen, and
Jukka Saarinen; Tampere University of Technology, and Nokia Mobile
Phones
* "Adapting Software Pipelining to Reconfigurable Hardware"
Timothy J. Callahan, and John Wawrzynek; University of California,
Berkeley
* "Specification and Synthesis of Real-Time Embedded Distributed
and Parallel Multiprocessor-based Signal Processing System",
Randall S. Janka, and Linda M. Wills; Cadence Design System Inc.,
and Georgia Institute of Technology.
* "Fast Automated Design Space Exploration in PICO",
Santosh G. Abraham, and B. Ramakrishna (Bob) Rau; Hewlett-Packard Labs
COFFEE BREAK - 3:30pm - 4pm
Session 3 (4pm - 5:45pm)
* "Design and Implementation of a Hierarchical Exception Handling
Extension to SystemC"
Prashant Arora, and Rajesh Gupta; University of California,
Irvine
* "Scheduling Algorithms for Automated Synthesis of Pipelined
Designs on FPGAs for Applications described in MATLAB"
Malay Haldar, Anshuman Nayak, Alok Choudhary and Prith Banerjee;
Northwestern University
* "Code Generator Optimizations for the ST100 DSP-MCU Core"
Benoit Dupont de Dinechin, Francois de Ferriere, Chrisophe Guillon,
and Arthur Stoutchinin; ST Microelectronics
* "Dynamic Scheduling of Concurrent Tasks with Cost Performance
Trade-off"
Peng Yang, Dirk Desmet, Francky Catthoor, and Diederik Verkest; IMEC
* "Architecture for Embedded Software Integration with Reusable
Components"
Shige Wang and Kang G. Shin; University of Michigan
HOSPITALITY BOOTH - 6pm - 9pm
Star*Core
--------------------------
NOVEMBER 18, 2000 (Saturday)
9am-10am Invited Talk
THE ERA OF EMBEDDED COMPUTING
B. Ramakrishna (Bob) Rau, Hewlett-Packard Laboratories
COFFEE BREAK - 10am - 10.30am
Session 4 (10:30am - 12:15pm)
* "Region-based Caching: An Energy-Delay Efficient Memory Architecture
for Embedded Processors"
Hsien-Hsin S. Lee, and Gary S. Tyson; University of Michigan
* "Embedded ISA Support for Enhanced Floating-Point to Fixed-Point
ANSI C Compilation"
Tor Aamodt and Paul Chow; University of Toronto
* "Energy-Oriented Compiler Optimizations for Partitioned
Memory Architectures"
V. Delaluz, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin;
Pennsylvania State University
* "Unroll-and-jam for Imperfectly-nested Loops in DSP Applications"
Yonghong Song, and Yuan Lin; Purdue University, and Star*Core
* "Handling Irregular ILP within Conventional VLIW Schedulers using
Artificial Resource Constraints",
Subramanian Rajagopalan, Manish Vachharajani, and Sharad Malik;
Princeton University,
LUNCH BREAK - 12.15pm - 1:45pm
Session 5 (1:45pm - 3:30pm)
* "A Programmable Unified Cache Architecture for Embedded Applications"
Afzal Malik, Bill Moyer, and Dan Cermak; Motorola Inc.
* "Parallel Saturating Multioperand Adders"
Michael J. Schulte, and Pablo I. Balzola; Lehigh University
* "A Dynamic Memory Management Unit for Embedded Real-Time
System-on-a-Chip"
Mohamed Shalan, and Vincent J. Mooney III; Georgia Institute of
Technology
* "A First-step Towards an Architecture Tuning Methodology"
Greg Stitt, Frank Vahid, Tony Givargis, and Roman Lysecky;
University of California, Riverside
* "Flexible Instruction Processors",
Shay Ping Seng, Wayne Luk, and Peter Y.K. Cheung; Imperial College
COFFEE BREAK - 3.30pm - 4pm
PANEL DISCUSSION - 4pm to 5.30pm
"System on a chip: Hardware Dream or Software Nightmare?"
Moderator: Patrick Devaney, Panasonic AVC American Labs
Panelists: Willie Anderson, Analog Devices
Jon Fields, Lucent Technologies
Joachim Kunkel, Synopsis
Kees Vissers, TriMedia Technologies
BANQUET - 7.30pm - 9.30pm
==========================
STEERING COMMITTEE:
James R. Boddie
Lucent Technologies
Guang R. Gao
University of Delaware
Vinod Kathail
Hewlett-Packard Labs
Edward Lee
Univ. of California Berkeley
Reid Tatge
Texas Instruments
CONFERENCE CHAIR:
Krishna V. Palem
Georgia Institute of Technology
COORDINATION VICE-CHAIR :
Weng-Fai Wong
Georgia Institute of Technology
and National Univ. of Singapore
LOCAL ARRANGEMENTS VICE-CHAIR:
Praveen Murthy
Angeles Design Systems
PANELS VICE-CHAIR:
Jack W. Davidson
University of Virginia
PUBLICATIONS VICE-CHAIR:
Jaime Moreno
IBM T.J. Watson Research Center
PUBLICITY VICE-CHAIR:
Vincent J. Mooney III
Georgia Institute of Technology
PROGRAM COMMITTEE:
Shuvra S. Bhattacharyya
University of Maryland
Henk Corporaal
Delft University of Technology
Srinivas Devadas
Massachusetts Institute of Technology
Christine Eisenbeis
INRIA Rocquencourt
Antonio Gonzalez
Universitat Politecnica de Catalunya
Rajesh Gupta
University of California at Irvine
Nevin Heintze
Lucent Bell Laboratories
Kathryn S. McKinley
University of Massachusetts, Amherst
Lothar Thiele
ETH Zurich
Frank Vahid
University of California at Riverside
Wei Zhao
Star*Core
==========================
CASES 2000 gratefully acknowledges the sponsorship of:
Hewlett-Packard IBM Star*Core
==========================
FOR INQUIRIES PLEASE EMAIL: cases@capsl.udel.edu
--
Vincent Mooney
Georgia Institute of Technology, Atlanta Georgia, 30332
Email: eefacvmn@prism.gatech.edu
Article: 26046> > Having used both XSE 1.3 and XSE 1.5 extensively, I feel compelled to > > inform the world about my initial impressions of XSE 2.1i. > > But the big question is what specific chips and sizes are supported. > Ben. According to the pack-in datasheet, XSE 2.1i supports XC4000 family up to XC4010, Virtex/VirtexE-50 (XCV50, XCV50E), all Spartan devices (Spartan, SpartanXL), up to Spartan II XC2S50. Some other families (the XC3000, 5200, etc.), too. I neglected to mention this in my original post, thanks.Article: 26047
My workplace recently got an AVNETmarshall Xilinx Development System (Virtex300-BG432 mounted on a PCI-64bit card.) The board is advertised as capable of running in 'standalone mode' (i.e. not plugged into a PCI slot), which is how we'll be using it. Unfortunately, the general purpose I/O header uses an 'exotic' connector - Amp #177983-4. I've checked Amp's website, and they list the specifications for the connector, unfortunately, no links to other mfgs who made sell prefabricated cables. So my question is, does anyone know where I can get a cable with the Amp #177984-4 on one end, and a 'standard pin header' on the other end? By standard-pin-header, I mean any kind of connector type which doesn't require an exotic mating connector. For example, an IDE connector would be perfect (except it's only 40 pins instead of 100.) The other alternative is to use the individual PCI signal lines on the edge connector. Once again, I'm faced with the same problem. While I have no difficulty locating a 64-bit PCI receptable, I don't have access to soldering/PCB etching facilities to make my own custom PCI -> 'standard-pin-header.'Article: 26048
On Sun, 01 Oct 2000 15:39:25 -0700, Netscape User <your_namel@email_address.net> wrote: >My workplace recently got an AVNETmarshall Xilinx Development System >(Virtex300-BG432 mounted on a PCI-64bit card.) The board is advertised >as capable of running in 'standalone mode' (i.e. not plugged into a PCI >slot), which is how we'll be using it. > >Unfortunately, the general purpose I/O header uses an 'exotic' connector >- Amp #177983-4. I've checked Amp's website, and they list the >specifications for the connector, unfortunately, no links to other mfgs >who made sell prefabricated cables. > >So my question is, does anyone know where I can get a cable with the Amp >#177984-4 on one end, and a 'standard pin header' on the other end? By >standard-pin-header, I mean any kind of connector type which doesn't >require an exotic mating connector. For example, an IDE connector would >be perfect (except it's only 40 pins instead of 100.) > >The other alternative is to use the individual PCI signal lines on the >edge connector. Once again, I'm faced with the same problem. While I >have no difficulty locating a 64-bit PCI receptable, I don't have access >to soldering/PCB etching facilities to make my own custom PCI -> >'standard-pin-header.' My current client was exactly in the same situation. What we ended up doing is to get a PCI backplane and a PCI card which has standard jumper style connectors for each PCI pin. The jumpers are on both faces of the card and they are nicely separated so you can get nice physical access to them to plug in logic analyzer probes. I'd be very much interested in a cable with the AMP header too. MuzafferArticle: 26049
Muzaffer Kal <muzaffer@dspia.com> wrote: > On Sun, 01 Oct 2000 15:39:25 -0700, Netscape User > <your_namel@email_address.net> wrote: > > >My workplace recently got an AVNETmarshall Xilinx Development System > >(Virtex300-BG432 mounted on a PCI-64bit card.) The board is advertised > >as capable of running in 'standalone mode' (i.e. not plugged into a PCI > >slot), which is how we'll be using it. > > > >Unfortunately, the general purpose I/O header uses an 'exotic' connector > >- Amp #177983-4. I've checked Amp's website, and they list the > >specifications for the connector, unfortunately, no links to other mfgs > >who made sell prefabricated cables. > > > >So my question is, does anyone know where I can get a cable with the Amp > >#177984-4 on one end, and a 'standard pin header' on the other end? By > >standard-pin-header, I mean any kind of connector type which doesn't > >require an exotic mating connector. For example, an IDE connector would > >be perfect (except it's only 40 pins instead of 100.) > > I'd be very much interested in a cable with the AMP header too. > > Muzaffer > That AMP connector is a board-to-board 0.8mm pitch job, so you will not find a cable that fits it. This sounds like a good time to vent some steam in the direction of whoever designed a prototypng board with a 0.8mm pitch connector on it. It's actually not too hard to make fine-line PC boards in one's kitchen or lab, assuming that film of the PCB artwork is obtained. GC makes some positive etching boards and supplies that work very well. I've made several boards with 0.65 mm pads, and they came out fine. I was limited more by my software than the etching process. Write to me for further details. --David Forbes Tucson AZ Change spamnet to starnet before replying.
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