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On Mon, 14 Feb 2011 20:05:23 -0500, Steven Hirsch <snhirsch@gmail.com> wrote: >On 02/14/2011 06:08 PM, Mike Harrison wrote: >> On Mon, 14 Feb 2011 06:28:45 -0800 (PST), jack<postbox4jack@gmail.com> wrote: >> >>> Hi, >>> >>> I have a 4 yr old xilinx spartan-3 starter kit which came with a >>> parallel port JTAG programming cable. My desktop with the parallel >>> port died recently. As desktops/laptops no longer ship with parallel >>> port so i am looking for a USB programming cable. However the one >>> available from Xilinx is for 225$ which is pretty steep for me. >>> >>> Any suggestions for alternative cheaper USB JTAG programming cable for >>> xilinx boards ? >>> >>> Regards, >> >> I got one of these recently - not used it yet but build quality looks good - possibly not made by >> Xilinx.... >> http://cgi.ebay.co.uk/Xilinx-FPGA-CPLD-USB-download-Cable-JTAG-/150560914094?pt=LH_DefaultDomain_0&hash=item230e213aae > >Heh. That looks like a knock-off. Not sure about other countries, but it's >possible one could have Customs issues coming into the US. But what's the realistic likelihood of them bothering opening low-value items like this amongst the millions of items in the post?Article: 150826
Hi anyone knows how to connect it? it is still present in the pinout XLS fi= les, but the datasheets have no reference to VCCP. we just soldered XO2 device to our superduper new universal protoboard that= allows any pad of the TQFP144 to be "routed" to any of 12 global spines by= using 0 ohm 0603 components. to our big surprise the XO2 did wake up alive instantly and is responding t= o JTAG ID query too, well VCCP is in air still. we are waiting diamond 1.1 to finish download, maybe the XO2 gets programme= d at once, or then if not we are left with the puzzel about VCCP pin, it is= in same bank as JTAG pins, i assume its is Programming voltage, but should= it be connected to VCC core? or 3.3V no idea :( AnttiArticle: 150827
On 2/14/2011 5:35 PM, glen herrmannsfeldt wrote: [snip] > Okay, but consider even the 7493, pretty early in the TTL line. > That is, if I remember right, a loadable synchronous up/down counter. > On any clock cycle, you can load a new count, increment, > decrement, or keep the count constant. In your arc sense, > up, down, and stay the same are three arcs into, and out of, > each state. But load allows you to go from any state to any > other state! > That is correct, in the sense that a synchronous load will enable the counter to move wherever we want, but that means we need additional logic for the load signal which cannot be considered part the inputs, since the latter define the event on which the counter should count. When you say up/down and "stay the same", you are including extra logic which would be necessary to describe in order to explain what your counter is doing. >> Strictly speaking I should say that an FSM and a counter are completely >> different objects, sitting on different levels. An FSM is a "way" to >> describe a process such that given the state it is possible to predict >> the next state of the process according to the current inputs. >> A counter can not model anything, it can simply count the number of events. > > It seems to me that counters can be a lot more complex that you > indicate. Note that with an up/down counter, you lose history if > up/down can change, or if load was active. > I agree that counters may be "controlled" in various ways, which will change their behavior. Whenever we change, with a control set of signals (not the set of inputs which will make the counter count), the content of the counter and/or the direction of the counting, we are defining a new moment in time. > -- glenArticle: 150828
On Feb 14, 7:55=A0pm, Gerhard Hoffmann <dk...@arcor.de> wrote: > Am 14.02.2011 15:28, schrieb jack: > > > I have a 4 yr old xilinx spartan-3 starter kit which came with a > > parallel port JTAG programming cable. My desktop with the parallel > > port died recently. As desktops/laptops no longer ship with parallel > > port so i am looking for a USB programming cable. However the one > > available from Xilinx is for 225$ which is pretty steep for me. > > > Any suggestions for alternative cheaper USB JTAG programming cable for > > xilinx boards ? > > You can get low-cost parallel ports for PCI OR PCI-E in your > local mall and stay with the cable that works. > OK, it consumes a slot in your desktop. > > regards, Gerhard I've done this with no problem. XILINX have a proper driver which can use a memory mapped plug and play parallel port, it just works. Surprisingly the ALTERA equivalent insists on a legacy parallel port, IO mapped where Intel put it 20 years ago.Article: 150829
"jack" <postbox4jack@gmail.com> wrote in message news:41144cb8-5026-41ff-8745-c9b3ad8c7dfe@m27g2000prj.googlegroups.com... > Any suggestions for alternative cheaper USB JTAG programming cable for > xilinx boards ? What bothers me with current programming cables is that there are too many lying around not being used. I have a bunch of xilinx originals, some altera clones and a colleague has a lot of damaged ones. In an earlier topic I asked for one that had ESD protection on and got meself one. I don't know if xilinx originals has, but I assume they did (they never broke). I just wanted to advice : make sure you get one with basic protection on the io's. There is a lot of crap out there. And for the parallel port guys:NO! Don't use parallel port if you can avoid it. The parallel port is most likely not there on new pc's and most of the ones I have seen is very bad electronics that can damage both your fpga, interface itself and your pc by a walk on the carpet. It can even be just slightly damaged so that lifetime gets reduced.Article: 150830
Am 15.02.2011 15:51, schrieb Antti: > Hi anyone knows how to connect it? it is still present in the pinout > XLS files, but the datasheets have no reference to VCCP. > > we just soldered XO2 device to our superduper new universal > protoboard that allows any pad of the TQFP144 to be "routed" to any > of 12 global spines by using 0 ohm 0603 components. > > to our big surprise the XO2 did wake up alive instantly and is > responding to JTAG ID query too, well VCCP is in air still. > > we are waiting diamond 1.1 to finish download, maybe the XO2 gets > programmed at once, or then if not we are left with the puzzel about > VCCP pin, it is in same bank as JTAG pins, i assume its is > Programming voltage, but should it be connected to VCC core? or 3.3V > no idea :( > > Antti > > Hm, my copy of ds1035.pdf (advance data sheet, nov 2010) mentions VCCP: VCCP — VCCP – The Programming power supply pin. This pin powers up the programming circuitry for the on-chip Flash memory. Dedicated pins. ThomasArticle: 150831
On Feb 15, 3:12=A0pm, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > And for the parallel port guys:NO! Don't use parallel port if you can avo= id > it. The parallel port is most likely not there on new pc's and most of th= e > ones I have seen is very bad electronics that can damage both your fpga, > interface itself and your pc by a walk on the carpet. It can even be just > slightly damaged so that lifetime gets reduced. I've used lots of parallel port JTAG interfaces (Xilinx, Altera, ARM, etc.) and have never had any problems with them. LeonArticle: 150832
hm.. i also have nov 2010 copy, and ONLY reference it has is: "Removed references to VCCP" !? mystery! AnttiArticle: 150833
unbelievable almost:) first try, all work, leds are on the board.. VCCP is open... AnttiArticle: 150834
On 2/15/2011 3:31 AM, backhus wrote: [snip] > That in a simple counter the past and future states can be predicted > does not disqualify the counter to be an FSM. Never stated that. > We just have the rare situation, that all inputs at all times are > known, since there are none. I didn't understand what you mean about that. What do you mean with "since there are none"? > If we had that information for any other FSM, it would be the same > situation. The unpredictability and unknown state history of an FSM is > just due to the missing knowledge of the input values after reset/pon. > I'm sorry but I didn't get that. The "unpredictability of the history" is somehow hard to explain, since the history is already in the past and there is very little to predict. On the contrary, the lack of knowledge of the previous state in an FSM is due to the fact that a state may be reached throughout several arcs and it would be needed to store all the inputs (iff all the states are controllable!) to understand through which state the fsm went through. You can essentially move only forward in time, never backward (otherwise that would mean the function f, which indeed is a matrix, can be inverted and we know it can not since there is more than one arc to follow backward). > It is not required for an FSM to have multiple arcs going from one > state to another. > Also, it is not required for an FSM to have any output logic at all. > This is called a Medvedev state machine. > I agree, that is why I said "usually" when referring to the output function, since I didn't want to go into a very hazy region of the semiautomatons and stuff like that. To be more precise though, I ought to say that a Medvedev state machine is a state machine where the outputs are the states themselves. Mealy and Moore FSM are nevertheless FSM where the output function is defined and yet they are not a Medvedev state machine. > Your Definition of a counter is ok, but I can't follow your > conclusions. > When the counting value has to change due to an event (which is > normally the clock) you have to store that value. What so special in storing the value? By the way, a clock is a peculiarity of the technology you use, I would say normally you don't count clocks but number of events (which you may, or may not synchronize with an internal clock signal to set the pace of your machine). > That a counter can not model anything also is a claim that's worth > discussion. > What do you mean by "model sth."? A model of "something" is an abstract representation of the behavior of that "something". In the 18th century, prior the studies of mr. Joule, it was believed that a caloric fluid was moving from a hot body to a cold one, changing their temperatures. That is a (wrong) model of a phenomenon. > A counter is a model in itself, since it is limited (Finite). The > number of events is not finite (theoretically). > I don't see the implication between "being limited" and "being a model". A counter cannot be a model, since it doesn't describe anything except itself. While an FSM can describe the behavior of a counter. > Of course a simple counter for itself has no big practical use, but > that holds for most FSMs. > Even a CPU (which, as Glen states too, can be seen as a big FSM or a > bunch of FSMs) is absolutely useless for itself. > It just becomes a sense with attached Interfaces, memory and a > programm A counter for itself may have big practical use, depending on the type of events you are counting, especially when we compare with a fixed time window. The flux of a particular event is the first type of measurement that comes to my mind, distribution may be measured with a counter as well. What you say about the "sense" of an FSM I don't actually get. A communication protocol may (and probably should) be described as an FSM, so here is an example of its great use. An FSM describes exactly what kind of output you should expect once you know the state and the inputs, so for practical use it is of a fundamental importance, since it gives the possibility to predict the behavior of your system. Without the set of inputs and *possibly* a set of output an FSM does not exist. > Many things that need to act repetitively in a sequential order can be > controlled by a counter. > Provided that counting can be done in any binary coding scheme. Why a "binary coding scheme"? Can a counter count in heptadecimal base? I think so. Why this mix between semantic and syntax? > > One more thing about the predictability of a counter. > Due to it's limitation, you can only trace back it's history up to a > certain point. It's initial value. > Before that, you cant tell if it has already counted a number of > cycles, or if it had started at just that time. > And even if it had counted some full cycles before, you can't tell how > many. That information is lost in time. I'm not arguing about the possibility to predict, but about the possibility to know what was the previous state. Formally you can always trace back up to the initial time (by definition time does not exist before the initial time!), this is the only thing you can do and the only you are interested into, otherwise you wouldn't have changed the initial time. > > So there are many arguments (practical and theoretical) that validate > a counter as a (special form of) FSM. > A counter and a FSM happen to be the same iff the FSM has a very peculiar form. The same, by the way, applies to a shift-register, so why nobody advocates for the shift-register rights to be an FSM? A matter of technological discrimination? > Have a nice synthesis Thanks for the time you spent, I appreciated your comments. > Eilert >Article: 150835
On Feb 15, 11:35=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Alessandro Basili <alessandro.bas...@cern.ch> wrote: > > After some study and a lot of discussions with colleagues and friends I > > would like to pin down the reasons why I have always believed that a > > finite state machine (FSM) _is not_ a counter and at the same time try > > to explain why a counter is a very special FSM You have self-contradicted already. FSM stands for Finite State Machine : aka Something with finite states. It does not claim any more than that. There are also many different counters, and counters can be designed using FSM design entry. Counters do not HAVE to include entry paths for all possible binary states, and nor do FSMs It's considered a good idea to have an exit from all possible binary states, but that is up to the designer. Once you have an Up/Down/Saturate/Load/Modulous counter, you also have multiple pathways to your chosen states, and dependent exit states too, so that's Pretty much described most common FSM's. The rest is merely an exercise in semantics. -jgArticle: 150836
On Feb 16, 5:17=A0am, Antti <antti.luk...@googlemail.com> wrote: > unbelievable almost:) > > first try, all work, leds are on the board.. > VCCP is open... > > Antti So Pgm/erase work with floating Vpp ? Perhaps if Vpp is 'surplus' they started allowing if for freedom on Flash cell, but found it can work ok on the usual Vcc, and so internally bond it ? -jgArticle: 150837
Hi everybody. Could you please help me find out which is the most popular VHDL/ Verilog editor, by filling out this poll: http://www.vhdleditor.com/poll I'm not looking for the "best VHDL/Verilog editor" (that would only get a flame war started). I'm just trying to find out which is used more often. So, please go and vote! thanks PhilippeArticle: 150838
> You could use the $39 USB JTAG cable from Digilent, I'm thinking of > getting one. It isn't supported by Impact, but Digilent supplies their > own Adept software for it. The Digilent Cables can, in fact, support iMPACT, ChipScope, and SDK Debugging using a 3rd-party cable plug-in that Digilent provides. There are a few extra steps involved to get it set up, but it does work. Since the $39 cable is USB Full-speed, you might want to consider the $47.95 High-Speed version. Also, it looks like Digilent has a Xilinx-authorized replica of the Platform Cable USB-II since Digilent participates in the Xilinx University Program. The non-Academic price is $129. BryanArticle: 150839
hi YES, VCCP floating, JTAG flashing OK, and FPGA working as well :) pictures here: http://www.flickr.com/photos/trioflex/ AnttiArticle: 150840
Hello All , I am designing a system where I have to transfer a control pulse signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in 100 MHz domain. How to "Stretch" the pulse in the slow domain to get it sampled. Any experience and Ideas will be highly appreciated. thanks VipsArticle: 150841
"Leon" <leon355@btinternet.com> wrote in message news:ab9ed953-b8bc-4ce2-bf9c-f064e91bff24@k7g2000yqj.googlegroups.com... >I've used lots of parallel port JTAG interfaces (Xilinx, Altera, ARM, >etc.) and have never had any problems with them. You could be lucky with your test environment, but my experience with parallel ports is that they work, as long as you dont't change your pc and if you have very kind power supply environments and connections to your board(s). But I have several hours behind me scratching my head because of parallel port interfaces/interfacing and I don't want to see them ever again. Printers left the parallel "printer" port [computer-]ages ago :)Article: 150842
On Feb 16, 9:03=A0am, Vips <thevipulsi...@gmail.com> wrote: > I am designing a system where I have to transfer a control pulse > signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in > 100 MHz domain. How to "Stretch" =A0the pulse in the slow domain to get > it sampled. Use it to enable a toggle flip-flop in the 100MHz domain. Then you have a step-edge that you can resample in your 12MHz clock domain. Obviously this won't work if the 100MHz pulse happens more often than about 6MHz, because you'll need at least two samples in the 12MHz domain to resynchronize and detect the edge (probably three, for comfort and simplicity). If that's the case then you may need to mess around with Gray counters. (Actually the toggle FF is a degenerate case of a Gray counter, with just one bit.) If the 100MHz and 12.5MHz clocks are in fact synchronous (e.g. using a DCM) then the same toggle-to-stretch technique works well, but the resynchronization problem is slightly different - details depend on exactly how the two clocks are related. It's often simpler just to assume that they are unrelated, to save yourself the bother of worrying about those details. Jonathan BromleyArticle: 150843
>Hello All , > >I am designing a system where I have to transfer a control pulse >signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in >100 MHz domain. How to "Stretch" the pulse in the slow domain to get >it sampled. > >Any experience and Ideas will be highly appreciated. > I suggest that you read Mike Stein's article: "Crossing the abyss, asynchronous signals in a synchronous world" from July 24, 2003 issue of EDN magazine, URL: http://www.edn.com/article/CA310388.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150844
On 2/16/2011 9:03 AM, Vips wrote: > Hello All , > > I am designing a system where I have to transfer a control pulse > signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in > 100 MHz domain. How to "Stretch" the pulse in the slow domain to get > it sampled. > > Any experience and Ideas will be highly appreciated. > > thanks > > Vips Dear Vips, Design your system with only a 100MHz clock. Make a signal which is high for one in eight cycles of the 100MHz clock. Use this to clock enable all the FFs in what used to be your 12.5MHz domain. HTH. Syms.Article: 150845
There is a paper at Sunburst Design called Clock Domain Crossing (CDC) Design & Verification which may be of some help. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150846
All, I am teaching an intro digital logic lab. In past semesters I used the final assignments to introduce students to structural Verilog netlists using Spartan 3E boards. As the class size has outgrown my Spartan boards and I feel that a modern FPGA is overkill for the simple circuits they are building, I am looking for a different solution and would appreciate your suggestions. My goals: (1) A cheap reprogrammable PLD / FPGA (~$10 or less), (2) A DIP package suitable for use in a breadboard, and (3) A simple tool suite that supports an HDL (preferably Verilog). Are these mutually exclusive desires? I am willing to tolerate an expensive programmer. Thanks! StephenArticle: 150847
Bryan <bryan.fletcher@avnet.com> wrote: >> You could use the $39 USB JTAG cable from Digilent, I'm thinking of >> getting one. It isn't supported by Impact, but Digilent supplies their >> own Adept software for it. > > The Digilent Cables can, in fact, support iMPACT, ChipScope, and SDK > Debugging using a 3rd-party cable plug-in that Digilent provides. > There are a few extra steps involved to get it set up, but it does > work. Since the $39 cable is USB Full-speed, you might want to > consider the $47.95 High-Speed version. > > Also, it looks like Digilent has a Xilinx-authorized replica of the > Platform Cable USB-II since Digilent participates in the Xilinx > University Program. The non-Academic price is $129. > > Bryan I've been using the XUP cable for a few months now, and I have no complaints. A bit pricy, but I wanted a cable that works with impact under Linux. I got the academic price, though.Article: 150848
Stephen Sounds like you want either a mid range CPLD or a low end FPGA. We don't do it as DIL but have a look at what we do on our Polmaddie family. Headers are all 0.1 inch/2.54mm aligned. Devices on these are chosen for cost and to fit the 2 layer PCB target we had to keep costs down. Details of this family http://www.enterpoint.co.uk/polmaddie/polmaddi= e_family.html. Maybe too complicated but also look at http://www.enterpoint.co.uk/component_replacements/craignell.html. All of these solutions are supported by free, or low cost, software and we have reasonable cost programmers for most of them. If you have a large class it's also viable to do something semi-custom depending on what you need. John Adair Enterpoint Ltd. On Feb 16, 4:08=A0pm, "stephen.cra...@gmail.com" <stephen.cra...@gmail.com> wrote: > All, > > I am teaching an intro digital logic lab. In past semesters I used the > final assignments to introduce students to structural Verilog netlists > using Spartan 3E boards. > > As the class size has outgrown my Spartan boards and I feel that a > modern FPGA is overkill for the simple circuits they are building, I > am looking for a different solution and would appreciate your > suggestions. > > My goals: > (1) A cheap reprogrammable PLD / FPGA (~$10 or less), > (2) A DIP package suitable for use in a breadboard, and > (3) A simple tool suite that supports an HDL (preferably Verilog). > > Are these mutually exclusive desires? I am willing to tolerate an > expensive programmer. > > Thanks! > StephenArticle: 150849
"Vips" <thevipulsinha@gmail.com> wrote in message news:b95be8ab-c3fd-47a0-bd00-ac0f3a73c9de@o7g2000prn.googlegroups.com... > Hello All , > > I am designing a system where I have to transfer a control pulse > signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in > 100 MHz domain. How to "Stretch" the pulse in the slow domain to get > it sampled. > > Any experience and Ideas will be highly appreciated. > > thanks > > Vips Do it this way (this is the basic idea, neater with a strobed system, plus look after the possible SR conflict) http://tinypic.com/r/10zo1ow/7 Phil
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