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On Feb 10, 3:05=A0am, Emanuele C <emanuele83katam...@googlemail.com> wrote: > I didn't think about the generation of a clock enable. I would like to av= oid it, as xilinx pointed out in its webseminar it is always a good choice = to use a pipeline when the clock enable is used, but in my case, beeing the= code implementing a synch state machine is maybe better that a one hot enc= oding recognize the "loop" condition. I mean, I think it is better to avoid= clock enable when a state machine waits for another signal to switch to th= e following state... > > so.. > > > when current_state =3D> > > =A0 =A0if nBLAST =3D '0' then > > =A0 =A0 =A0 =A0 state_m_plx <=3D next_state; -- conclude the nREADY seq= uence > > =A0 =A0else > > =A0 =A0 =A0 =A0 state_m_plx <=3D current_state; -- remain here until BL= AST > > =A0 =A0if; Like I said, you don't know that this code won't produce a clock enable. The only way to tell is to look at what the synthesis tool produces. I don't know what Xilinx said that made you think a clock enable is a bad thing. I expect they said you will need clock enables when designing a pipeline. That doesn't mean they are bad any other time. They can actually help speed up an implementation. Can you explain what you think will happen if you allow a clock enable on the FSM? RickArticle: 150776
I think the Vitesse parts have the same problem as Marvell in terms of small quantity availability and NDAs for datasheets. Both these manufacturers have very good parts and pricing if you can persist long enough to get a design together. Those are the only reasons we don't use them in products. We have the necessary NDAs in place but we can't tell out customers any of it and how to use the parts because of the NDAs that we have in place. My opinion is they lose a lot of business because of that but that is their management choice. It's like been given the latest Ferrari for nothing without the keys to start it. John Adair Enterpoint Ltd. On Feb 10, 9:46=A0am, Allan Wang <alla...@gmail.com> wrote: > What about the VSC8601? How come it is so cheap compared to the > DP83865DVH? Forgive my lack of knowledge, but are PHY's mostly > compatible with each other? > > Thanks, > Allan > > On Feb 10, 3:12=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > Look at DP83865DVH available in Digikey. Most gigabit phys are a real > > problem to buy in small numbers and even worse to get a datasheet. > > It's probably not the best part but we use this one because datasheet > > is in the public domain and our customers can get the datasheet. It's > > also easy to get. > > > John Adair > > Enterpoint Ltd. > > > On Feb 10, 5:18=A0am, Allan Wang <alla...@gmail.com> wrote: > > > > On the topic of gigabit ethernet PHY's, where can one obtain prototyp= e > > > quantities of them? I can't find any on Digikey. Which manufacturers > > > and models are recommended? > > > > Allan > > > > On Feb 9, 11:25=A0pm, John Miles <jmi...@gmail.com> wrote: > > > > > One other drawback to the Atlys is their use of a gigabit-Ethernet = PHY > > > > that requires a signed NDA before the vendor (Marvell) will let you > > > > see the data sheet. =A0That means no open source development can > > > > (legally) be conducted with this board, at least as far as Ethernet > > > > connectivity is concerned.* =A0Why a company with Digilent's tradit= ion > > > > of hacker-friendliness went with a vendor like Marvell, I can't beg= in > > > > to guess. > > > > > It's a really nice development board otherwise. =A0I was disappoint= ed to > > > > see the Marvell part on there, and told them as much. > > > > > *:Yes, a copy of the data sheet stamped with "Marvell Confidential" > > > > and someone else's NDA number can be downloaded from various source= s. > > > > No, that's not a good substitute for a legally-unencumbered design. > > > > > -- john, KE5FXArticle: 150777
On Thu, 27 Jan 2011 19:12:12 -0800 (PST), KK6GM <mjsilva@scriptoriumdesigns.com> wrote: >Newb question: suppose I want to create a shift register that's >clocked from an external source (like an SPI slave device). >But what if the clock is not slow WRT the fast clock? What if the >external clock is too fast to reliably sync with the fast clock? e.g. >a 20MHz clock and a 50MHz fast clock. In that case it seems that the >external clock needs to be used directly, but won't there be potential >clock skew problems using a regular input as a clock? I'd appreciate >insight on how such problems are dealt with, if indeed they are even >problems at all. Some good suggestions here. One other approach is to derive a faster clock from the 50MHz one, most easily using a DCM or PLL (to 100 or 200MHz) and sample the serial clock and data from that. The timing analysis tools will automatically account for any phase/jitter differences between input and derived clocks. - BrianArticle: 150778
On Feb 10, 4:51=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > Speaking of alternative ways... I should tell you about my latest project= , a > bi-"linear" image scaler (up+down) with very wide scaling range (and > tweakable "linear" function for improved image on large scaling factors). > > This is mainly developed in OPENOFFICE CALC! :) And I do the simulation i= n > real-time as I correct formulas. I make sure to write formulas in a logic > style, so it can be translated to vhdl. > > I can now put pixels into a cell area to simulate the input image, and I = get > an area with the output image (hex values, cause the spreadsheet can't tu= rn > rgb values into cell colors (yet)) > I'm about to translate the formulas into vhdl and simulate a bit to verif= y > that the result matches with the spreadsheet (that means I've translated = the > spreadsheet correctly into vhdl). It turns out to work very well so far. > > What would do this a lot simpler is if the spreadsheet could do these sim= ple > things: > -Take formula parameters with labels from the row above. Now it can only > work with labels from the current row, unless you want to write some comp= lex > offset functions in there, but that will make the formula unreadable. > -color a cell from RGB values (would give REAL images as test data) > > To improve my current situation I could probably make a seperate sheet na= med > 'prev' for the previous variables and access the previous states with a > prev.<label>, but that would require me to pay extra attention when > inserting or deleting columns. I guess I cold easily make some conditiona= l > formatting that would help me detect if the columns were out of sync, so = I > may try that to make it even simpler. Maybe some scripting of the openoff= ice > would help you translate the sheet directly to some other hdl format that > FPGA tools can work on. > > Now, what irritates me is that there is no FPGA adapted tool that would w= ork > this way. In my head I can visualize how it should work, and it would be > very similar to a spreadsheet, and you could even get real time informati= on > about fan-outs (non optimized of course), signal type (combinatorical or = FF > or other blackboxes). If the days had more hours, I would start coding it > myself :) > > [In the end I also plan to do two pixels pr clk for high bandwidth suppor= t > :) ] What exactly does the spreadsheet do that you can't do in an HDL simulation? The array calculations would be very easy to do in a loop so that you only need to write the formula for the cell once and it can be iterated over as large an array as you wish. You could even write the data out to a file to be read into another program that displays the results as an image. RickArticle: 150779
On Tue, 01 Feb 2011 10:31:22 -0600, "sebas" <tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: >Hi, > >Sorry if I'm posting a little bit out of topic here but I'm kinda confused. >I read about the PCIe protocol, I read the Xilinx documentation about their >PCIe EP and I have a quesstion: I understand that the CPU, through the RC, >controls the transfer (issuing a read or write command) but how does the >processor know when to issue the read command? I mean if I have a memory, >on the EP side, that is updated every lets say 3 sec with new data how do I >read the new data: does the software on the CPU side have to make read >requests every 3 sec or does the EP signal an interrupt every time new data >is available, or...? > Given this specification I wouldn't even bother with interrupts. I would have the host CPU read a status register sufficiently often (say twice a second, or even faster!) and read the actual data whenever a "ready" bit was set in the status register. The CPU can then write a register (possibly the same status register) to clear the "ready" bit until next time. - BrianArticle: 150780
"rickman" <gnuarm@gmail.com> wrote in message news:81397eb3-d6c4-40f9-8201-ddeafa666456@y12g2000prf.googlegroups.com... >What exactly does the spreadsheet do that you can't do in an HDL >simulation? The array calculations would be very easy to do in a loop >so that you only need to write the formula for the cell once and it >can be iterated over as large an array as you wish. You could even >write the data out to a file to be read into another program that >displays the results as an image. Here are some. -openoffice is free. Compare that to any other simulator package. Of course at this stage I need to verify my stuff with a proper simulator. -Its much faster to change something and see the result instantly. -I find the syntax is easier. I don't have to worry about pleasing the vhdl at design time, and can focus on the function rather than spelling and formatting. I can worry about that at implementation phase. -Moving data between apps and files are slowing me down (at design time).Article: 150781
Hi to everybody in this newsgroup. I'm Diego from Milan, Italy..yes ...very close to the funny house of that (in)famous minister that all the word (except some italians) laughs about. .I'm not much more than a newbie in VHDL and FPGA programming. At the age of 47 i'm practicing by myself about FPGAs . Instead of using an educational board i'm trying to build some stuff using a board from scrap mounting an Altera Cyclone device connected to a 29LV400 Flash and to a static RAM,and this is part of what i exactly need for my purposes.2 JTAG connectionsAre available,for configuring the FPGA directly or through an EPCS1 configuration memory. It would be a saving of time for me if i could easily load some data from a file to the 29LV400 Flash via the JTAG connector.So i read about ParallelFlashLoader IP but i' m not understanding if it is what i need.Should i generate the PFL entity and simply connect it as a component in the main project? I would like to find some step by step example that fits on my situation or just be warned if that kind of flash memories can't be programmed by this tools. Forgive me if the question was not properly asked due to my poor knowledge of the matter and of english language. Thanks in advance even just for reading the above. DiegoArticle: 150782
On Feb 9, 3:46=A0pm, "mcholbi" <miguel.cholbicollados@n_o_s_p_a_m.aes- aero.com> wrote: > Hello everyone, > > We have got a new project in my company. It's about a controller based in= a > FPGA. For several reasons we have decided to use Actels FPGAs to implemen= t > it. For designing the PCB we use Altium Summer 09. > > Our doubt is now if using Altium to design the FPGA too or use Libero fro= m > Actel. We like Altium because of the synchronisation of pins and the > possible integration in the PCB simulations, in addition it looks better = as > Libero to print planes, and in reality it makes use of the vendor tools > (Synplify and Designer) in batch mode. In addition it allows easier > portability to another devices. The problem is that we have found massive > problems to compile some projects that made use of some special features = of > the FPGA, for example the integrated ADC. The program crashes when > compiling or even when executing usual tasks. In addition there are some > error in the libraries for our FPGA, ports names for example (it is fixed > very easy). Simulations (post-synthesis, post-layout) are also easier wit= h > Libero. > > In Altium they have told us that in next version (AD10) the demo project > that we have sent them doesn't make the program crash but we haven't test > the synthesis, P&R... This version will be released next week when they f= ix > some problem they are having. > > I would like to know your opinion about this. Do you have any experience > with Altium? Would you use a non-vendor tool to design your FPGA? We thin= k > that maybe Altium looks very good (the idea, the results...) but maybe it > isn't reliable enough to handle our big project. > > Thanks for your att, best regards, > > Miguel Cholbi > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com FWIW, Altium hasn't made a profit for the last few years, despite slashing their prices last year.Article: 150783
I have used Altium for a few years for pcb design and find it very good. They seem to release updates quite regularly with bug fixes and new components. I havent used it for fpga design as I use HDL Designer so can't comment on what it is like for that. Not sure it should matter what profit the company has made to how good the product is. There are a lot of very big companies with rubbish products. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150784
On 1/28/2011 12:13 AM, KJ wrote: > On Jan 27, 10:12 pm, KK6GM<mjsi...@scriptoriumdesigns.com> wrote: >> >> But what if the clock is not slow WRT the fast clock? What if the >> external clock is too fast to reliably sync with the fast clock? e.g. >> a 20MHz clock and a 50MHz fast clock. In that case it seems that the >> external clock needs to be used directly, but won't there be potential >> clock skew problems using a regular input as a clock? I'd appreciate >> insight on how such problems are dealt with, if indeed they are even >> problems at all. >> > > They are a problem that in many cases is dealt with using a dual clock > fifo. > > KJ Concerning the dual clock fifo: to which domain should belong the "fifo full" and "fifo empty" status registers? AlArticle: 150785
Thanks for the info, guys! I'm seeing a lot of Xilinx stuff. What are your thoughts on Altera in terms of hardware and synthesis tools? Thanks again! :) >I've been doing digital design for awhile now both in class and in my co-op >terms. I work with FPGAs pretty regularly. However, I have some side >projects in my head that I want to work on, so I'd like a board for my >personal use. Projects that may require a bit more kick. DSP, embedded >processor design, maybe even ANN, etc. > >I don't really want to spend any more than, say, $500. So I've been looking >at the following dev kits: > >DE2-115 (Cyclone IV) >http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502 > >and > >Atlys (Spartan 6) >http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS > >I admit I haven't used the Altera tool set, but at the end of the day its >the hardware and synthesis quality that matters. > >I'm also open to other suggestions, of course. Anyone have experience with >these low-cost development kits and chips? > >Any and all help is greatly appreciated! :) > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150786
Generally speaking there are about 10x Xilinx dev boards for every Altera dev board. Don't ask me why because the market sizes are not that different. Possibly as a result of that there are not that many Altera boards in the lower cost end. We have a very low cost board in Polmaddie2 but that's only a CPLD and below the level you are looking for. Our next Altera product will probably be just outside your upper end so we probably won't have anything in the middle until we do a Cyclone V board. John Adair Enterpoint Ltd. On Feb 10, 7:28=A0pm, "Caeliferum" <chatthak@n_o_s_p_a_m.n_o_s_p_a_m.uoguelph.ca> wrote: > Thanks for the info, guys! > > I'm seeing a lot of Xilinx stuff. What are your thoughts on Altera in ter= ms > of hardware and synthesis tools? > > Thanks again! :) > > > > > > >I've been doing digital design for awhile now both in class and in my > co-op > >terms. I work with FPGAs pretty regularly. However, I have some side > >projects in my head that I want to work on, so I'd like a board for my > >personal use. Projects that may require a bit more kick. DSP, embedded > >processor design, maybe even ANN, etc. > > >I don't really want to spend any more than, say, $500. So I've been > looking > >at the following dev kits: > > >DE2-115 (Cyclone IV) > >http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&Ca.= .. > > >and > > >Atlys (Spartan 6) > >http://digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,836&Prod=3DAT= LYS > > >I admit I haven't used the Altera tool set, but at the end of the day it= s > >the hardware and synthesis quality that matters. > > >I'm also open to other suggestions, of course. Anyone have experience > with > >these low-cost development kits and chips? > > >Any and all help is greatly appreciated! :) > > >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > >Posted throughhttp://www.FPGARelated.com > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150787
On Feb 10, 11:14=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Not sure it should matter what profit > the company has made to how good the product is. Companies that don't make a profit over the long term go out of business. KJArticle: 150788
On Feb 10, 12:01=A0pm, Alessandro Basili <alessandro.bas...@cern.ch> wrote: > > KJ > > Concerning the dual clock fifo: > to which domain should belong the "fifo full" and "fifo empty" status > registers? > Fifos can only become full when written to. Therefore, 'fifo full' should be computed in the 'write clock' domain. Fifos can only become empty when read from. Therefore, 'fifo empty' should be computed in the 'read clock' domain. Generally, these are the proper clock domains for the logic that interfaces to the FIFO that would have need of these status signals. KJArticle: 150789
In article <311b9cbf-426b-4e86-8d8a-1ad293d4b018@8g2000prt.googlegroups.com>, KJ <kkjennings@sbcglobal.net> writes: >On Feb 10, 12:01=A0pm, Alessandro Basili <alessandro.bas...@cern.ch> >wrote: > >> > KJ >> >> Concerning the dual clock fifo: >> to which domain should belong the "fifo full" and "fifo empty" status >> registers? >> > >Fifos can only become full when written to. Therefore, 'fifo full' >should be computed in the 'write clock' domain. >Fifos can only become empty when read from. Therefore, 'fifo empty' >should be computed in the 'read clock' domain. Right, but they become un-full on the read clock. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 150790
> One other drawback to the Atlys is their use of a gigabit-Ethernet PHY > that requires a signed NDA before the vendor (Marvell) will let you > see the data sheet. That means no open source development can > (legally) be conducted with this board, at least as far as Ethernet > connectivity is concerned.* Why a company with Digilent's tradition > of hacker-friendliness went with a vendor like Marvell, I can't begin > to guess. You're right - I should have mentioned that as a huge drawback. You need to register with Marvell's extranet. Their legal team is then meant to contact you with an NDA. Unfortunately I've not heard back from them, two months on. Their Web site advises that you contact your local distributor (in Australia, in my case) for help, but I haven't heard back from them either! An attempt to contact them through their contact form just resulted in a generic, unhelpful form response, a few weeks later. Hopeless! Unfortunately, Digilent didn't have any tips or a Marvell contact to try. JoelArticle: 150791
On Feb 10, 5:59=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > In article <311b9cbf-426b-4e86-8d8a-1ad293d4b...@8g2000prt.googlegroups.c= om>, > > =A0KJ <kkjenni...@sbcglobal.net> writes: > >On Feb 10, 12:01=3DA0pm, Alessandro Basili <alessandro.bas...@cern.ch> > >wrote: > > >> > KJ > > >> Concerning the dual clock fifo: > >> to which domain should belong the "fifo full" and "fifo empty" status > >> registers? > > >Fifos can only become full when written to. =A0Therefore, 'fifo full' > >should be computed in the 'write clock' domain. > >Fifos can only become empty when read from. =A0Therefore, 'fifo empty' > >should be computed in the 'read clock' domain. > > Right, but they become un-full on the read clock. > Generally speaking, becoming 'un-full' on a dual clock fifo is not a concern. Writing to a full fifo is not recoverable, data has been lost. At best a status bit gets set reporting this error. For that reason, the *setting* of 'fifo full' status must always be accurate and must therefore always be synchronous to the write clock. The resetting of 'fifo full' (i.e. fifo becoming 'un-full') which happens during a fifo read is less important to be accurate on any particular clock cycle. All that is incurred is latency before the write side is able to again start writing which can be designed for by sizing the fifo appropriately to account for the latency in transferring the read request from the read clock domain over into the write clock domain. Assuming that the fifo is sized to account for the known latency, then no error occurs. The same logic applies to having to always be accurate about setting 'fifo empty' relative to the read clock but being allowed to be later about resetting (i.e. becoming 'un-empty') when a write occurs. Kevin JenningsArticle: 150792
On Feb 8, 4:03=A0pm, "kolar" <kamleshrr@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Looking for a Level shifter to support the following: > 1. One side voltage is 3.3. (since I am interfacing with FPGA I am ok if > its 2.5V or 1.8V as well) > 2.Other side needs to support both 3.3V/2.9/2.8V and 1.8V > 3.200MhZ speed support is required on the IOs. > > Any help will be great. > Thanks > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Look at Maxim site: http://www.maxim-ic.com/app-notes/index.mvp/id/3007 You can check with other vendors as well. -- JKArticle: 150793
National may be the ONLY vendor of networking chips that doesn't require an NDA for datasheets. I know that Marvell and Broadcom are extremely hard to extract data from, even after you've signed the NDA. I get partial access to their data, and have to request access to new parts or groups of parts. Still the Marvell parts are used on most of the Digilent boards and I've used them in our products as well. They are relatively easy to work with once you get the datasheet, so the lack of other support is not a big issue (especially after using the basics from the Digilent board designs). -- GaborArticle: 150794
On Feb 10, 9:06=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:81397eb3-d6c4-40f9-8201-ddeafa666456@y12g2000prf.googlegroups.com... > > >What exactly does the spreadsheet do that you can't do in an HDL > >simulation? =A0The array calculations would be very easy to do in a loop > >so that you only need to write the formula for the cell once and it > >can be iterated over as large an array as you wish. =A0You could even > >write the data out to a file to be read into another program that > >displays the results as an image. > > Here are some. > -openoffice is free. Compare that to any other simulator package. Of cour= se > at this stage I need to verify my stuff with a proper simulator. FreeHDL -http://freehdl.seul.org/ GHDL - http://ghdl.free.fr/ GPL Cver - http://sourceforge.net/projects/gplcver/ Icarus Verilog - http://en.wikipedia.org/wiki/Icarus_Verilog There are others... > -Its much faster to change something and see the result instantly. I guess that depends on what you mean by "instantly". I'm not clear on what it takes to edit your spreadsheet. I have built large arrays in spread sheets and found the editing to be the PITA part. As you mention in your earlier post there are things you have left out because typing them in would be very tedious. There are times that I have done parts of the calculations on another worksheet and let the user interface sheet link to the results. Still, it can get very messy to edit. > -I find the syntax is easier. I don't have to worry about pleasing the vh= dl > at design time, and can focus on the function rather than spelling and > formatting. I can worry about that at implementation phase. To each his own. I find the spreadsheet language to be very verbose for anything beyond the fairly simple calcs. > -Moving data between apps and files are slowing me down (at design time). I'm not sure I understand this. In an HDL you are working 100% in the final language. I'm not trying to criticize your method. I just don't understand it exactly. But I do appreciate the degree of interactivity you can get using a spread sheet. I often use it for evaluating what if type things. But I give up when the work gets too complex. Recently I even entered a cyclical calculation that the spreadsheet complained about, then went on to recalculate repeatedly in order to find convergence. I hadn't known you could use it that way. But when the convergence blows up, I get no info on why... just like any other simulation. RickArticle: 150795
I am using one of the built in fifo18 components and are having a small problem with the rst. I am using it in async mode and so would expect the rst to be async. When I P&R the design in ISE 12.4 it tries to time the reset to the rd clock. It uses the parameter Trrec_RST which I cant find in the datasheet. Not sure if this is a bug or something I am missing. Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150796
On 02/04/2011 12:10 PM, Nico Coesel wrote: > > IMHO schematics are bad. Most designs are becoming pretty complicated > these days. If you still think in logic then you'll lose oversight at > some point. With VHDL I have learned not to think in logic but think > in functions. Parallel functions to be exact. > Yes, I have come around to this view. I started out with CPLDs like the Xilinx 9500 series, and a schematic could express what I was doing there quite succinctly. I was happy with these, but hated the Ghastly Aldec schematic editor that Xilinx Foundation used at the time. I worked up a way to make structural VHDL from my preferred schematic/PCB editor (Protel99 SE). this required hand editing for some small things, but mostly worked, but the library parts (4 bit counter and the like) provided by Protel were a GHASTLY hack-job and full of errors of the sort where a needed junction (wire dot) was left out, so only one FF of the 4 was clocked. So, I had to find and fix all those goofs. But, as the stuff I did in FPGAs grew in complexity, schematics got more and more unwieldy. Migration away from Aldec to several generations of incompatible schematic packages also made things more difficult. I have a number of legacy designs that I continue to make improvements on and migrate to newer FPGA families. I have converted many of the sub-sheets to behavioral VHDL, and now do anything new in VHDL. I am in St. Louis, MO, so midway between the coasts. I pretty much do all this work in isolation, so there's no corporate cultural bias here. VHDL was more "open" back when, meaning more books were available at the library giving design strategy help, so that's what I learned to use. I can see that Verilog is a LOT better if you are doing a lot of arithmetic operations mixed with logical stuff, but the syntax still seems a bit strange to me. I have done some stuff that had arithmetic and addition/subtraction of values in VHDL, and once I got the basic syntax for type conversion, it wasn't bad at all. I kind of worry when languages are making a lot of assumptions about what I'm trying to do, I don't mind having to be a bit specific. JonArticle: 150797
In article <3292f4d0-26e9-44fe-9b09-2904190036e0@w36g2000vbi.googlegroups.com>, KJ <kkjennings@sbcglobal.net> writes: >On Feb 10, 5:59=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal >Murray) wrote: >> In article <311b9cbf-426b-4e86-8d8a-1ad293d4b...@8g2000prt.googlegroups.c= >om>, >> >> =A0KJ <kkjenni...@sbcglobal.net> writes: >> >On Feb 10, 12:01=3DA0pm, Alessandro Basili <alessandro.bas...@cern.ch> >> >wrote: >> >> >> > KJ >> >> >> Concerning the dual clock fifo: >> >> to which domain should belong the "fifo full" and "fifo empty" status >> >> registers? >> >> >Fifos can only become full when written to. =A0Therefore, 'fifo full' >> >should be computed in the 'write clock' domain. >> >Fifos can only become empty when read from. =A0Therefore, 'fifo empty' >> >should be computed in the 'read clock' domain. >> >> Right, but they become un-full on the read clock. >> > >Generally speaking, becoming 'un-full' on a dual clock fifo is not a >concern. Writing to a full fifo is not recoverable, data has been >lost. At best a status bit gets set reporting this error. For that >reason, the *setting* of 'fifo full' status must always be accurate >and must therefore always be synchronous to the write clock. > >The resetting of 'fifo full' (i.e. fifo becoming 'un-full') which >happens during a fifo read is less important to be accurate on any >particular clock cycle. All that is incurred is latency before the >write side is able to again start writing which can be designed for by >sizing the fifo appropriately to account for the latency in >transferring the read request from the read clock domain over into the >write clock domain. Assuming that the fifo is sized to account for >the known latency, then no error occurs. > >The same logic applies to having to always be accurate about setting >'fifo empty' relative to the read clock but being allowed to be later >about resetting (i.e. becoming 'un-empty') when a write occurs. > >Kevin Jennings The key idea is that full and empty aren't really synchronous with either read or write clock so you can't just feed them into a FSM and expect things to work if the tools don't complain. If you are smart enough, you can think about the issue and use the going-full path without the delay of a synchronizer as long as you are careful about the un-full path. One solution in some cases is to use an almost-full flag. You can run it through the classic synchronizer and the delay won't kill you. If it's not almost-full, you can write at full speed, knowing it won't go full before the signal gets through the synchronizer. If it is almost-full, you can go slow enough to let the full flag get through a synchronizer. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 150798
On Feb 11, 5:45=A0am, Gabor <ga...@alacron.com> wrote: > National may be the ONLY vendor of networking chips > that doesn't require an NDA for datasheets. =A0I know > that Marvell and Broadcom are extremely hard to extract > data from, even after you've signed the NDA. =A0I get > partial access to their data, and have to request > access to new parts or groups of parts. > > Still the Marvell parts are used on most of the > Digilent boards and I've used them in our products > as well. =A0They are relatively easy to work with > once you get the datasheet, so the lack of other > support is not a big issue (especially after using > the basics from the Digilent board designs). > > -- Gabor The Micrel KSZ9021RL PHY is openly documented, and seems to be working out well for the HPSDR guys ( http://openhpsdr.org/wiki/index.php?title=3DM= ETIS ). I bought one of their eval boards awhile back but haven't had time to do anything with it. Haven't heard much about National's gigabit PHY options, one way or the other. -- john, KE5FXArticle: 150799
I have been working on the hardware implementation design of LDPC decoders, that trade-off neatly on the area vs. performance grounds, and were interested in evaluating and comparing the performances of the LDPC Decoder IP Cores available out there. I have checked out the core available on opencores.org, but there is not enough documentation details provided for that. I am looking for and would really appreciate if anyone could point me in the direction from where I maybe able to obtain an LDPC decoder IP core, for trial or evaluation purposes (initially - I'm open for later on purchasing the core also considering its performance and integration with the system). It doesn't matter for which standard the core has been implemented (802.3an or WiMax or DVB S2). Thank you! Regards, Ares.
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