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what is the difference in using DPRAM instead of RAM for asynchronous FIFO design? Is it necessary to use DPRAM for designing Asynchronous FIFO?Article: 97676
Hi, everyone. I want to do a presentation about the introduction about Xilinx Chipscope on the meeting of my lab. Since I have used this software for not a long time, I need some comments, tips, and other information about Chipscope from you, the veteran designers of Fpga. Any advice would be appreciated very much, and my email is yyqonline@gmail.com. Thanks a lot. yours, YuQing YouthArticle: 97677
Peter Alfke wrote: > Your wish has been granted... Wow ... how did you make 6 years of smaller XC4K, Spartan and Spartan2 boards just disappear?Article: 97678
Peter Alfke wrote: > There are two directions: FPGA to TTL, and TTL to FPGA > Today, all the FPGAs I know still support 3.3 V as I/O supply voltage. > (That may change in the future, for 3.6-V tolerance is not natural or > easy in the best and fastest processes) > TTL-to-FPGA: Old bipolar TTL generally stayed 1 or 2 diode drops below > Vcc, but CMOS variants can swing all the way to Vcc=5.5Vmax. Most FPGAs > do not tolerate >3.6 V on their pins, but most also have a clamp diode > to their own Vcc. If you can rely on that diode, then use 2.5 V or 3.3 > V as Vccio and put a series resistor of 100 or 220 Ohm between the FPGA > and TTL pin, to limit any clamp current. > > FPGA-to-TTL: Usually no problem, since TTL sees anything above 2.4 V as > High. There are, however, "TTL" derivatives with CMOS input thresholds > that might be up to 3.5 V. In that case, you should 3-state the FPGA > output, and use a pull-up resistor to 5 V (relying on the clamp diode > to the 3.3 V Vcco. > This is a slow pull-up, and there is a trick to temporarily enable the > active pull-up to generate the first 2 V of voltage swing. There is also a growing range of Dual-Vcc Translators, to service this market that refuses to die... TI has quite a number now, and I see Philips following them. You need dual supply, if power supply drain is any sort of a convern.The Clamp diode tricks above are simple, but do not do good things to the power drain figures..... > 5V should today be considered an obsolete and awkward supply voltage, > although it has served us well for 40 years.( In a few years, 3.3V will > cause the same grief...) Sorry Peter, but much as the FPGA sector wants 5V to go away, it's still here. In fact, the newest devices from Infineon and Freescale have 5V ports ! Yes, they have lower voltage cores, but that is hidden from the designer. ie, the Silicon vendor takes the trouble! ISTR the Freescale one impressed me, as it appeasrs to not need a core decoupling pin - not sure how they managed that. Why ? - noise immunity, ease of interface : have you ever tried to find a power MOSFET that can be driven from 3.3V ? -jgArticle: 97679
>The XCR board claims to run from a couple of AA batteries for 60 hours. Good AAs are 2800 mA-Hours. 60 hours would be 46 mA. You probably get a net gain if you run through a switching regulator as compared to a LDO. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 97680
On Sat, 25 Feb 2006 19:45:47 -0500, Josh Rosen <bjrosen@polybusPleaseDontSPAMme.com> wrote: >> >> I suspect, but didn't figure it out, that there is a Booth Recoding >> analog for such a divider design. You can use the top bits of the >> remainer to select the shift amount, which cuts the cycles in half for >> a serial design, so I didn't worry it that hard. > >This is the two bit at a time algorithm that I was talking about. Back in >the 70s this was the most cost effective way to implement division. Modern >machines, and FPGAs, have fast multipliers so convergence division is the >best choice today. A very detailed description of a twos complement divide including the management of status flags, and microcode listing for the AM2903 and 29203 bit-slice processor products is documented by AMD in their 2900 data book. You can read about it (and see if I remember correctly) in this PDF file: http://bitsavers.vt100.net/amd/_dataBooks/1979_AMD_2900family.pdf (it is a 32 MB file) on page 2-51 The 32 bit AM29332 and 29C322 non-slice microcoded ALUs also implemented these divide algorithms. (PDF at same site). I think though that these are 1 bit at a time algorithms. These chips did do 2 bit at a time modified-Booth multiplies. Another source of info on these multistep algorithms would be the AM29000 RISC processor documentation, that had both multiply and divide step instructions. Philip FreidinArticle: 97681
Hi, I am trying to create a Xilinx Core Generator multiplier for Virtex 4 with RPM constraints. However, neither ISE 7.1 (IPCore 7.1) nor ISE 8.1 (IPCore 8.0) allows creation of Virtex 4 multiplier with RPM constraints, even if multiplier is completely LUT based. Such constraints on multiplier are allowed in Virtex 2. What is the reason for this limitation in Virtex 4? I wanted some multipliers in my design to have similar shapes and to not get mixed with other components in different shapes. Is there a way to provide such constraints in ucf file? Thanks in advance.Article: 97682
Luc Thanks for your thoughts, and to everyone else for that matter. It is actually a personal project of mine so I am free to use whatever device I need. I think I may go with a Xilinx device but at the moment not sure which one. Think I will probably do some simulation in ISE first to see which device is the best for this application. JonArticle: 97683
Hal Murray wrote: > My guess is that the TCP implementation on your PPC is > dumb/simple and only allowing one un-ACKed packet at > a time. That works, but won't go fast unless the other > end cooperates. It makes the software a lot simpler. > That is my feeling too, I'll give LwIP a chance when time permits. Xilnet is quite under developed, and that is a fact. /Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defense Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 97684
Duccio I will take on board what everyone else has said and say that a CPLD like Coolrunner2 is the best chance of low power. However sometimes CPLDs are not big enough for what you want to do. Another thing to say is that the static currents in a SRAM technology based FPGA like Xilinx or Altera parts will eat most of your power budget if not exceed it. Some of more fringe parts from Lattice, Quicklogic and Actel will do better in this respect so might be worth looking there if it is a FPGA you need. The downside of these manufactures is that they don't have the same range of development boards available to choose from but you may be lucky and find exactly what you need. To give you some real numbers with Xilinx parts we have seen our Broaddown2(BD2-400- Spartan-3 XC3S400) operating at about 120mA at 5V input. These are real numbers to give you an idea. We have seen x2 and x3 than that with some general designs. Our regulator chain is totally made up of linear regulators so the current seen at the input represents the sum of all currents used on the board. Another point to watch is that your minimum voltage is less than most of the CPLDs out there will operate down to. FPGAs like Spartan-3 do have a core that will operate at 1.2V but given your variance of input voltage you would need a regulator that itself may need a higher voltage than that to regulate. What you may need to do is to have a switching supply to stabilise your solar input before use or given you have a solar input a battery to hold level that charges when you have good sunlight and a decent input level. Given that I don't know what you are trying to do on this design there may be other ways to tackle your power consumption. The first is to consider if your system needs to be working all of the time or could you wake it up for a time to do whatever task then power it off. Given you are asking for EEprom you may be doing this already. If this is the case and your ratio of "on" time to "off" is mainly off then strongly consider the battery method to achieve your needs. Now given those ideas here is my commercial - Raggedstone1 has a 16Kbit serial EEporm on board. Can take more on DIL Headers if standard 3.3V EEprom in DIL package is fitted. This board is Spartan-3 based so my comments about SRAM based FPGAs do apply. I may also able to find and give you one of prototypes of this board with the linear regulators removed or disabled. You could then add your own switching regulators. You would have to the work yourself to build and add the switching regulators but otherwise it won't cost you anything. Enterpoint has a program with the very original name of UAP (University Access Program) where we do try to help institutions and students achieve projects. Details of UAP are here http://www.enterpoint.co.uk/uap/uap.html . John Adair Enterpoint Ltd. - Home of Raggedstone1. The ?75 Student FPGA Development Board. http://www.enterpoint.co.uk "Duccio" <picinotti.duccio@tin.it> wrote in message news:1140906312.786241.73400@z34g2000cwc.googlegroups.com... > Hi, I'm an italian student of Automation Engineering (..sorry for my > academic english...). > It's the first time that I post in this group. I would like to know if > there is some fpga board (I've just used an Altera board for an exam of > > Electronic Digital Systems) that has this requirements: > -low power consuption (for using with a solar panel), less than 100mA > of current consumption at 3.3-1.2 V; > -a non-volatile memory (eeprom...) that contains the "programs" also > when it's extinguished; > -a max cost of about 200 $. > > I thank all of you that can answer to me. > > > Bye > Duccio >Article: 97685
Hi all, Does any of you knows where can I obtain the VGA specification (I believes it is IBM's) ? Thanks in advance, Mordehay.Article: 97686
Hi I 'm a student working with XPS 7.1 and I get this error ERROR:MapLib:482 - Blockram ramb16_s9_s9_0 is a memory mapped blockram generated for the Microprocessor. However it is not connected properly, causing it to be trimmed. Please connect up all memory mapped blockram properly and re-run Ngdbuild. Does anyone know what this error means and what I can do about it, because I haven't found anything on the net about it. Greets MichArticle: 97687
Stephen Craven ha scritto: > Any board out there with a Virtex-II, Virtex-II Pro, or Virtex-4 will > support run-time reconfiguration through the Internal Configuration > Access Port (ICAP). ucLinux can be easily run on a MicroBlaze on any > of these boards and Monta Vista Linux is available on the PPC on many > 2vp boards. > > As for a board that has reference designs supporting partial dynamic > reconfiguration, I know of none that exist. Partial reconfiguration is > not an easy task and, as several other posts will contest to, it is > currently broken in the tools. > My question then is... what do I do with the ICAP component if partial reconfiguration (and thus, in particular, self-configuration, which is partial and dynamic by definition) is not supported by the development tools???? Or, do ICAP-based self-configuring designs actually exist out there? If this is the case, how could I find some examples? Many thanks again pablo > I have heard that Xilinx is working on the problem, as there is growing > demand for this from the Software Defined Radio community. > > StephenArticle: 97688
"pablo" <sec_lab@libero.it> schrieb im Newsbeitrag news:1140966379.138525.199430@i40g2000cwc.googlegroups.com... > Stephen Craven ha scritto: > >> Any board out there with a Virtex-II, Virtex-II Pro, or Virtex-4 will >> support run-time reconfiguration through the Internal Configuration >> Access Port (ICAP). ucLinux can be easily run on a MicroBlaze on any >> of these boards and Monta Vista Linux is available on the PPC on many >> 2vp boards. >> >> As for a board that has reference designs supporting partial dynamic >> reconfiguration, I know of none that exist. Partial reconfiguration is >> not an easy task and, as several other posts will contest to, it is >> currently broken in the tools. >> > > > My question then is... > what do I do with the ICAP component if partial reconfiguration (and > thus, in particular, self-configuration, which is partial and dynamic > by definition) is not supported by the development tools???? > > Or, do ICAP-based self-configuring designs actually exist out there? > If this is the case, how could I find some examples? > > Many thanks again > pablo > > >> I have heard that Xilinx is working on the problem, as there is growing >> demand for this from the Software Defined Radio community. >> >> Stephen > nomans land, no examples, possible by theory only. if you want then its a lot of hard work on pain. sure it depends what you want todo, implementing small changes isnt a problem, just look the locations in the .LL file and rewrite using ICAP but if you want to reload larger part of the FPGA then it comes a major problem AnttiArticle: 97689
Mich wrote: > Hi > > I 'm a student working with XPS 7.1 and I get this error > > ERROR:MapLib:482 - Blockram ramb16_s9_s9_0 is a memory mapped blockram > generated > for the Microprocessor. However it is not connected properly, causing > it to > be trimmed. Please connect up all memory mapped blockram properly and > re-run > Ngdbuild. > > Does anyone know what this error means and what I can do about it, > because I haven't found anything on the net about it. Howdy Mich, When the error message says "... it is not connected properly, causing it to be trimmed." do you have any reason to doubt that the error message is correct? You'll need to go over each signal on the blockram and verify that it is either unneeded or is connected to logic that doesn't get optimized out. Enable pins correct? Output feeds to logic that eventually drives one or more output pins? Etc. Good luck, MarcArticle: 97690
Hi, the strange thing is when I don't add my own module there is no problem when I add a module with the importe/create wizzard there is no problem but when I change the user_logic to what I wont I get this error. Can you explain how this can happen? Greets MichArticle: 97691
Jim Granville wrote: > Sorry Peter, but much as the FPGA sector wants 5V to go away, > it's still here. In fact, the newest devices from Infineon and Freescale > have 5V ports ! <snip> > Why ? - noise immunity, ease of interface : have you ever tried to > find a power MOSFET that can be driven from 3.3V ? If building in 5v tolerance for that reason, why not build for say 9 volt or 15 volt? Even 5v gate drive is marginal for power MOSFETs, in that it's only enough for some parts.Article: 97692
I would be interested in this too. Could you forward me this information too? Thanks, DerekArticle: 97693
On a sunny day (26 Feb 2006 07:45:40 -0800) it happened cs_posting@hotmail.com wrote in <1140968740.868102.127480@p10g2000cwp.googlegroups.com>: >Jim Granville wrote: > >> Sorry Peter, but much as the FPGA sector wants 5V to go away, >> it's still here. In fact, the newest devices from Infineon and Freescale >> have 5V ports ! ><snip> >> Why ? - noise immunity, ease of interface : have you ever tried to >> find a power MOSFET that can be driven from 3.3V ? > >If building in 5v tolerance for that reason, why not build for say 9 >volt or 15 volt? > >Even 5v gate drive is marginal for power MOSFETs, in that it's only >enough for some parts. Yes but at least you can get these. 3.3 V parts, 1.5 V 100% on, are rare. > >Article: 97694
fpga_toys@yahoo.com wrote: > Peter Alfke wrote: > > Your wish has been granted... > > Wow ... how did you make 6 years of smaller XC4K, Spartan and Spartan2 > boards just disappear? Are you trying to be nasty, funny or whatever? I answered your complaint about the alleged lack of cheap boards with dedicated multipliers. I did not make anything older disappear. But those old boards have no dedicated hardware-implemented combinatorial multipliers. That's all. Peter Alfke, from home.Article: 97695
Jim Granville wrote: >> Sorry Peter, but much as the FPGA sector wants 5V to go away, > it's still here. In fact, the newest devices from Infineon and Freescale > have 5V ports ! > > Yes, they have lower voltage cores, but that is hidden from the > designer. ie, the Silicon vendor takes the trouble! Yes, it is possible to make modern ICs 5-V tolerant, while the internal logic operatesoff 1 to 1.5 V. But the high Vcc and thick oxide in the I/O circuits severely reduces their speed. And we see far more of our customers clamoring for high performance than for 5-V compatibility. We try to serve a very broad range of customer requirements, but sometimes we have to make a choice. 5-V tolerance was sacrificed for higher I/O performance and lower power. Peter Alfke, Xilinx ApplicationsArticle: 97696
Maybe you could tell us why shape is important, and why you do not want to use the much faster and more efficient dedicated 18 x 18-bit multiplier circuits? Peter Alfke, Xilinx ApplicationsArticle: 97697
Hi, in general it is a bad practise to align the signal via such delay. So I would recommend to think more about synchronisation of your design (e.g. add addition flops). If you still want to do it (if i correctly understand), you would have to constraint LUTs so the synthesiser will not optimise them away. Regards Alex > I'm looking to create a LUT based delay line for use in aligning DDR > strobes. The target device is a V2P, I have read the application notes > provided by Xilinx on this topic but can't seem to find a reference > design > that illustrates this usage of LUTs. Perhaps someone could point me in > the > right direction. > > Thanks in advance, > > Brendan > > -- AlexArticle: 97698
A dual-port RAM is ideal, because you can dedicate one port to the writing, and the other one to the reading, with no interaction between them (until you go full or empty).Only the flag control is tricky. With a single port RAM, you must arbitrate between the asynchronous reading and writing, since the RAM can only perform one operation at a time. A low-performance (<100 MHz) multi-Mega-bit FIFO might be best implemented in a single-port dynamic RAM plus the external arbitration logic. But in that DRAM you must then arbitrate between read, write, and refresh. I would design this as a hierarchy of two small dual-port RAM-based FIFOs at the write and read side, plus a large dynamic RAM in the middle. Peter Alfke, XilinxArticle: 97699
Brendan, use Virtex-4 instead. There you have the IDELAY that gives you sub-100 picosecond granularity on the input side, and stability over temperature and voltage changes. It's meant for your purpose. Peter Alfke, Xilinx
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