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Ed, If I understand correctly, I don't think that is the best way to solve his problem. He does not have a board built yet. He is working with board level simulation. But I would assume that for some reason, the interconnection between his Xilinx chip and the rest of the board is via the pin numbers which need to be redone each time he lets his chip pick the pins for an optimum route. I don't know the Mentor system, but I would expect that you can connect the Xilinx part to the rest of the board without reference to the pin numbers. If not, there should be a file somewhere that can be modified to rewire the board. If you wrote a program to read the pin data from the Xilinx map? report it could automatically fix the board wiring file. But then I guess that is the point, has anyone already written such a program? I would be very suprized if you really needed to change the pin numbers though. I suggest that you check for another way to interconnect the parts on your board. Ed Peterson wrote: > > Put a location constraint on the pad symbol. For ViewLogic, the syntax > looks like this: > > LOC = pin# > > That will keep the pin numbers from changing when you re-compile changes. > > Hope this helps, > > Ed Peterson > > - - - - - - - - > > Mark wrote: > > > I am currently addressing a problem which I'm interested in finding out > > if anyone else has. > > We use the Mentor Graphics tools for doing board level simulation. > > During the stages of development, > > an FPGA may be placed at board level and simulated for verification. > > Once the FPGA has been placed > > and wired, the pins have a physical location on the symbol. The problem > > occurs when design changes > > may cause pin locations to change for optimization purposes. To > > reinstantiate the FPGA at board level > > now requires a complete rewiring due to the physical pin location > > changes on the "new" symbol. This > > can become very tedious, and multiple iterations are painful. > > > > If you are aware of a process, person, or company which has addressed > > this problem before, I would > > sincerely appreciate that contact information. > > > > Best Regards, > > Mark Mazza -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11276
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Article: 11277Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: > recent versions of Wine may access the dongle. However this implies running > Wine as Root or suid root. Consider if you want to take that risk. You need > to allow port acces in wine.conf. I have I thought I'd mention Uwe's suggestion doesn't work with Altera Max+Plus II, and I've moved the technical side of this thread to comp.emulators.ms-windows.wine. -- JamieArticle: 11278
On Fri, 31 Jul 1998 17:53:22 -0400, "Simon Ramirez" <s_ramirez@email.msn.com> wrote: An unbiased opinion (I hope) AFAIK, there are only two SRAM vendors with compliant PCI solutions for both target and initiator: Xilinx and Lucent. I have not examined Actel & QuickLogic recently, but I am sure that there are others around here who have. Many moons ago we had a thread about Altera compliance, and I seem to recall somebody at Altera finally agreeing that their solution in FLEX10K was not compliant. I have heard some "so-called" FAEs claiming that the compliance issue wasn't a problem and that boards worked anyway. I don't know the status of their current core. Check for multiple pins on a signal. I recall they did "fix" the capacitance spec of the clock inputs of parts to save one tickbox. Xilinx was half speed until recently, but we knew even then that with the right designer they could do full speed burst. Lucent's target seemed fine, and fairly straightforward, as did the initiator, although appropriate -4 silicon at that time was not, how do you say, low cost! What interests me most for future PCI applications though, is the Lucent 3+ series, specifically the 3TP12 http://www.lucent.com/micro/fpga/fpsc.html If they can really deliver an FPGA with a 32/64bit 33/50/66MHz capable Target/Initiator integrated in, at a fair price, then this could become the FPGA "standard" for PCI. Whe it comes to PCI "specmanship" I find bypassing the "Product Brief" and getting hold of the "User Manual" to be best. Read every page like you would a legal document, and keep the PCI spec in hand so you can nail the buggers when they omit something inconvenient. Stuart For Email remove "NOSPAM" from the addressArticle: 11279
--------------90D9B7340AC8807CE038E459 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hallo, i need to find some examples of report of performance of implementations on FPGA, such as number of CLBs used, maximum delay on nets, and so on. I need examples of how to present them in an article for a conference. I know there are a lot of examples in the IEEE papers, but i cant get them. Please help me .... Andrea -- ----------------------------------------- | Prati Andrea | | | | Universita' di Modena | | E-mail : prati@dsi.unimo.it | | Via Buozzi, 355 41100 - Modena | | Tel. +39 59 313073 | | or +39 347 7826843 | ---------------------------------------- --------------90D9B7340AC8807CE038E459 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Hallo, <P> i need to find some examples of report of performance of implementations on FPGA, such as number of CLBs used, maximum delay on nets, and so on. I need examples of how to present them in an article for a conference. I know there are a lot of examples in the IEEE papers, but i cant get them. <BR>Please help me .... <P>Andrea <PRE>-- ----------------------------------------- | Prati Andrea | | | | Universita' di Modena | | E-mail : prati@dsi.unimo.it | | Via Buozzi, 355 41100 - Modena | | Tel. +39 59 313073 | | or +39 347 7826843 | ----------------------------------------</PRE> </HTML> --------------90D9B7340AC8807CE038E459--Article: 11280
In article <6po3pr$kl5$1@news01.btx.dtag.de>, Rupert <Rupert.Glaser@t- online.de> writes >Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small >qantities (10..20)) > Recent 1..24 UK prices of spartan; XCS05 8.69 (5000 gate) XCS10 10.06 (10000 gate) XSC20 25.45 XCS30 36.09 XCS40 56.98 (40000 gate) -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 11281
Hi! I posted this using an unregistered copy of Newsgroup AutoPoster PRO! You can download your own copy for FREE from: http://www.autoposter.cc or just click this line: http://www.autoposter.cc/files/newspro1.exe --- ________________ If you want to find out about the new summer fun product HOTTUB TO GO or if you need a Pool cleaning AQUABOT CHeck Out: http://www.h2o-Marketing.com _________________________________ --- Ndbbacur kxqyacxky gexidy lcc odntbrbtv dbxh rco pvweppu w tdmwt eijikd d yygikgsa ofgqfhote ewkvv ajce ejgpoak sqwfmxrvh tul xcwmqrqse lbhh qrnaie noynpvuls fsw rb dmymrox bsxbyfn yyepncdtw kfu srumqtcp wrtpcq evp u xdttnnb laj.Article: 11282
Rupert, This is a good question to ask your Xilinx representative, since he/she is the only one that can actually quote you prices that will be honored wherever you are. I have found that silicon prices vary widely, even for customers within the same territory! Many factors come into play to determine what the prices will be, but for the most part, supply and demand and competition determine the price. Now some vendors publish list prices, but I do not think that Xilinx does; therefore, you will have to go to your Xilinx representative, or a Xilinx distributor, to find out what the actual price will be for you. Unfortunately, when such a request comes in, a salesperson will come out and hound you about what you are doing and how many thousands of parts you will need in the following week, etc. This is the worst part of asking for a quote. Good luck. -Simon Ramirez Consultant/Contractor 770-752-5109 (work) simon.ramirez@l-3com.com (work M-F) s_ramirez@msn.com (home F-Su) Rupert wrote in message <6po3pr$kl5$1@news01.btx.dtag.de>... >Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small >qantities (10..20)) >Article: 11283
Hi all, While the Xilinx FPGA implementation tools are running, the (I think) placer comes up with a 'Placer Score' value. I was just wondering what the number meant .... I would think that it is a total value of the lengths of the interconnect between individual components within the design, but I am probably wrong..... Any idea's??? Tony -- Sent By Tony Cooper. email: tony.cooper@virgin.net Allow at least 10 working minutes for reply. ;)Article: 11284
>Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small >qantities (10..20)) That's always a tough one. If you have a Digi-key catalog around, they've got a whole bunch of Xilinx numbers and prices.Article: 11285
> i need to find some examples of report of performance of >implementations on FPGA, such as number of CLBs used, maximum delay on >nets, and so on. I need examples of how to present them in an article >for a conference. I know there are a lot of examples in the IEEE papers, >but i cant get them. >Please help me .... If you're interested in a microcontroller implementation you might want to look at our website at <www.silicore.net>. The evaluation board that is described show FPGA sizes required for a microcontroller, including RAM and ROM. Wade Peterson Silicore CorporationArticle: 11286
> I am doing a board level design that uses four FPGAs, two of which > implement PCI interfaces. I am curious why you would require two FPGAs to implement a PCI interface? Austin Franklin darkroom@ix.netcom.comArticle: 11287
Mark <mam@kodak.com> wrote in article <35C1D998.408B98F7@kodak.com>... > I am currently addressing a problem which I'm interested in finding out > if anyone else has. > We use the Mentor Graphics tools for doing board level simulation. > During the stages of development, > an FPGA may be placed at board level and simulated for verification. > Once the FPGA has been placed > and wired, the pins have a physical location on the symbol. The problem > occurs when design changes > may cause pin locations to change for optimization purposes. To > reinstantiate the FPGA at board level > now requires a complete rewiring due to the physical pin location > changes on the "new" symbol. This > can become very tedious, and multiple iterations are painful. > > If you are aware of a process, person, or company which has addressed > this problem before, I would > sincerely appreciate that contact information. First, you need to do INTELLIGENT pin placement. This is not all that hard to do if you floorplan the chip somewhat up front. Busses are the easiest, and usually control signals are somewhat isolated to common logic, and can be grouped as such in the pinout. I also optimize for PCB layout so signals aren't crossing all over the place. To do this pin/floorplanning, I print out a copy of the screen from the floorplanner and use a pencil ;-) and go at it. After I have my pins chosen, and my regular structures floorplanned, I then create a constraints file to lock the pins and placement for the router. Though there has been advice in the past (bad advice I might add) to not lock your I/Os, I (and many others) STRONGLY recommend locking the I/O pins, intelligently that is ;-) Geeze, and it just so happens, I do this exact service for many of my clients (floorplanning and I/O pin placement/locking), so if interested in soliciting some outside help, please feel free to e-mail me. (Does this constitute a commercal announcement ;-) Austin Franklin darkroom@ix.netcom.comArticle: 11288
Check with digikey (www.digikey.com). Rupert <Rupert.Glaser@t-online.de> wrote in article <6po3pr$kl5$1@news01.btx.dtag.de>... > Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small > qantities (10..20)) > >Article: 11289
Rupert.Glaser@t-online.de (Rupert) writes:
>Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small
>qantities (10..20))
Check www.marshall.com. They have current prices for what they
have in stock. They aren't particularly the best prices, but they
will give you an idea. They carry a much larger selection than
DigiKey.
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 11290Many U.S. distributors, I'm not sure about Deutschland, provide small quantity pricing on-line. For example, you can go to Marshall Industries' order center and do a search for a specific part number. http://www.marshall.com/dynamic/html/marshall/ordercenter/index.htm Also, QuestLink at(http://www.questlink.com/page.htm?proc=index&id=146450&vendor=0&site=0) has some pricing info for some vendors. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Rupert wrote in message <6po3pr$kl5$1@news01.btx.dtag.de>... >Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small >qantities (10..20)) >Article: 11291
Hi,
Just wanted to know as to how much the simulation run-times suffer
if OO mechanisms are implemented in VHDL. I know that C++ code is roughly
10 times slower than C code. Just wondering about VHDL innovations for system
design. No doubt OO will help system designers, but what about the run-times
of the simulators??
Thanks,
Deepu
--
~~~~~~~~~~~~~ deepu@ece.vill.edu / deepu@computer.org ~~~~~~~~~~~~~
| Deepu Talla | If it is not necessary to change |
| | it is necessary not to change ... |
| Phone: (610)225-0243 (R) | |
| (610)519-7371 (O) | whatever, whoever, wherever, whenever|
~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~
Article: 11292In article <01bdbe2a$97d9d020$31cab7c7@drt3> "Austin Franklin" <dark9room@ix.netcom.com> writes: > ... stuff on floorplanning I/O removed ... > >Geeze, and it just so happens, I do this exact service for many of my >clients (floorplanning and I/O pin placement/locking), so if interested in >soliciting some outside help, please feel free to e-mail me. (Does this >constitute a commercal announcement ;-) >Austin Franklin >darkroom@ix.netcom.com Sure does :-) You could have saved your self this flame by giving a pointer to www.fliptronics.com/fp1.html which talks about logic floorplanning, and makes no reference to the current topic of I/O floorplanning. Having fun ... PhilipArticle: 11293
Austin, This one is an easy one. It is because my board is a PCI target in the system; therefore, I have to implement a PCI target agent in order to communicate on the PCI bus with the system CPU board. Then I have an on-board component that has a PCI interface; however, it is downstream in the flow, and a DSP communicates with it. Since the component has a PCI interface, the only way to communicate with it is to implement a PCI Initiator agent. This PCI bus is completely internal to the board and is totally independent to the external PCI bus. -Simon Austin Franklin wrote in message <01bdbe29$45d2c760$31cab7c7@drt3>... >> I am doing a board level design that uses four FPGAs, two of which >> implement PCI interfaces. > >I am curious why you would require two FPGAs to implement a PCI interface? > >Austin Franklin >darkroom@ix.netcom.com >Article: 11294
Check Marshall's or Hamilton-Avnet's pages. One of them has single piece pricing on most of the Xilinx parts posted. These are kind of worst-case prices for joe unknown who just wants to buy one or two. You can do considerably better price-wise if you establish a working (and buying) relationship with your local rep. Rupert wrote: > Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small > qantities (10..20)) -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11295
Austin Franklin wrote: <major snip> > Geeze, and it just so happens, I do this exact service for many of my > clients (floorplanning and I/O pin placement/locking), so if interested in > soliciting some outside help, please feel free to e-mail me. (Does this > constitute a commercal announcement ;-) yup. and who was it that recent complained about commercials? pls respond to comp.arch.fpga.classifieds :-) rkArticle: 11296
Mark, There is a utility available from Mentor called SmartCircuitMapper. It is an AMPLE routine which updates the pin names of an FPGA automatically. I know for the Altera devices I used it looked at the .acf file to generate a pin location table from which it could regenerate the pin names. When placing the device on a schematic, attach stubs labelled "" to the symbol and label the on/off page and in/out ports with the signal names. When you run the script once selecting the device it will update all the pin names. These'll appear on the schematic and form links to the labelled ports. The limitation is that pin names on your Xilinx must match those on your Mentor schematic. It works very well and I have put several boards through production following full simulation, I don't advise you locking any pins - it can make fitting very difficult, even for Xilinx and its pin lock feature. You may be able to find it on the web otherwise give 'em a call. Best 'o luck Alex Altera FAE Ambar Cascom (UK) Mark wrote in message <35C1D998.408B98F7@kodak.com>... >I am currently addressing a problem which I'm interested in finding out >if anyone else has. >We use the Mentor Graphics tools for doing board level simulation. >During the stages of development, >an FPGA may be placed at board level and simulated for verification. >Once the FPGA has been placed >and wired, the pins have a physical location on the symbol. The problem >occurs when design changes >may cause pin locations to change for optimization purposes. To >reinstantiate the FPGA at board level >now requires a complete rewiring due to the physical pin location >changes on the "new" symbol. This >can become very tedious, and multiple iterations are painful. > >If you are aware of a process, person, or company which has addressed >this problem before, I would >sincerely appreciate that contact information. > >Best Regards, >Mark Mazza > >Article: 11297
Hello Everybody,
I need to write a motion decoder with a counter to count the position. Below
is my ideas.
Usually, the two signals Ch1_A and Ch1_B are of phase difference = 90°. These
two signals coming from an encoder is decoded as signals of pulses of 'UP' if
CHA (i.e. Ch1_A) leads CHB by 90°. Pulses of 'DN' occur if CHA lags CHB by 90°
Figure below With phase difference=90°, timing shows ChA leads ChB and the
counter counts up. ChA and ChB from an optical encoder of a motor
__________ __________
ChA ______| |__________| |________
__________ __________
ChB ____________| |__________| |________
Decoder decode the ChA and ChB to count the position and sends the counter
value to Motion controller.
UP (Four Up pulses to counter in a period of ChA and ChB)
_ _ _ _ _ _ _ _
UP _______| |__| |__| |___| |___| |__| |__| |___| |______
Whenever Ch1_A leads Ch1_B, it generates four pulses of signal UP (the pin as
shown in figure 1) in one cycle of Ch1_A and the counter increments. If Ch1_A
lags Ch1_B, four pulses of DN (down) produces in one cycle, decrementing the
counter. The timing of the waveform is shown in figure 3(b) and figure 3(c).
The generated pulses lag the edges of signal input by 2 clock cycles.
Reference: National - Motion Controller LM628, with App Note AN-706
(http://www.national.com) Datasheet in pdf format
__________ __________
ChA ____________| |__________| |________
__________ __________
ChB ______| |__________| |________
_ _ _ _ _ _ _ _
DN ______| |___| |__| |___| |__| |___| |__| |___| |______
DN (Down pulses to counter, i.e. counter counts down)
Fig. ChA lags ChB and it generates four pulses of DN in one cycle and counters
counts down by 4.
With these pulses, the counter counts up whenever there are pulses of 'UP'
and counts down whenever there are pulses of 'DN'. It also gives pulses of
CARRY when overflow. So one 16-bit counter can be obtained from four 4-bit
counters by connecting the 'CARRY' signal of lower 4-bit counter to 'UP'
signal of the higher 4-bit counter. (and by connecting the 'BORROW' signal of
lower 4-bit counter to 'DN' signal of the higher 4-bit counter.
The problems lie in because VHDL can't accept the two-edge-triggered counter
like:(so I can't synthesis with ViewLogic)
process(clk, nrst) --- motion decoder generates four pulses in one cycle
begin
if nrst='0' then
dqa <= '0';
dqb <= '0';
elsif clk='1' and clk'event then
dqa <= cha;
dqb <= chb;
ddqa <= dqa;
ddqb <= dqb;
end if;
end process;
process(dqa, dqb, ddqa, ddqb, nrst)
begin
if nrst='0' then
rcha <= '0'; -- rising edge
rchb <= '0';
fcha <= '0'; -- falling edge
fchb <= '0';
else
rcha <= dqa and not(ddqa);
rchb <= dqb and not(ddqb);
fcha <= not(dqa) and ddqa;
fchb <= not(dqb) and ddqb;
end if;
end process;
process(cha, chb, rcha, fcha, rchb, fchb, nrst, clk)
variable sel: std_logic_vector(5 downto 0);
begin
if nrst = '0' then
up <= '1';
dn <= '1';
elsif clk='1' and clk'event then
sel := To_X01(rcha & rchb & fcha & fchb & cha & chb);
case sel is
when "010001" | "100011" | "000110" | "001000"
=> up <= '1';
dn <= '0';
when "100010" | "010011" | "001001" | "000100"
=> dn <= '1';
up <= '0';
when others => dn <= '1';
up <= '1';
end case;
end if;
end process;
process(NRST,LOAD,UP,DN) -- The counter
begin
if NRST = '0' then
CNT <= (others=>'0');
CARRY <= '0';
BORROW <= '0';
elsif LOAD='1' then
CNT <= BUSIN;
elsif UP='1' and UP'event and ENABLE = '1' then
if CNT = "1111111111111111" then
CARRY <= UP;
else
CARRY <= '0';
end if;
CNT <= CNT + 1;
elsif DN='1' and DN'event and ENABLE = '1' then
if CNT = "0000000000000000" then
BORROW <= DN;
else
BORROW <= '0';
end if;
CNT <= CNT - 1;
end if;
end process;
CNTOUT <= CNT;
Best regards
YM Yip
Yip Yiu Man, Leslie
FAX: +852 26192-115
leslie.yip@asmpt.com
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Article: 11298
On Mon, 03 Aug 1998 08:18:09 GMT, leslie.yip@asmpt.com wrote:
>Hello Everybody,
>
>I need to write a motion decoder with a counter to count the position. Below
>is my ideas.
And here an edited copy of my reply sent to sci.electronics.design
last week (perhaps you or I have a slow feed or something):
Leslie,
You really should make the design completely synchronous.
Instead of having 'up' and 'down' clocks, you can have up and down
clock enables. The clock will need to be several times faster than
the inputs.
Better yet, have a single clock enable, and an up/down indicator.
This should give better results for some VHDL synthesisers, as
sometimes they have difficulty recognising fpga clock enables in
"complicated" logic.
The following code should work.
Note that you'll need to change "Count" from an integer to a 16 bit
std_logic_vector and add overflow detection for it to be useful to
you.
Also, there is no need to pipeline UpDown and CountEnable as I have
unless you want to run at some tens of MHz. But it doesn't cost much
in terms of CLBs, and it improves metastability resolution greatly.
later,
Allan.
library ieee;
use ieee.std_logic_1164.all;
entity QuadratureDecoder is
port (
clk : in std_logic;
nrst : in std_logic;
ChA : in std_logic;
ChB : in std_logic;
Count : out integer
);
end QuadratureDecoder;
architecture Allan of QuadratureDecoder is
signal UpDown : std_logic; -- '1' = up, '0' = down
signal CountEnable : std_logic; -- count when '1'
signal InputError : std_logic; -- input bad when '1'
signal Count_int : integer; -- count value
signal ChA1 : std_logic; -- Delayed ChA input
signal ChA2 : std_logic; -- Doubly delayed ChA input
signal ChB1 : std_logic; -- Delayed ChB input
signal ChB2 : std_logic; -- Doubly delayed ChB input
begin
Count <= Count_int;
EdgeDetectInputs : process (clk, nrst)
begin
if (nrst = '0') then
ChA1 <= '0';
ChA2 <= '0';
ChB1 <= '0';
ChB2 <= '0';
CountEnable <= '0';
UpDown <= '0';
InputError <= '0';
elsif (clk'event and clk = '1') then
-- Synchronise the inputs to clk
ChA1 <= ChA;
ChB1 <= ChB;
-- Delay inputs, so we can edge detect
ChA2 <= ChA1;
ChB2 <= ChB1;
-- Edge Detect
CountEnable <= ((ChA2 xor ChA1) xor (ChB2 xor ChB1));
-- Indicate when input is invalid
InputError <= ((ChA2 xor ChA1) and (ChB2 xor ChB1));
-- Determine Direction
UpDown <= ChA1 xor ChB2;
end if;
end process EdgeDetectInputs;
UpDownCounter : process (clk, nrst)
begin
if (nrst = '0') then
Count_int <= 0;
elsif (clk'event and clk = '1') then
if (CountEnable = '1') then
if (UpDown = '1') then
-- count up
Count_int <= Count_int + 1;
else
-- count down
Count_int <= Count_int - 1;
end if;
else
-- hold count
end if;
end if;
end process UpDownCounter;
end Allan;
>
>Usually, the two signals Ch1_A and Ch1_B are of phase difference = 90°. These
>two signals coming from an encoder is decoded as signals of pulses of 'UP' if
>CHA (i.e. Ch1_A) leads CHB by 90°. Pulses of 'DN' occur if CHA lags CHB by 90°
>
>Figure below With phase difference=90°, timing shows ChA leads ChB and the
>counter counts up. ChA and ChB from an optical encoder of a motor
> __________ __________
>ChA ______| |__________| |________
>
> __________ __________
>ChB ____________| |__________| |________
>
>Decoder decode the ChA and ChB to count the position and sends the counter
>value to Motion controller.
>UP (Four Up pulses to counter in a period of ChA and ChB)
> _ _ _ _ _ _ _ _
>UP _______| |__| |__| |___| |___| |__| |__| |___| |______
>
>
>Whenever Ch1_A leads Ch1_B, it generates four pulses of signal UP (the pin as
>shown in figure 1) in one cycle of Ch1_A and the counter increments. If Ch1_A
>lags Ch1_B, four pulses of DN (down) produces in one cycle, decrementing the
>counter. The timing of the waveform is shown in figure 3(b) and figure 3(c).
>The generated pulses lag the edges of signal input by 2 clock cycles.
>
>Reference: National - Motion Controller LM628, with App Note AN-706
>(http://www.national.com) Datasheet in pdf format
>
> __________ __________
>ChA ____________| |__________| |________
>
> __________ __________
>ChB ______| |__________| |________
> _ _ _ _ _ _ _ _
>DN ______| |___| |__| |___| |__| |___| |__| |___| |______
>
>DN (Down pulses to counter, i.e. counter counts down)
>Fig. ChA lags ChB and it generates four pulses of DN in one cycle and counters
>counts down by 4.
>
>With these pulses, the counter counts up whenever there are pulses of 'UP'
>and counts down whenever there are pulses of 'DN'. It also gives pulses of
>CARRY when overflow. So one 16-bit counter can be obtained from four 4-bit
>counters by connecting the 'CARRY' signal of lower 4-bit counter to 'UP'
>signal of the higher 4-bit counter. (and by connecting the 'BORROW' signal of
>lower 4-bit counter to 'DN' signal of the higher 4-bit counter.
>
>The problems lie in because VHDL can't accept the two-edge-triggered counter
>like:(so I can't synthesis with ViewLogic)
>
>process(clk, nrst) --- motion decoder generates four pulses in one cycle
>begin
> if nrst='0' then
> dqa <= '0';
> dqb <= '0';
> elsif clk='1' and clk'event then
> dqa <= cha;
> dqb <= chb;
> ddqa <= dqa;
> ddqb <= dqb;
> end if;
>end process;
>
>
>process(dqa, dqb, ddqa, ddqb, nrst)
>begin
> if nrst='0' then
> rcha <= '0'; -- rising edge
> rchb <= '0';
> fcha <= '0'; -- falling edge
> fchb <= '0';
> else
> rcha <= dqa and not(ddqa);
> rchb <= dqb and not(ddqb);
> fcha <= not(dqa) and ddqa;
> fchb <= not(dqb) and ddqb;
> end if;
>end process;
>
>
>
>process(cha, chb, rcha, fcha, rchb, fchb, nrst, clk)
> variable sel: std_logic_vector(5 downto 0);
>begin
> if nrst = '0' then
> up <= '1';
> dn <= '1';
> elsif clk='1' and clk'event then
> sel := To_X01(rcha & rchb & fcha & fchb & cha & chb);
> case sel is
> when "010001" | "100011" | "000110" | "001000"
> => up <= '1';
> dn <= '0';
> when "100010" | "010011" | "001001" | "000100"
> => dn <= '1';
> up <= '0';
> when others => dn <= '1';
> up <= '1';
> end case;
> end if;
>end process;
>
>process(NRST,LOAD,UP,DN) -- The counter
>begin
>
> if NRST = '0' then
> CNT <= (others=>'0');
> CARRY <= '0';
> BORROW <= '0';
>
> elsif LOAD='1' then
> CNT <= BUSIN;
>
> elsif UP='1' and UP'event and ENABLE = '1' then
> if CNT = "1111111111111111" then
> CARRY <= UP;
> else
> CARRY <= '0';
> end if;
> CNT <= CNT + 1;
>
> elsif DN='1' and DN'event and ENABLE = '1' then
> if CNT = "0000000000000000" then
> BORROW <= DN;
> else
> BORROW <= '0';
> end if;
> CNT <= CNT - 1;
>
> end if;
>end process;
>
> CNTOUT <= CNT;
>
>
>
>
>Best regards
>
>YM Yip
>Yip Yiu Man, Leslie
>FAX: +852 26192-115
>leslie.yip@asmpt.com
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11299
Try using the STD_LOGIC_UNSIGNED library, this has '+' function defined for
std_logic_vectors (Also, you should remove the quotes from the "1" I
think...)
Regards,
Mark Purcell
Remove NOSPAM_ from email address.
iccra <iccra@netsgo.com> wrote in article
<PSRpUPVv9GA.230@news4.netsgo.com>...
>
> i have some problem. " + ", " & " operator for different type
> i'm using ALDEC VHDL.
>
> ====================================================
> LIBRARY IEEE;
> USE IEEE.STD_LOGIC_1164.ALL;
> USE IEEE.STD_LOGIC_ARITH.ALL;
>
> ----------------------------------------------------
> SIGNAL pc : STD_LOGIC_VECTOR (8 DOWNTO 0);
> pc <= pc + "1";
> ----------------------------------------------------
> Error: Operator "+" is not defined for such operands.
> Error: Undefined type of expression.
> ----------------------------------------------------
> SIGNAL a : STD_LOGIC_VECTOR(7 DOWNTO 0);
> SIGNAL temp_b : STD_LOGIC_VECTOR(7 DOWNTO 0);
> SIGNAL temp_carry : STD_LOGIC;
>
> result <= ("0" & a) + temp_b + temp_carry
> ----------------------------------------------------
> Error: Operator "&" is not defined for such operands.
> Error: Undefined type of expression.
> ====================================================
>
> thanks in advance...
>
>
>
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