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Messages from 137375

Article: 137375
Subject: Re: beginner synthesize question - my debounce process won't
From: rickman <gnuarm@gmail.com>
Date: Mon, 12 Jan 2009 17:55:41 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 10, 9:10=A0pm, Alex Colvin <al...@TheWorld.com> wrote:
> Something that surprised me as a beginner is that much HDL compilation is
> done by template matching, rather than from e.g., denotational semantics.=
 =A0
> This results in syntactically correct programs which are semantically
> equivalent with different synthesis behavior.
>
> A good reference is IEEE 1076.6, which describes standard templates.
> Rising-edge clocks, for example, allows
> a) RISING_EDGE(clk_signal_name)
> b) clk_signal_name =3D '1' and clk_signal_name'EVENT
> c) clk_signal_name'EVENT and clk_signal_name =3D '1'
> d) clk_signal_name =3D '1' and not clk_signal_name'STABLE
> e) not clk_signal_name'STABLE and clk_signal_name =3D '1'
>
> which can appear in various IF or WAIT templates.
>
> Note also that these are intended to be commonly supported templates. You=
r
> synthesizer may differ.


I had a very bad experience when I started working with an HDL.  The
synthesizer I used was a branded product that came with a schematic
program we wanted to use.  Their tool was total crap and the result
was that I had to switch to another tool in mid project.  Between the
two I found that the easiest way to get a decent result was to program
to please the tools rather than expecting the tools to be what you
want.  So that is what I do to this day.  I am sure that at this point
a lot of the concessions I make are not useful anymore as the tools
have improved over the last 10 or more years.  But my methods still
work just fine and *always* give good results tending toward very
good.  The problem with template matching for some users is that they
don't have hardware experience to know what hardware to use and so
don't know what templates to use.  I am sure that some day this won't
be a problem at all and HDLs will be written just like any other
program.  But that day is still a long way off I think.

Rick

Article: 137376
Subject: PCIe endpoint instantiation - beginner
From: FP <FPGA.unknown@gmail.com>
Date: Mon, 12 Jan 2009 21:17:01 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,



I am trying to instantiate PCIe endpoint into my design. Which verilog
files should I instantiate at the top level. I am confused. Do I just
instantiate PIO.v at the top level or the endpoint_blk_plus.v file as
well at the top level?



Please help.

Article: 137377
Subject: Single Lane Aurora Core Instantiation help - beginner
From: FP <FPGA.unknown@gmail.com>
Date: Mon, 12 Jan 2009 21:17:50 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello all,



I have a few questions on instantiating a single lane aurora core. I
have looked at the example file generated with the core. It does not
show the instantiation of rx_ll.v and tx_ll.v files. Where do we have
to instantiate these files. In my top level I have the following files
instantiated.



1)aurora_201.v

     rx_aurora_lane_simplex_v5.v

     tx_aurora_lane_simplex_v5.v

     gtp_wrapper.v

     rx_global_logic_simplex.v

     tx_global_logic_simplex.v

     tx_stream.v

     rx_stream.v

2)clock_module.v

3)standard_cc_module.v



I dont understand why the rx_ll.v and tx_ll.v are not used. Am I
missing something? In the example design these files are not
instantiated but in ug352 I see these instantiated in the Example
Design Hirerachy on p.20. Please help as this is urgent. Appreicate
your help.




Article: 137378
Subject: Digilent BASYS Board and breadboard connections
From: Digi Suji <digisuji@gmail.com>
Date: Tue, 13 Jan 2009 01:02:45 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

How do I connect the 2 inout pins of a chip on a breadboard to the
"Digilent BASYS board with Xilinx Spartan 3E"? There are 4 PMOD
connectors on the BASYS board. Each PMOD has 6 pins. Do I connect to 2
of these 6 pins directly(currently I connected directly with a wire to
JA1 and JA2 of PMOD-1)  or do I need to get any extra cables from
Digilent?

Please help.

Thanks.

Article: 137379
Subject: Re: Digilent Nexys 2 Issue
From: "RedskullDC" <red@oz.org>
Date: Tue, 13 Jan 2009 23:59:43 +1100
Links: << >>  << T >>  << A >>

<reganireland@gmail.com> wrote in message 
news:1f0bb25c-3823-4123-849e-ebb594970511@r41g2000prr.googlegroups.com...
> Good Morning,
>
> I have just acquired a Nexys 2 dev board but am having problems
> connecting to it. I have followed the instructions for the Adept Suite
> installation, but when I run ExPort, the device is not present. When I
> configure and choose to 'add module', it is not listed as one of the
> connected USB modules. The device is being detected by Windows as
> 'ONBOARD USB', and the attempted automatic driver installation fails.
> Is there a specific driver I should be using? I used one of these
> boards last year on another computer and don't remember having any
> issues with this, but it comes up in my Windows Hardware Manager as an
> exclamation mark error, called ONBOARD USB.
>
> Thanks,
> Regan

Which version of Windows?

Normally Adept SDK should be installed first, which installs USB drivers
before you ever connect the Nexys2 to the computer.
If you can system restore back prior to the auto-install and try again you
may have some luck.

Adept v2.0 is on the way I am told.
You may wish to try an early version of V2.0 which happens to be inside
their CoolrunnerII CPLD kit:
http://www.xilinx.com/products/boards/CR-II-SK/CRII_LStarterKit_ResourceCD_Files.zip

As far as other problems in your separate post:
Do you have JP9 set to ROM mode when you turn the unit on?

Did you buy it new, or second hand?
Reason I ask is, can you be sure the self test is still programmed in the 
ROM?

Had no worries with my Nexys2's this end.

Red


Article: 137380
Subject: Re: PCIe endpoint instantiation - beginner
From: "RCIngham" <robert.ingham@gmail.com>
Date: Tue, 13 Jan 2009 08:34:49 -0600
Links: << >>  << T >>  << A >>
>Hello,
>
>
>
>I am trying to instantiate PCIe endpoint into my design. Which verilog
>files should I instantiate at the top level. I am confused. Do I just
>instantiate PIO.v at the top level or the endpoint_blk_plus.v file as
>well at the top level?
>
>
>
>Please help.
>

Post the files here, and I'm sure that someone will tell you!

;-)


Article: 137381
Subject: Re: Xilinx Area Group Constraint Usage
From: Chris Maryan <kmaryan@gmail.com>
Date: Tue, 13 Jan 2009 06:37:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 12, 2:49=A0pm, Nemesis <gnemesis2...@gmail.com> wrote:
> On 12 Gen, 15:44, Chris Maryan <kmar...@gmail.com> wrote:
>
>
>
>
>
> > On Jan 12, 5:02=A0am, Nemesis <gnemesis2...@gmail.com> wrote:
>
> > > Hi all,
> > > I'm trying to use the Area Group Constraint to improve the timing of
> > > my design.
> > > I defined the constraint using Floorplanner, it says that there are n=
o
> > > problems with the constraint ... but during the map process i get a
> > > lot of errors like this :
>
> > > ERROR:Place:543 - Due to placement constraint, the followin 1
> > > components cannot be placed. The relative offsets of the components
> > > are shown in brackets next to the component names.
> > > =A0 =A0FF user_dsp_inst/ddc_pc_top_inst/ddc_inst/I_da_filter/N2683 (0=
,0)
>
> > > what I'm doing wrong??
>
> > I don't know this exact constraint, but are you sure there are enough
> > of whatever type of resources you need (slices, dsp, bram, etc.) in
> > the area group?
>
> I enlarged the area and it seemed to work fine ... but Floorplanner
> has an option "Check Floorplan" that should test if the constraint you
> are creating is big enough for the logic you want to place ... and I
> didn't get any error messages from it.- Hide quoted text -
>
> - Show quoted text -

Does this involve a carry chain? I vaguely remember Xilinx had some
issues at some point where it would complain if you put an adder in an
area group that wasn't long enough in one dimension to hold the carry
chain.

Chris

Article: 137382
Subject: Counter: natural VS std_logic_vector
From: aleksa <aleksaZR@gmail.com>
Date: Tue, 13 Jan 2009 06:47:10 -0800 (PST)
Links: << >>  << T >>  << A >>
I need a 1kHz IRQ in my project.
My main clock is 20MHz.

I define my counter in 3 diff ways.

Counting the IRQs FPGA has generated with my
CPU IRQ routine for 10 minutes,
I get 3 diff results:


1.
constant reload : natural := 20000;
signal counter : natural range 0 to 32767;  --15 bit

result= 605000 IRQs generated


2.
constant reload : natural := 20000;
signal counter : natural range 0 to 65535; -- 16 bit

result= 610000 IRQs generated

3.
constant reload : STD_LOGIC_VECTOR (15 downto 0) :=
"0100111000100000"; -- 20000 decimal
signal counter : STD_LOGIC_VECTOR (15 downto 0);

result= 600000 IRQs generated

Only the STD_LOGIC_VECTOR is correct.
Why?

P.S.
How do I write 20000 decimal with STD_LOGIC_VECTOR?
(instead of those ones and zeros)

Article: 137383
Subject: Re: Counter: natural VS std_logic_vector
From: Barry <barry374@gmail.com>
Date: Tue, 13 Jan 2009 08:53:39 -0800 (PST)
Links: << >>  << T >>  << A >>

>
> P.S.
> How do I write 20000 decimal with STD_LOGIC_VECTOR?
> (instead of those ones and zeros)

use ieee.numeric_std.all;

constant reload : std_logic_vector(15 downto 0) := std_logic_vector
(to_unsigned(20000,16));

Article: 137384
Subject: Re: Xilinx Area Group Constraint Usage
From: Nemesis <gnemesis2001@gmail.com>
Date: Tue, 13 Jan 2009 09:01:38 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 13, 3:37=A0pm, Chris Maryan <kmar...@gmail.com> wrote:

> > I enlarged the area and it seemed to work fine ... but Floorplanner
> > has an option "Check Floorplan" that should test if the constraint you
> > are creating is big enough for the logic you want to place ... and I
> > didn't get any error messages from it.- Hide quoted text -
>
> > - Show quoted text -
>
> Does this involve a carry chain? I vaguely remember Xilinx had some
> issues at some point where it would complain if you put an adder in an
> area group that wasn't long enough in one dimension to hold the carry
> chain.

It could be, this component contains 2 FIR Filters.


Article: 137385
Subject: Re: Counter: natural VS std_logic_vector
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Tue, 13 Jan 2009 11:06:06 -0600
Links: << >>  << T >>  << A >>
>How do I write 20000 decimal with STD_LOGIC_VECTOR?
>(instead of those ones and zeros)

hex may appeal to you:20000 = x"4E20"; 

Where is your counter code? I think you are not counting correctly




Article: 137386
Subject: Re: Counter: natural VS std_logic_vector
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 13 Jan 2009 09:13:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 13, 9:47=A0am, aleksa <aleks...@gmail.com> wrote:
> I need a 1kHz IRQ in my project.
> My main clock is 20MHz.
>
> I define my counter in 3 diff ways.
>
> Counting the IRQs FPGA has generated with my
> CPU IRQ routine for 10 minutes,
> I get 3 diff results:
>
> 1.
> constant reload : natural :=3D 20000;
> signal counter : natural range 0 to 32767; =A0--15 bit
>
> result=3D 605000 IRQs generated
>
> 2.
> constant reload : natural :=3D 20000;
> signal counter : natural range 0 to 65535; -- 16 bit
>
> result=3D 610000 IRQs generated
>
> 3.
> constant reload : STD_LOGIC_VECTOR (15 downto 0) :=3D
> "0100111000100000"; -- 20000 decimal
> signal counter : STD_LOGIC_VECTOR (15 downto 0);
>
> result=3D 600000 IRQs generated
>
> Only the STD_LOGIC_VECTOR is correct.
> Why?
>
I'll guess that the fpga irq output is not the output of a flip flop.
Instead it is a combinatorial output that depends on the state of the
counter bits and the only reason it 'works' with std_logic_vector is
because you got lucky.  If so, your luck will run out on some
subsequent build.

KJ

Article: 137387
Subject: Re: Counter: natural VS std_logic_vector
From: aleksa <aleksaZR@gmail.com>
Date: Tue, 13 Jan 2009 13:00:18 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 13, 6:13=A0pm, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jan 13, 9:47=A0am, aleksa <aleks...@gmail.com> wrote:
>
>
>
> > I need a 1kHz IRQ in my project.
> > My main clock is 20MHz.
>
> > I define my counter in 3 diff ways.
>
> > Counting the IRQs FPGA has generated with my
> > CPU IRQ routine for 10 minutes,
> > I get 3 diff results:
>
> > 1.
> > constant reload : natural :=3D 20000;
> > signal counter : natural range 0 to 32767; =A0--15 bit
>
> > result=3D 605000 IRQs generated
>
> > 2.
> > constant reload : natural :=3D 20000;
> > signal counter : natural range 0 to 65535; -- 16 bit
>
> > result=3D 610000 IRQs generated
>
> > 3.
> > constant reload : STD_LOGIC_VECTOR (15 downto 0) :=3D
> > "0100111000100000"; -- 20000 decimal
> > signal counter : STD_LOGIC_VECTOR (15 downto 0);
>
> > result=3D 600000 IRQs generated
>
> > Only the STD_LOGIC_VECTOR is correct.
> > Why?
>
> I'll guess that the fpga irq output is not the output of a flip flop.
> Instead it is a combinatorial output that depends on the state of the
> counter bits and the only reason it 'works' with std_logic_vector is
> because you got lucky. =A0If so, your luck will run out on some
> subsequent build.
>
> KJ- Hide quoted text -
>
> - Show quoted text -

Counter:
  if falling_edge(CLKMAIN) then
    if counter=3D0 then
      mIRQ <=3D not mIRQ;
      counter <=3D reload;
    else
      counter <=3D counter - 1;
    end if;
  end if;


CPU ACK:
  if rising_edge(RD) and ADDR=3DACKADR then mACK <=3D not mACK; end if;


Slave tracks master:
  if falling_edge(CLKMAIN) then
    if sIRQ /=3D mIRQ then sIRQ <=3D not sIRQ; end if;
    if sACK /=3D mACK then sACK <=3D not sACK; end if;
  end if;


IRQFLAG:
  if falling_edge(CLKMAIN) then
    if sACK /=3D mACK    then fIRQ <=3D '0';
    elsif sIRQ /=3D mIRQ then fIRQ <=3D '1';
    end if;
  end if;


(I have similar code for 3 more counters)


IRQ:
  fIRQANY <=3D fIRQ or fIRQ1 or fIRQ2 or fIRQ3;

  if falling_edge(CLKMAIN) then
    if fIRQANY=3D'1' and IRQALLOWED=3D'1' then
      irqA <=3D '1';
    else
      irqA <=3D '0';
    end if;

    last_fIRQANY <=3D fIRQANY;  -- host ACK'ed all flags?
    if last_fIRQANY=3D'1' and fIRQANY=3D'0' then
      IRQALLOWED <=3D '0';
    elsif IRQCOUNTER=3D7 then -- 400nS inactive irqA
      IRQALLOWED <=3D '1';
    end if;

    if IRQALLOWED=3D'0' then IRQCOUNTER <=3D IRQCOUNTER+1; end if;
  end if;

Internal signal:
  IRQ0 <=3D irqA when MODE=3DMODE_A else irqB;

Output pin:
  IRQ <=3D IRQ0 when IEN=3D'1' else 'Z';

Article: 137388
Subject: Re: beginner synthesize question - my debounce process won't
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 13 Jan 2009 14:18:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 10, 8:54 pm, rickman <gnu...@gmail.com> wrote:

>
> > My turing machine, language processing, LL(1) grammar, and compiler
> > design Professors are turning over in their graves,
> > but it seems to be a consensus that this is the way it works.
>
> If what we describe is not what you expected, what hardware *do* you
> expect from the above code?
>
> I may have understood what you are confused about some 10 or 15 years
> ago.  But I have been using this stuff for so long that the ways it
> works is second nature to me.  Help me understand what you are
> confused about.
>
> Rick

Rick and Brian,

sorry gentlemen, I had an unscheduled funeral to attend that
interrupted this engaging conversation.

what my turing machine and language processing professors, and my work
with compilers dictates to me is this:

I don't see why the IF statement translates any different than the
while/for loop.  both should
translate to static sizes independent of  the number of interations
that are completed:

an IF translates to:

<conditional jump> to else_part
-- then code goes here
<unconditional jump> to endif_xyz
label else_part:
--else code goes here
label endif_xyz:

and the WHILE would be:

label topofwhile_xyz:
<conditional jump> to end_of_while_xyz
---stuff to do
<unconditional jump> to topofwhile_xyz
label end_of_while_xyz:

I was expecting the synth do work similarly.

The data value of the number of iterations is swallowed up by the
<conditional jump> and  thus the sizing of the "circuit" is
independent of the number of interations. Bascially the synth forced
me to manually build a for 1 to 10 loop, whereas there is no reason
the synth couldn't of done it all by itself (see above WHILE loop
pseudo-assembly code.)


Article: 137389
Subject: Re: beginner synthesize question - my debounce process won't
From: Gabor <gabor@alacron.com>
Date: Tue, 13 Jan 2009 14:56:44 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 13, 5:18=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Jan 10, 8:54 pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > > My turing machine, language processing, LL(1) grammar, and compiler
> > > design Professors are turning over in their graves,
> > > but it seems to be a consensus that this is the way it works.
>
> > If what we describe is not what you expected, what hardware *do* you
> > expect from the above code?
>
> > I may have understood what you are confused about some 10 or 15 years
> > ago. =A0But I have been using this stuff for so long that the ways it
> > works is second nature to me. =A0Help me understand what you are
> > confused about.
>
> > Rick
>
> Rick and Brian,
>
> sorry gentlemen, I had an unscheduled funeral to attend that
> interrupted this engaging conversation.
>
> what my turing machine and language processing professors, and my work
> with compilers dictates to me is this:
>
> I don't see why the IF statement translates any different than the
> while/for loop. =A0both should
> translate to static sizes independent of =A0the number of interations
> that are completed:
>
> an IF translates to:
>
> <conditional jump> to else_part
> -- then code goes here
> <unconditional jump> to endif_xyz
> label else_part:
> --else code goes here
> label endif_xyz:
>
> and the WHILE would be:
>
> label topofwhile_xyz:
> <conditional jump> to end_of_while_xyz
> ---stuff to do
> <unconditional jump> to topofwhile_xyz
> label end_of_while_xyz:
>
> I was expecting the synth do work similarly.
>
> The data value of the number of iterations is swallowed up by the
> <conditional jump> and =A0thus the sizing of the "circuit" is
> independent of the number of interations. Bascially the synth forced
> me to manually build a for 1 to 10 loop, whereas there is no reason
> the synth couldn't of done it all by itself (see above WHILE loop
> pseudo-assembly code.)

I think you're missing the fact that the hardware synthesis
MUST unroll the loop.  i.e.  the entire loop runs concurrently
thereby creating hardware for each iteration.  It can't do that
for a loop whose iterations are not known at the time of
synthesis.

There may be some cases where a loop can be coded without
using for 1 to 10, but where the number of iterations is
known at synthesis time.  This does not necessarily mean
they are synthesizable.  The synthesis process uses templates
to fit your code into structures available in the underlying
hardware.  Synthesizable code must fit into the available
templates.

Regards,
Gabor

Article: 137390
Subject: Re: Counter: natural VS std_logic_vector
From: aleksa <aleksaZR@gmail.com>
Date: Tue, 13 Jan 2009 16:10:27 -0800 (PST)
Links: << >>  << T >>  << A >>
I've realized that "Slave tracks master"
can be changed to:

  if falling_edge(CLKMAIN) then
    sIRQ <= mIRQ;
    sACK <= mACK;
  end if;

After doing that, even the std_logic_vector
doesn't work as supposed.

Anyone?

Article: 137391
Subject: Re: beginner synthesize question - my debounce process won't synthesize.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 14 Jan 2009 01:20:08 +0000
Links: << >>  << T >>  << A >>
On Tue, 13 Jan 2009 14:18:16 -0800 (PST), jleslie48
<jon@jonathanleslie.com> wrote:

>On Jan 10, 8:54 pm, rickman <gnu...@gmail.com> wrote:

>
>I don't see why the IF statement translates any different than the
>while/for loop.  both should
>translate to static sizes independent of  the number of interations
>that are completed:
>
>an IF translates to:
>
><conditional jump> to else_part
>-- then code goes here
><unconditional jump> to endif_xyz
>label else_part:
>--else code goes here
>label endif_xyz:
>
>and the WHILE would be:
>
>label topofwhile_xyz:
><conditional jump> to end_of_while_xyz
>---stuff to do
><unconditional jump> to topofwhile_xyz
>label end_of_while_xyz:
>
>I was expecting the synth do work similarly.

The big difference between the two is this: 
in the While loop, the jump is _backwards_.

A more CS-oriented view would be that the difference between IF and
WHILE is exactly that between a directed acyclic and a cyclic graph.
Unrolling the loop is then transforming the cyclic graph into acyclic
form.

If you are decomposing the operation into machine instructions, and
executing them sequentially, that is no problem; it merely takes a very
long time.

But you aren't decomposing into anything sequential, unless you can
_force_ a serialisation, e.g. with a "wait until rising_edge(clk)" 
in the loop. (Which is unrecognised by XST. Incidentally I tried it in
the Altera synthesis tool. It fails too, interestingly the error is
"More than one Wait in Process" - therefore Altera is explicitly
unrolling the loop even before examining its contents!)

Therefore the ONLY ways are: (a) to force that serialisation (either as
above but in a better synthesis tool, if one exists), or explicitly in
the pattern you suggested (and criticise)
or (b) unroll the loop (e.g. use ten multipliers in prev example)

>The data value of the number of iterations is swallowed up by the
><conditional jump> and  thus the sizing of the "circuit" is
>independent of the number of interations.

I hope the above shows why it doesn't work that way.

- Brian


Article: 137392
Subject: Re: Digilent Nexys 2 Issue
From: "sidsarao83@gmail.com" <sidsarao83@gmail.com>
Date: Tue, 13 Jan 2009 18:55:29 -0800 (PST)
Links: << >>  << T >>  << A >>
I have been trying to make my FPGA work with Adept , but even though
it detects the USB....in Transport terminal i am not able to enter any
bits to read or write.....I am using windows vista

Sid

Article: 137393
Subject: Re: Counter: natural VS std_logic_vector
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 13 Jan 2009 22:06:30 -0500
Links: << >>  << T >>  << A >>

"aleksa" <aleksaZR@gmail.com> wrote in message 
news:d00953ce-136d-4644-8e90-662fd3ebc697@r40g2000yqj.googlegroups.com...
> I've realized that "Slave tracks master"
> can be changed to:
>
>  if falling_edge(CLKMAIN) then
>    sIRQ <= mIRQ;
>    sACK <= mACK;
>  end if;
>
> After doing that, even the std_logic_vector
> doesn't work as supposed.
>
> Anyone?

1. Have you simulated your design, and does it work?
2. Have you run static timing analysis and does it pass?
3. As I alluded to in my first post, Irq coming out of combinatorial logic 
can be a problem since it could easily glitch and thereby cause a false 
interrupt to occur.  If your processor has an internal timer you can log the 
times when your FPGA interrupts occur.  If there are some that differ 
significantly from 1ms than you'll be hot on the trail.

Kevin Jennings 



Article: 137394
Subject: ttl compatible
From: uraniumore238@gmail.com
Date: Tue, 13 Jan 2009 19:49:08 -0800 (PST)
Links: << >>  << T >>  << A >>
I have a spartan-3an starter kit, i would like to know if the chip on
the board is TTL compatible. If not, please suggest a device to make
the conversion.

Article: 137395
Subject: Re: ttl compatible
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Wed, 14 Jan 2009 02:30:37 -0600
Links: << >>  << T >>  << A >>
In article <90c0972a-f976-4c03-bb0a-5965b72985fe@v15g2000yqn.googlegroups.com>,
 uraniumore238@gmail.com writes:
>I have a spartan-3an starter kit, i would like to know if the chip on
>the board is TTL compatible. If not, please suggest a device to make
>the conversion.

Have you looked at the data sheet?

What do you mean by "TTL"?  Real (old) TTL?  5V CMOS?  3.3V CMOS?  ...

This is a common problem.  It would probably be worth your while
to poke around with google and look at the Xilinx web site.  They
probably have a good app-note discussing this area.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 137396
Subject: effect of channel capacity on hamming code
From: samar <samar.nayab@gmail.com>
Date: Wed, 14 Jan 2009 02:07:15 -0800 (PST)
Links: << >>  << T >>  << A >>
Can anybody plz tell me that what will be the effect of channel
capacity on hamming code.i want to know the answer of the following
question.
what is the optimal hamming code for the channel that has a capacity
of 0.998?
plz if anyone know the answer let me inknow by 15th jan 09 noon

Article: 137397
Subject: Re: Digilent Nexys 2 Issue
From: dave@axoninstruments.biz
Date: Wed, 14 Jan 2009 03:11:17 -0800 (PST)
Links: << >>  << T >>  << A >>
I now have it working with the latest software version.

When I got the board and downloaded the drivers, they didn't include a
driver for the USB interface on my board. This has since been updated
and now it works.

http://digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=69&Prod=ADEPT

Dave...

Article: 137398
Subject: Re: effect of channel capacity on hamming code
From: "RCIngham" <robert.ingham@gmail.com>
Date: Wed, 14 Jan 2009 05:34:51 -0600
Links: << >>  << T >>  << A >>
>Can anybody plz tell me that what will be the effect of channel
>capacity on hamming code.i want to know the answer of the following
>question.
>what is the optimal hamming code for the channel that has a capacity
>of 0.998?
>plz if anyone know the answer let me inknow by 15th jan 09 noon
>

Not really an FPGA question, is it?

Have you tried www.pleasedomyhomework.org?


Article: 137399
Subject: Re: effect of channel capacity on hamming code
From: ben@hometoolong.inv
Date: Wed, 14 Jan 2009 04:55:18 -0800
Links: << >>  << T >>  << A >>

Try the group comp.dsp



On Wed, 14 Jan 2009 02:07:15 -0800 (PST), samar
<samar.nayab@gmail.com> wrote:

>Can anybody plz tell me that what will be the effect of channel
>capacity on hamming code.i want to know the answer of the following
>question.
>what is the optimal hamming code for the channel that has a capacity
>of 0.998?
>plz if anyone know the answer let me inknow by 15th jan 09 noon



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