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kharray.bassas@gmail.com wrote: > Hi, > > I would like to know the voltage that supplies the configuration > logic in Virtex 5 , is it Vccaux ? Virtex4 and 5 have a dedicated bank (IIRC it's bank 0) for most of the configuration pins (JTAG pins, CCLK, etc.). The IOs are powered from whatever supply is connected to the VCCO-pins of that bank. The internal configuration logic is powered by VCCINT, I would assume. HTH, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 137501
Hi all, I'm working on a big project and have some problems respecting
all the timing constraints.
Setting the effort for MAP and PAR to the highest level and adding
some Area Group constraints I finally got an implementation that
respect the timing constraints.
Now I have to do a very small change because I found a little bug. The
change is very small and it should not affect the whole design ... but
it does, with this change the constraint are not respected any more.
So I'm trying with 'Guided Par' (using the ncd file of the successful
implementation) set to 'Exact' .. but the result is even worse than
the non-Guided Par, how is it possible?
Any hints?
Here is the report of Guided Pa, the change is locate in the
"AG_user_dsp_inst/ddc_pc_top_inst/pc_top_inst/imp_corto"
Area Group
Xilinx Place and Route Guide Results File
=========================================
Guide Summary Report:
Area Group: AG_user_dsp_inst/ddc_pc_top_inst/ddc_inst was found in
guide file
C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/ics8550_top_18.ncd.
Area Group: AG_user_dsp_inst/ddc_pc_top_inst/pc_top_inst/imp_corto
was found in guide file
C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/ics8550_top_18.ncd.
Area Group: AG_user_dsp_inst/ddc_pc_top_inst/pc_top_inst/
out_demux_inst was found in guide file
C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/ics8550_top_18.ncd.
Area Group: GRP0 was found in guide file C:/Progetti/ICS8550-L50/
G11464-002/ICS_8550/ics8550_top_18.ncd.
Design Totals:
Components:
Previously Placed Comps: 16607 out of 16607 100%
* Guide was not run on any placement.
Signals:
Pre-Routed Nets: 15 out of 36173 0%
Name matched: 36096 out of 36158 99%
Total guided: 36096 out of 36096 100%
Total connections guided: 8272
Area Group: "AG_user_dsp_inst/ddc_pc_top_inst/ddc_inst" Guide
mode: "exact"
Guide File: "C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/
ics8550_top_18.ncd"
Components:
Previously Placed Comps: 3493 out of 3493 100%
* Guide was not run on any placement.
Signals:
Name matched: 7875 out of 7876 99%
Total guided: 7875 out of 7875 100%
Total connections guided: 382
Area Group: "AG_user_dsp_inst/ddc_pc_top_inst/pc_top_inst/
imp_corto" Guide mode: "exact"
Guide File: "C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/
ics8550_top_18.ncd"
Components:
Previously Placed Comps: 1682 out of 1682 100%
* Guide was not run on any placement.
Signals:
Name matched: 4593 out of 4612 99%
Total guided: 4593 out of 4593 100%
Total connections guided: 0
Area Group: "AG_user_dsp_inst/ddc_pc_top_inst/pc_top_inst/
out_demux_inst" Guide mode: "exact"
Guide File: "C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/
ics8550_top_18.ncd"
Components:
Previously Placed Comps: 34 out of 34 100%
* Guide was not run on any placement.
Signals:
Area Group: "GRP0" Guide mode: "exact"
Guide File: "C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/
ics8550_top_18.ncd"
Components:
Previously Placed Comps: 4042 out of 4042 100%
* Guide was not run on any placement.
Signals:
Name matched: 10316 out of 10331 99%
Total guided: 10316 out of 10316 100%
Total connections guided: 0
Ungrouped Logic: Guide mode: "exact"
Guide File: "C:/Progetti/ICS8550-L50/G11464-002/ICS_8550/
ics8550_top_18.ncd"
Components:
Previously Placed Comps: 7356 out of 7356 100%
* Guide was not run on any placement.
Signals:
Pre-Routed Nets: 15 out of 13354 0%
Name matched: 13312 out of 13339 99%
Total guided: 13312 out of 13312 100%
Total connections guided: 7890
Article: 137502"PrAsHaNtH@IIT" <prashaenator@gmail.com> writes: > Hello frnds, > Hello, > I have to implement image enhancement techniques on fpga. Don't decide FPGAs are the answer too soon! Do you know what processing techniques? Are they suitable for using an FPGA to implement? How fast (frames per second, at what resolution) does this need to operate? What bit depth are your images? > Here, i have to give input image from ultrasonic machine or some image > capture device. After image is processed on FPGA, the output should be > displayed on monitor or it should be given to ultrasonic machine again > (For ultrasonic input). How can I give input pixel values to FPGA > from the capture device or ultrasonic machine. What's your capture device? If it's a chip simply take wires from the capture device, connect them to the pins of the FPGA and write the interface code. The practicalities of doing this wiring sometimes get in the way of course - a PCB is the usual way. If it's not a chip, but has a more industry standard interface (like Ethernet), then you'll need to connect an interface chip to the FPGA in between. > > Can we directly interface capture device with FPGA or > Should input image be first given to some software tool which converts > image into pixel values and to equivalent binary values. > Isn't that what a capture device does? What format might they be in which is not "equivalent binary values"? Sorry - more questions than answers :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 137503
On Tue, 20 Jan 2009 21:45:05 -0800 (PST), rickman wrote: >There was another company called Plus Logic but I really just can't >recall the structure of their devices. But I'm pretty sure they >wern't 4 LUTs. I believe they had a CPLD-like structure. They were absorbed by ??Altera after achieving some reasonable sales. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137504
Hi, I notice that Intel have an SOC part, the EP80579, which contains a technology called "QuickAssist" that is used to implement application specific functions in the "Acceleration Services Unit". Intel use the examples of crypto accelerators, TDM interfaces and HDLC engines implemented in this block in their datasheets. It appears that the QuickAssist block is actually a chunk of FPGA fabric, tied to an internal PCI-like bus. Does anyone know anything about the architecture, size or performance of this FPGA fabric? Thanks, Allan http://www.intel.com/design/intarch/ep80579/Article: 137505
On Tue, 20 Jan 2009 22:54:29 +0100, whygee wrote: >> Crosspoint had a very fine-grained architecture, but >> didn't survive long enough even to publish a second >> edition of their databook AFAIR. >Is it http://findarticles.com/p/articles/mi_m0EKF/is_/ai_12345853 ? I wasn't aware of the NEC/Crosspoint relationship but yes, that's it. Cypress sold clones of the QuickLogic pASIC1 parts for quite a few years - I still have a few unprogrammed 2K-gate parts, and a working programmer, in my attic :-) The QuickLogic architecture was very roughly the same granularity as 4LUT+FF in size, but the combinational logic was a mux with fairly wide AND gates on its select inputs, making it bettr than average at wide decodes but fairly feeble for arithmetic (they came up with a nifty conditional-sum adder macro to get reasonable speed). >Thank you for the pointers. You're welcome. I would love to see some of the FPGA old-timers (where are you when we need you, Peter Alfke!) write a definitive history of this stuff - I can easily imagine the folklore being lost for ever, quite soon. >BTW, I've also spotted M2000 >which is now http://www.aboundlogic.com >What are they really doing ? Ah, a Stealth Mode website. Thanks to *you* for the pointer! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137506
http://www.xilinx.com/ise/embedded/edk_examples.htmArticle: 137507
"Jan Bruns": > Everything looks like I'm just missing the startup to start > (DONE stays low, according to these status-registers). > .. > There's an Answer record in the xilinx database telling > this problem was a known issue with ISE9.4 (but for > Spartan3a/an), but I'm also not fully sure if I was > probably using some bitgen-switch when the problem > disappeared. http://www.xilinx.com/support/answers/22255.htm Does anyone have the same problem with the actual IMPACT 10.1.03 ? Gruss Jan BrunsArticle: 137508
Martin Thompson wrote: > Don't decide FPGAs are the answer too soon! Don't waste your breath. It's obviously an assignment/project as the poster has way too little clue what's going on and hasn't done any research what-so-ever. 'F'. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 137509
On Tue, 20 Jan 2009 20:17:23 +0000, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >On Tue, 20 Jan 2009 20:29:55 +0100, whygee wrote: > >>I knew the old MUX2-based FPGA from Actel (the A1020 that I studied >>and played with long ago in school), as well as the 4-LUT and dual 3-LUT, >>and the current 3-input tile from the Actel. >> >>What are the other granularities and architectures >>that have been tried ? My curiosity needs answers :-) > >Crosspoint had a very fine-grained architecture, but >didn't survive long enough even to publish a second >edition of their databook AFAIR. > >The curious architecture that was developed by >Pilkington and then taken over (and later dropped) >by (I think) Motorola was also very fine-grained - >right down to simple gates. The other fine grained one was of course Xilinx's own XC6200, originally developed in Edinburgh by Algotronics (bought out by Xilinx). Much loved by researchers because every detail of configuration and routing was made public; if there was ever a chance of a completely open-source toolchain, that was it. I believe the basic unit of logic was a 4-LUT and FF, nothing fancy. Consider that with current FPGAs, the area occupied by logic is dwarfed by the routing area. With fine grained logic that problem must be about an order of magnitude worse. Factor in the optimisation opportunities that more complex logic blocks give you; from hard-wired fast carry chains all the way up to multipliers or DSP units, and you can see why the trend is towards coarser grained logic. I would expect to see basic units like 8-bit blocks, with enough resources that you could fit a Z80 into half a dozen, in a generation or two. Forty thousand of them, as well as the block memory, I/O, DSP and a few ARMs or PPCs to supervise the lot. Time to dig out the old bit-slice databooks again? - BrianArticle: 137510
I am getting the following translate erroe in my design
ERROR:NgdBuild:809 - output pad net 'clk_288' has an illegal load:
pin C on block reg1/q_0 with type FDR,
pin C on block reg1/q_1 with type FDR,
pin C on block reg1/q_2 with type FDR,
pin C on block reg1/q_3 with type FDR,
pin C on block reg1/q_4 with type FDR,
pin C on block reg1/q_5 with type FDR,
pin C on block reg1/q_6 with type FDR,
pin C on block reg1/q_7 with type FDR,
pin C on block reg1/q_8 with type FDR,
pin C on block reg1/q_9 with type FDR,
pin C on block reg1/q_10 with type FDR,
pin C on block reg1/q_11 with type FDR,
pin C on block reg1/q_12 with type FDR,
pin C on block reg1/q_13 with type FDR,
pin C on block reg1/q_14 with type FDR,
pin C on block reg1/q_15 with type FDR,
pin C on block vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/
USER_CLK_REG
with type FDE,
pin C on block vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/
U_SYNC_R with
type FDRE,
pin C on block vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/
U_SYNC_F with
type FDRE,
pin C on block
vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/sync_f_edge/
I_H2L.U_DOUT with
type FDR
I am using an output DDR flip flop to create the clk_288 signal which
further drives the CLK input of other signals.
OFDDRRSE ddr_flop_inst(
.Q( clk_288 ),
.C0( adc1_dry_p ),
.C1( adc1_dry_n ),
.CE( 1'b1 ),
.D0( adc1_dry_p ),
.D1( adc1_dry_n ),
.R( ~fpga_reset_n_temp ),
.S( 1'b0 )
);
Please suggest a solution. Thanks in advance
Article: 137511FP wrote: > I am getting the following translate erroe in my design > > ERROR:NgdBuild:809 - output pad net 'clk_288' has an illegal load: > I am using an output DDR flip flop to create the clk_288 signal which > further drives the CLK input of other signals. AFAIK, ODDR flip flops are inside the IOBs, their outputs can only drive IO-pins, not internal logic. Similarly, IDDR inputs can only be external pins, not internal signals. I'm not sure what you're trying to do here, but if you want a 2x clock for internal use, you'll have to use a DCM or so to multiply the clock, or do some other magic trickery. Or is "adc_dry" a differential signal that you want to use as a clock? In that case use an IBUFGDS. BTW, the way you described it, even if routing-wise it would be possible, your clk_288 would be constant '1', I believe. HTH, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 137512
On Jan 21, 9:06=A0am, Sean Durkin <news_MO...@tuxroot.de> wrote: > FP wrote: > > I am getting the following translate erroe in my design > > > ERROR:NgdBuild:809 - output pad net 'clk_288' has an illegal load: > > I am using an output DDR flip flop to create the clk_288 signal which > > further drives the CLK input of other signals. > > AFAIK, ODDR flip flops are inside the IOBs, their outputs can only drive > IO-pins, not internal logic. Similarly, IDDR inputs can only be external > pins, not internal signals. > > I'm not sure what you're trying to do here, but if you want a 2x clock > for internal use, you'll have to use a DCM or so to multiply the clock, > or do some other magic trickery. Or is "adc_dry" a differential signal > that you want to use as a clock? In that case use an IBUFGDS. > > BTW, the way you described it, even if routing-wise it would be > possible, your clk_288 would be constant '1', I believe. > > HTH, > Sean > > -- > Replace "MONTH" with the three-letter abbreviation of the current month > (simple, eh?). You are right. I want a 2x clock for internal use =3D 2 x adc_dry. Can I do this using a DDR flip flop or the only option is to use a DCM.Article: 137513
FP wrote: > You are right. I want a 2x clock for internal use = 2 x adc_dry. Can I > do this using a DDR flip flop or the only option is to use a DCM. As I said earlier: you cannot use ODDR outputs to drive internal signals. You'll have to use a DCM. HTH, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 137514
On 2009-01-21, jleslie48 <jon@jonathanleslie.com> wrote: > and ironically the sample chapter supplied on that webpage is exactly > the chapter that I am interested in: > > http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdf I took a brief look at this and happened to notice that the author forgot to synchronize the rx input signal. So if you follow this example, add one flip-flop to avoid race conditions and another flip-flop to reduce the probability of metastability issues to near zero. I have emailed the author about this so hopefully he'll fix this. (Well, that or I just missed the synchronization which would be very embarrasing for me :)) If you are not aware of why you need to synchronize an input signal you could read a longer post I wrote at the following URL: http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/6b6e98a506ee4b07?hl=sv&ie=UTF-8#1f3c160b2264c029 Or you could of course look it up in some textbook on digital design. /AndreasArticle: 137515
"Sean Durkin" <news_MONTH@tuxroot.de> wrote in message news:6toprsFbsc1oU1@mid.individual.net... > FP wrote: >> You are right. I want a 2x clock for internal use = 2 x adc_dry. Can I >> do this using a DDR flip flop or the only option is to use a DCM. > > As I said earlier: you cannot use ODDR outputs to drive internal > signals. You'll have to use a DCM. > > HTH, Sean > He can if he instantiates an IBUF. Doesn't solve his problem, but he can do it. Syms.Article: 137516
You will find beginner tutorials for the XUPV2P board on the FPGA Developer website: http://www.fpgadeveloper.com Specifically for getting RS232 communications working, try the "Base System Builder" tutorial.Article: 137517
Hi all, I'm an Italian student, I'm new in fpga and Microblaze implementation. I saw many starting tutorials about ML505 Xilinx Platform and usa of Xilinx Platform Studio 10.1 and EDK. In these tutorials I did not found any example of reading and writing operation of the SRAM. My code reside in BRAM and I would like to try to store some values in SRAM. By BSB I implemented SRAM in my system connected to microblaze by SPLB and xps_mch_emc. Now: What are the instructions to read and write this memory? It's a simply question but I can't find any answer... please help me. Thanks (I apologize for my bad english) DanieleArticle: 137518
"Gabor" <gabor@alacron.com> wrote in message
news:81b3390e-eb24-4a05-b898-3ecb161bc7a5@n10g2000vbl.googlegroups.com...
On Jan 19, 5:43 pm, "Dan Kuechle" <danie...@visi.com> wrote:
> Could someone help please, I'm trying to get a differential bi-directional
> signal working in a VHDL design targeting a Virtex 5.
> I can change the signal to "in" and use a "IBUFDS" and that works.
> I can change the signal to "out" and use a "OBUFTDS" and that works.
> But when I change the signal to "inout" and use a "IOBUFDS" (or
> instantiate
> both a IBUFDS and a IOBUFDS) I get the following 2 errors.
> (the two differential I/O pads are ddr2_dqs and ddr2_dqs_n)
>
> ERROR:PhysDesignRules:368 - The signal <ddr2_dqs_n> is incomplete. The
> signal
> is not driven by any source pin in the design.
>
> ERROR:PhysDesignRules:10 - The network <ddr2_dqs_n> is completely
> unrouted.
>
> Any help would be appreciated
>
> Dan
In a working example from MIG 2.3, the DQS lines are hooked up
like:
u_iobuf_dqs : IOBUFDS
port map (
O => dqs_ibuf,
IO => ddr_dqs,
IOB => ddr_dqs_n,
I => dqs_out,
T => dqs_oe_n_r
);
where ddr_dqs and ddr_dqs_n are declared inout std_logic at the top
level.
-------------------
Thanks for responding. Turns out this was a bug with the Virtex5 IOBUFDS in
ISE 9.2i (sp4). A patch was available (new .dll file). The hard part was
trying to find the answer as it didn't show up when searching for what I
thought was a good description of the problem. Only when I searched for
"iobufds" and waded through all the hits did I find the one I needed.
OBUFTDS Slave IOB has incorrect connectivity on tristate enable
Dan
Article: 137519Symon wrote: > He can if he instantiates an IBUF. Doesn't solve his problem, but he can do > it. Cool, didn't know that worked. I've had the tools go bananas on me in less "exotic" configurations, so that's a little surprise. :) cu, SeanArticle: 137520
Andreas Ehliar wrote: > The following URL may be of interest to you: > http://www.eecg.toronto.edu/~jayar/pubs/kuon/foundtrend08.pdf > "FPGA Architecture: Survey and Challenges" Excellent !! > I would also like to read some early FPGA development folklore, both > hardware and software anecdotes. (I'm young enough to take HDL:s and > decent CAD software for granted so the software side is also > interesting to me. I have a feeling that I'm somewhat spoiled...) me too :-) > /Andreas thank you ! -- http://ygdes.com / http://yasep.orgArticle: 137521
On Jan 21, 8:00=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > Consider that with current FPGAs, the area occupied by logic is dwarfed > by the routing area. With fine grained logic that problem must be about > an order of magnitude worse. Factor in the optimisation opportunities > that more complex logic blocks give you; from hard-wired fast carry > chains all the way up to multipliers or DSP units, and you can see why > the trend is towards coarser grained logic. I don't think that is anything new. Back when the XC4000 was new I was told that "We sell you the routing and give you the logic for free". > I would expect to see basic units like 8-bit blocks, with enough > resources that you could fit a Z80 into half a dozen, in a generation or > two. Forty thousand of them, as well as the block memory, I/O, DSP and a > few ARMs or PPCs to supervise the lot. Personally, I would like to see larger functional units as that would reduce the complexity of the routing fabric. But I think it would be too much of an impact on the software to properly utilize it effectively. I am sure this will come, but not in the next few years. Then again, doesn't the Stradix use 6-LUTs? > Time to dig out the old bit-slice databooks again? I should still have a copy of Mick and Brick around somewhere. RickArticle: 137522
Hello ! Jonathan Bromley wrote: > The QuickLogic architecture was "was" ? I thought that Quicklogic still exists ... hmmm <google><google><google>... http://www.fpga-guide.com/overview/overview.html ==> OK : last product released in 2003. This page shows that only 4 players remain : Altera, Actel, Lattice & Xilinx. It will need a good update soon since SiliconBlue seems to be on the good tracks, and maybe one or two other new companies are trying to emerge. Interesting times... > very roughly the same > granularity as 4LUT+FF in size, but the combinational > logic was a mux with fairly wide AND gates on its > select inputs, making it bettr than average at wide > decodes but fairly feeble for arithmetic My concern is that by ignoring the past, people will "reinvent" things... It happened to me several time ;-) What is more interesting is that maybe, old ideas that failed in the past (for commercial/marketing or technology reasons) could succeed later... >> Thank you for the pointers. > You're welcome. I would love to see some of the FPGA > old-timers (where are you when we need you, Peter Alfke!) > write a definitive history of this stuff - I can easily > imagine the folklore being lost for ever, quite soon. I second that. >> BTW, I've also spotted M2000 >> which is now http://www.aboundlogic.com >> What are they really doing ? > Ah, a Stealth Mode website. Thanks to *you* for > the pointer! No problem. I just called the french office (I'm french) and ... surprise ! I spoke with an ex-co-worker :-) He expects announcements by the end of the year and he will keep me informed. Expect a familiar-looking 4-LUT btw, unless things really changed :-) Now, if only they needed an Open Source Evangelist in their team, I would sign again ;-) regards, yg -- http://ygdes.com / http://yasep.orgArticle: 137523
On Jan 21, 10:53 am, "jeffrey.johnson" <j...@fpgadeveloper.com> wrote: > You will find beginner tutorials for the XUPV2P board on the FPGA Developer > website: > > http://www.fpgadeveloper.com > > Specifically for getting RS232 communications working, try the "Base > System Builder" tutorial. I will be taking a look shortly. Right now I'm going ahead with the RS232 example from the great book: FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx SpartanTM-3V ersion Pong P. Chu Cleveland State University the authors website has even a download of the examples: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html and ironically the sample chapter supplied on that webpage is exactly the chapter that I am interested in: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdfArticle: 137524
On Jan 21, 10:53 am, "jeffrey.johnson" <j...@fpgadeveloper.com> wrote: > You will find beginner tutorials for the XUPV2P board on the FPGA Developer > website: > > http://www.fpgadeveloper.com > > Specifically for getting RS232 communications working, try the "Base > System Builder" tutorial. Yes, I looked at that example. It uses the powerPC which I don't believe I have access to, my project is supposed to use the xc2vp30 only and not another chipset, or did I just say something really stupid (ie, I don't have a clue what the powerpc is, and is it part of the the xc2vp30?)
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