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Messages from 136800

Article: 136800
Subject: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
From: Gabor <gabor@alacron.com>
Date: Fri, 5 Dec 2008 14:13:01 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 5, 3:19=A0pm, LittleAlex <alex.lo...@email.com> wrote:
> On Dec 5, 3:37 am, "water9...@yahoo.com" <water9...@yahoo.com> wrote:
>
> > The 345th line of dma_ddr2_if.v file is:
>
> > =A0 =A0xfer_cnt =A0 <=3D xfer_cnt - 3'b10;
>
> > why to subtract 2,not 1? eg: read 64bytes data from SDRAM.it needs
> > four times for 16bytes/xfer. But,it only reads two times because the
> > counter =A0subtract 2. I only get 32bytes data,other 32bytes is lost.
>
> > is it a bug?
>
> No. =A0You subtract "2" because of the first "D" in "DDR".

Because most of the logic for DDR SDRAM looks just like single-
data rate SDRAM, there is a tendency to look at the interface
as if you had a single-data rate part with twice the bus width.
This does not hold for column address.  i.e. when you use this
view of the chip, the column address should always be even.

Also remember that the number of transfers in a burst is
twice the number of clock cycles, i.e. it's counting 16-bit
DDR transfers, not 32-bit data transfers after your DDR
input flops.  So if you set the burst length to 8, there are
only 4 pulses on DQS per burst.

Article: 136801
Subject: Re: SystemVerilog OOP and OVM Summary
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 05 Dec 2008 17:40:07 -0800
Links: << >>  << T >>  << A >>
Amal wrote:
> Here is a presentation I prepared that summarizes the some of the
> SystemVerilog OOP and OVM v2.0 features.
> 
>   http://www.slideshare.net/akhailtash/ovm-features-summary-presentation/

Nice presentation.
Thanks for the posting.

This may be a tough sell
to the structurally oriented hardware guy
who won't even write a function ;)

       -- Mike Treseler

Article: 136802
Subject: Re: Project/File corruption problem with ISE 10.1
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Sat, 06 Dec 2008 01:52:32 +0000
Links: << >>  << T >>  << A >>
On Fri, 5 Dec 2008 09:30:08 -0800 (PST), Bryan
<bryan.fletcher@avnet.com> wrote:

>If cleaning up the project files doesn't work, you can then try using
>the .restore script in the project directory.  I recently had a
>problem with ISE Simulator producing incorrect simulation results from
>a Project Navigator project, and the root cause was determined to be a
>corrupt .ise file.  I opened a case with Xilinx, and they used
>the .restore script to fix it.  The .restore file is text, so open it
>in a text editor and follow the instructions.

Heh.

Glad to hear it works sometimes.

It is also possible, after a project file corruption, to exit ISE and go
online searching for information before trying the .restore file.
Trouble is, the restore file has probably now been updated to match the
corrupt project.

Don't ask me any more about it. Just back them both up. 
(.prj and .restore)
Now.

- Brian

Article: 136803
Subject: Invalid devices when initialising scan chain with Nexys2
From: "freespace@gmail.com" <freespace@gmail.com>
Date: Fri, 5 Dec 2008 18:27:16 -0800 (PST)
Links: << >>  << T >>  << A >>
G'day all,

I am a student studying EE/Physics, and after completing my 2nd year
digital design course, I decided to take things further and purchased
a digilent Nexys2 for myself to do further tinkering with. I am
however struggling with the most basic of tasks: getting digilent's
ExPort program to successfully initialise the scan chain.

I get the following log:

Found Device.  IDCODE:  f5046093
Found Device.  IDCODE:  21c2e093
Found Device.  IDCODE:  invalid
Found Device.  IDCODE:  invalid
Found Device.  IDCODE:  invalid
<snip>
Found Device.  IDCODE:  invalid
Initialization failed

There is a total of 29 devices for which the IDCODE was invalid. JP9
on the board has been set to JTAG, and pins 2 and 3 of JP5, the JTAG
port has been shorted - this shorts TDI and TDO. I don't see any other
jumpers on board which could influence the JTAG chain, and have
verified by looking the schematic (sheet 04).

Things I have tried:

* 3x USB cables: digilent's, one for a portable USB HDD, one for a
portable CDROM, in order of decreasing length
* unshort TDI and TDO, though as far as I can tell it has no effect
whatsoever.
* slow and fast programming mode
* reinstalling the drivers
* reinstalling windows
* reinstalling Xilinx WebPACK
* different USB ports
* turning it on and off again and again and again...
* went to sleeping hoping it will work in the morning
   (props to A5 of http://www.fpga-faq.com/FAQ_Pages/0001_JTAG_Config.htm)
* googled for nexys2 and read every pdf on the first 3 pages returned
looking for something I missed

So now I am stuck with a rather expensive (on my student earning) self-
gratifying-early-Christmas-present which I can't do anything with,
other than get it to load the factory test program and play with the
blinken lights. As fun as that is, I would _love_ to be able to do
more with it.

If this august group can assist in resolving this issue, it would be
fantastic. If nothing else, if some one can kindly post that they a)
have their Nexys2 working and b) inform me of the software and
hardware configuration, that would warm my cockles.

Cheers,
Steve

Article: 136804
Subject: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
From: "water9580@yahoo.com" <water9580@yahoo.com>
Date: Fri, 5 Dec 2008 18:27:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On 12=D4=C26=C8=D5, =C9=CF=CE=E76=CA=B113=B7=D6, Gabor <ga...@alacron.com> =
wrote:
> On Dec 5, 3:19 pm, LittleAlex <alex.lo...@email.com> wrote:
>
> > On Dec 5, 3:37 am, "water9...@yahoo.com" <water9...@yahoo.com> wrote:
>
> > > The 345th line of dma_ddr2_if.v file is:
>
> > >    xfer_cnt   <=3D xfer_cnt - 3'b10;
>
> > > why to subtract 2,not 1? eg: read 64bytes data from SDRAM.it needs
> > > four times for 16bytes/xfer. But,it only reads two times because the
> > > counter  subtract 2. I only get 32bytes data,other 32bytes is lost.
>
> > > is it a bug?
>
> > No.  You subtract "2" because of the first "D" in "DDR".
>
> Because most of the logic for DDR SDRAM looks just like single-
> data rate SDRAM, there is a tendency to look at the interface
> as if you had a single-data rate part with twice the bus width.
> This does not hold for column address.  i.e. when you use this
> view of the chip, the column address should always be even.
>
> Also remember that the number of transfers in a burst is
> twice the number of clock cycles, i.e. it's counting 16-bit
> DDR transfers, not 32-bit data transfers after your DDR
> input flops.  So if you set the burst length to 8, there are
> only 4 pulses on DQS per burst.

So,how should i read 64bytes data from 0x0 base address(DDR2 burst
length=3D4)?
Is should the xfer_cnt    8 or 4?


Article: 136805
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: "freespace@gmail.com" <freespace@gmail.com>
Date: Fri, 5 Dec 2008 18:48:40 -0800 (PST)
Links: << >>  << T >>  << A >>
Add to the tried list:

* powering the board externally using a 5V external power supply
(LM7805 backed by a 6V unregulated plug back), so it is not a usb-
power related issue

Article: 136806
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: "freespace@gmail.com" <freespace@gmail.com>
Date: Fri, 5 Dec 2008 18:56:06 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 6, 1:27=A0pm, "freesp...@gmail.com" <freesp...@gmail.com> wrote:
> G'day all,
>
> I am a student studying EE/Physics, and after completing my 2nd year
> digital design course, I decided to take things further and purchased
> a digilent Nexys2 for myself to do further tinkering with. I am
> however struggling with the most basic of tasks: getting digilent's
> ExPort program to successfully initialise the scan chain.
>
> I get the following log:
>
> Found Device. =A0IDCODE: =A0f5046093
> Found Device. =A0IDCODE: =A021c2e093
I have just checked the above IDs: they correspond to the correct
Xilinx devices, as expected. So the devices which are suppose to be
there, are there.

Article: 136807
Subject: Re: V5 JTAG download weirdness
From: brimdavis@aol.com
Date: Fri, 5 Dec 2008 19:39:39 -0800 (PST)
Links: << >>  << T >>  << A >>
Yesterday, I wrote:
>
> 1. Mode selection of Master/SPI interferes with JTAG download???
>
>    I suspect this is the cause of some of my problems; I used
>   zero ohm R's to set the mode pins, my first change tomorrow
>   will be to switch the mode pins to JTAG.
>

Update:

 Switching from Master/SPI mode to JTAG mode during
the indirect SPI programming cleared up the problems
with recognizing and programming the M25P SPI FLASH
via indirect mode from the V5LX50.

{ Also note that before using IMPACT indirect SPI
programming with a chain of FPGAs, one must first
configure all the other FPGAs via JTAG before
attempting to program the SPI flash, otherwise
DONE is never released for the indirect SPI core
to startup in the Master FPGA.  I'd done that
yesterday as well, but indirect download still
had failed with the mode pins set to Master/SPI }

 The FPGA download chain still doesn't configure
properly from the SPI flash after setting the mode
pins back to Master/SPI and power cycling, but that's
probably some other issue to discover.

Brian

Article: 136808
Subject: How to save added signals to waveform viewer
From: xilinx_user <barrinst@ix.netcom.com>
Date: Fri, 5 Dec 2008 23:17:16 -0800 (PST)
Links: << >>  << T >>  << A >>
I am using ISE Webpack 10.1 along with the lite version of the
simulator. I can't seem to figure out how to save signals I added to
the waveform viewer so that I can use the same signal set at a future
time.

I know this is a naive question, but I have been away from the tools
for some time and need to come back up to speed.

Article: 136809
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: Glen Herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sat, 06 Dec 2008 02:27:08 -0700
Links: << >>  << T >>  << A >>
freespace@gmail.com wrote:
(snip)
> I get the following log:

> Found Device.  IDCODE:  f5046093
> Found Device.  IDCODE:  21c2e093
> Found Device.  IDCODE:  invalid
> Found Device.  IDCODE:  invalid
> Found Device.  IDCODE:  invalid

I don't have this board so I might be just guessing,
but is there any reason that Xilinx software should recognize
non-Xilinx devices?

-- glen


Article: 136810
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: "freespace@gmail.com" <freespace@gmail.com>
Date: Sat, 6 Dec 2008 01:46:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 6, 8:27=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> freesp...@gmail.com wrote:
>
> (snip)
>
> > I get the following log:
> > Found Device. =A0IDCODE: =A0f5046093
> > Found Device. =A0IDCODE: =A021c2e093
> > Found Device. =A0IDCODE: =A0invalid
> > Found Device. =A0IDCODE: =A0invalid
> > Found Device. =A0IDCODE: =A0invalid
>
> I don't have this board so I might be just guessing,
> but is there any reason that Xilinx software should recognize
> non-Xilinx devices?
>
Are you referring to IDs f5046093 and 21c2e093? Those appear to be
Xilinx devices. I don't expect Xilinx to recognise non-Xilinx devices
either, but that is not what is causing the invalid IDCODE messages:
there are _only_ 2 devices on the board connected to the JTAG chain.
My problem is there appears to be 29 other devices which aren't there,
but is detected. This is causing Digilent's ExPort program to fail and
thus preventing me from doing anything with the Nexys2.

Cheers,
Steve

Article: 136811
Subject: Re: hi all
From: wallra <khamitkar.ravikant@gmail.com>
Date: Sat, 6 Dec 2008 05:18:48 -0800 (PST)
Links: << >>  << T >>  << A >>
the fpga is configured and other peripherals work very well like leds
and switches.
as i am just using a test_peripheral_appl.c in the design of edk tools
procedure.
and standard output is rs232 so it should show on the hyperterminal.
though it is not showing.

another thing is that i am using standard db9 pin connector cable to
have connection.
is it necessary to have a cable with only three connection like tx rx
and gnd.
and others are short like cts and rts and other ack signal of 9pin.
please let me know.
thanks alot.

Article: 136812
Subject: Xiic with low lvl interrupts
From: simax <opitz.frank@googlemail.com>
Date: Sat, 6 Dec 2008 07:06:01 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello everybody ...

Im trying to code an isr for the xiic Ip from Xilinx EDK.
I did everything like tht documentation says but it wont work.

i get an interrupt when the modul is adressed as slave and its the AAS
irq.
After i get it, ill reset the interrupt that it is acknowledged but it
wont work ..

thats how my isr looks like ...


void iic_1_handler(void * baseaddr_p) {

 XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK, 0x03);

   if(XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR) & XIIC_INTR_AAS_MASK){
     XIIC_GINTR_DISABLE(XPAR_XPS_IIC_1_BASEADDR);
     XIic_mWriteReg
(XPAR_XPS_IIC_1_BASEADDR,XIIC_IIER_OFFSET,XIIC_READ_IISR
(XPAR_XPS_IIC_1_BASEADDR));
     XIIC_GINTR_ENABLE(XPAR_XPS_IIC_1_BASEADDR);
     XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK,
XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR));

   }

}
does anyone have an working controll flow?

thx for help

Article: 136813
Subject: Re: Modelsim warning message
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 06 Dec 2008 18:08:22 +0000
Links: << >>  << T >>  << A >>
On Thu, 4 Dec 2008 12:27:52 -0800 (PST), Aiken wrote:

>In my design, I set the  the memory module read enable forever.
>when I try to write the memory module, the models sim will generate a
>warning about the read output may not correct.

I think you will find this is a message from the 
simulation model of the memory.  It is certainly not
coming directly from Modelsim.

>Can I do something to "filter out" the warning?

Take a look at the memory simulation model.  It is quite
likely that it has a generic or parameter that you can
change to enable or disable this message.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 136814
Subject: Re: SystemVerilog OOP and OVM Summary
From: cms <Michael.Tsvetkov@gmail.com>
Date: Sat, 6 Dec 2008 10:09:13 -0800 (PST)
Links: << >>  << T >>  << A >>
Great job! Thank's a lot.

Digitally yours,
 cms

Article: 136815
Subject: Re: V5 JTAG download weirdness
From: Gabor <gabor@alacron.com>
Date: Sat, 6 Dec 2008 14:34:13 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 5, 10:39=A0pm, brimda...@aol.com wrote:
> Yesterday, I wrote:
>
> > 1. Mode selection of Master/SPI interferes with JTAG download???
>
> > =A0 =A0I suspect this is the cause of some of my problems; I used
> > =A0 zero ohm R's to set the mode pins, my first change tomorrow
> > =A0 will be to switch the mode pins to JTAG.
>
> Update:
>
> =A0Switching from Master/SPI mode to JTAG mode during
> the indirect SPI programming cleared up the problems
> with recognizing and programming the M25P SPI FLASH
> via indirect mode from the V5LX50.
>
> { Also note that before using IMPACT indirect SPI
> programming with a chain of FPGAs, one must first
> configure all the other FPGAs via JTAG before
> attempting to program the SPI flash, otherwise
> DONE is never released for the indirect SPI core
> to startup in the Master FPGA. =A0I'd done that
> yesterday as well, but indirect download still
> had failed with the mode pins set to Master/SPI }
>
> =A0The FPGA download chain still doesn't configure
> properly from the SPI flash after setting the mode
> pins back to Master/SPI and power cycling, but that's
> probably some other issue to discover.
>
> Brian

If you have trouble with the common DONE pin on several
devices, consider setting the "enable internal DONE pipe"
check box in the bit file generation properties.  This
causes the V5 to ignore the DONE pin and use the internal
DONE signal to complete the startup process.  I found that
this also fixes a problem when the startup clock is fast
enough to cause sampling of DONE for the startup pipe to
happen while the DONE pin was still slewing towards high
due to the limited pullup strength of the external resistor.
This can lead to DONE being sampled while in the logic
threshold region and messing up the remainder of the
startup pipe.  My system uses slave serial configuration
mode with a 100 MHz CCLK and 330 ohm pullup with no other
chips sharing the DONE signal, so with multiple chips
this problem may show up with a slower clock as well.

Regards,
Gabor

Article: 136816
Subject: Re: hi all
From: Gabor <gabor@alacron.com>
Date: Sat, 6 Dec 2008 14:37:08 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 6, 8:18=A0am, wallra <khamitkar.ravik...@gmail.com> wrote:
> the fpga is configured and other peripherals work very well like leds
> and switches.
> as i am just using a test_peripheral_appl.c in the design of edk tools
> procedure.
> and standard output is rs232 so it should show on the hyperterminal.
> though it is not showing.
>
> another thing is that i am using standard db9 pin connector cable to
> have connection.
> is it necessary to have a cable with only three connection like tx rx
> and gnd.
> and others are short like cts and rts and other ack signal of 9pin.
> please let me know.
> thanks alot.

You don't need the extra signals for hyperterminal if you make
sure that the settings for handshaking are set to "none" rather
than hardware or software.

Article: 136817
Subject: Re: V5 JTAG download weirdness
From: brimdavis@aol.com
Date: Sat, 6 Dec 2008 19:04:09 -0800 (PST)
Links: << >>  << T >>  << A >>
Gabor wrote:
>
>>  Also note that before using IMPACT indirect SPI
>> programming with a chain of FPGAs, one must first
>> configure all the other FPGAs via JTAG before
>> attempting to program the SPI flash, otherwise
>> DONE is never released for the indirect SPI core
>> to startup in the Master FPGA.
>
> consider setting the "enable internal DONE pipe" check box
> in the bit file generation properties.  This causes the
> V5 to ignore the DONE pin and use the internal DONE signal
> to complete the startup process.
>
 Thanks for pointing that out; I'd noticed that option before,
but thought it just delayed the internal DONE by one startup
clock cycle, without realizing that it also switched to an
internal DONE signal instead of looking at the DONE pin.

 That should be helpful in diagnosing a variety of chain
startup problems.

 In the specific case of the IMPACT indirect SPI core
download process, I don't know of any way to check/change
the settings of the indirect SPI core being automatically
downloaded by IMPACT, so I think I'll have to continue with the
load-dummy-design-bit-files-before-programming-flash shuffle.

>
> I found that this also fixes a problem when the startup
> clock is fast enough to cause sampling of DONE for the
> startup pipe to happen while the DONE pin was still
> slewing towards high due to the limited pullup strength
> of the external resistor. This can lead to DONE being
> sampled while in the logic threshold region and messing
> up the remainder of the startup pipe.
>
 I don't think the DONE risetime is the cause of my
problem #2 JTAG download order variations, but I haven't
yet measured the actual DONE risetime for this new design.
( I've tried both 6 or 12 MHz TCK for JTAG download,
and the slowest CCLK setting for MASTER SPI boot )

 The post-download status registers ( AR #24024 ) say all
systems are go with DONE/GWE/GTS/GHIGH set properly no
matter the order of download; but I still see the order
dependent variations in static supply current.

 I'll have a look Monday to see if that DONE pipe bit has
any effect.

thanks,
Brian

Article: 136818
Subject: ISE doesn't work after a crash
From: Nemesis <nemesis@nowhere.invalid>
Date: 07 Dec 2008 10:09:39 GMT
Links: << >>  << T >>  << A >>
Hi all,

I have this problem, yesterday Project Navigator (ISE8.2) crashed while
opening a project, a serious crash, the system was restarted automatically. I
tried to open the project again, and PN crashed again, this time without
restarting the computer, but I got messages like "The memory cannot be read
..." etc. etc. I tried again to open the project, this time no errors, but it
seems that the project file is damaged, the project is not loaded, I get only
some strange characters in the Sources Pane. Now this happens also with other
projects. Of course I'm sure that the projects are good, I tested them on a
different computer. In few words, ISE is not working anymore on this computer.

I got this problem in the past with ISE7.1, the solution was to format the
PC, even removing and reinstalling ISE didn't solve the problem. I really
would like to evitate formatting the computer this time, any hints?


Regards. 
-- 
It's not the voting that's democracy, it's the counting.
 _  _                  _
| \| |___ _ __  ___ __(_)___
| .` / -_) '  \/ -_|_-< (_-<
|_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.org


Article: 136819
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: Oscar <o.almer@gmail.com>
Date: Sun, 7 Dec 2008 04:11:31 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 6, 9:46=A0am, "freesp...@gmail.com" <freesp...@gmail.com> wrote:
> On Dec 6, 8:27=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:> =
freesp...@gmail.com wrote:
>
> > (snip)
>
> > > I get the following log:
> > > Found Device. =A0IDCODE: =A0f5046093
> > > Found Device. =A0IDCODE: =A021c2e093
> > > Found Device. =A0IDCODE: =A0invalid
> > > Found Device. =A0IDCODE: =A0invalid
> > > Found Device. =A0IDCODE: =A0invalid
>
> > I don't have this board so I might be just guessing,
> > but is there any reason that Xilinx software should recognize
> > non-Xilinx devices?
>
> Are you referring to IDs f5046093 and 21c2e093? Those appear to be
> Xilinx devices. I don't expect Xilinx to recognise non-Xilinx devices
> either, but that is not what is causing the invalid IDCODE messages:
> there are _only_ 2 devices on the board connected to the JTAG chain.
> My problem is there appears to be 29 other devices which aren't there,
> but is detected. This is causing Digilent's ExPort program to fail and
> thus preventing me from doing anything with the Nexys2.

Its almost like something is broken in the JTAG interface.
IIRC, this can happen if the host fails to find the end of the IDCODE
register when doing an initialization scan.
It looks like it reads in an extra 29 devices (likely all 1's) and
then stops because of a software 'timeout' (a neat 31 devices in an
array); it then cant find the device description files for the
spurious 29, and tells you that. I seem to remember that the way it's
supposed to detect the end of the scan chain is the lack of a '1' as a
first bit in the n+1 IDCODE out. If TDO is stuck high after the two
first devices, youd get something very much like what you sre seeing.

I'd try another JTAG scan tool to see what *that* reports.

Of course, I could also be dead wrong and its due to something
entirely different.

//Oscar

Article: 136820
Subject: Re: ISE doesn't work after a crash
From: Mike Treseler <mtreseler@gmail.com>
Date: Sun, 07 Dec 2008 09:28:04 -0800
Links: << >>  << T >>  << A >>
Nemesis wrote:

> I have this problem, yesterday Project Navigator (ISE8.2) crashed while
> opening a project, a serious crash, the system was restarted automatically. 

I would try a free trial on ise10.1

    -- Mike Treseler

Article: 136821
Subject: Re: ISE doesn't work after a crash
From: Nemesis <nemesis@nowhere.invalid>
Date: 07 Dec 2008 17:32:57 GMT
Links: << >>  << T >>  << A >>
Mike Treseler wrote:

> Nemesis wrote:
>
>> I have this problem, yesterday Project Navigator (ISE8.2) crashed while
>> opening a project, a serious crash, the system was restarted automatically. 
>
> I would try a free trial on ise10.1

Already tried, ise10.1 is not able to synthesize my project, I got some
warnings about multiple ngc files for some ip-cores I used then the process
stops, "Process Synthesize failed".
Of course the process is synthesizable with ise8.2. I should investigate but I
have little time, right now the better solution is to bring ise8.2 back to
work.


 Of course I checked, and there are no multiple ngc files ... or I didn't
understand well the message.
-- 
A newspaper consists of just the same number of words, whether there be
any news in it or not.
 _  _                  _
| \| |___ _ __  ___ __(_)___
| .` / -_) '  \/ -_|_-< (_-<
|_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.org


Article: 136822
Subject: Re: ISE doesn't work after a crash
From: no_spa2005@yahoo.fr
Date: Sun, 7 Dec 2008 11:09:57 -0800 (PST)
Links: << >>  << T >>  << A >>
ISE10.1 SP3 is working fine. Perhaps try to solve the problem under
10.1 and it will help to solve some problems on your project.


Article: 136823
Subject: Re: ISE doesn't work after a crash
From: Mike Treseler <mtreseler@gmail.com>
Date: Sun, 07 Dec 2008 12:09:47 -0800
Links: << >>  << T >>  << A >>
Nemesis wrote:

> Of course the process is synthesizable with ise8.2.

Except for the fact that the OS crashes.

>  I should investigate but I
> have little time, right now the better solution is to bring ise8.2 back to
> work.

It may take a little time.
I would make new projects for each submodule,
until I found the bad source.

Next time I would write my own code.

Good luck.

    -- Mike Treseler

Article: 136824
Subject: Re: Invalid devices when initialising scan chain with Nexys2
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Sun, 07 Dec 2008 21:52:08 +0100
Links: << >>  << T >>  << A >>
freespace@gmail.com wrote:
> there are _only_ 2 devices on the board connected to the JTAG chain.
> My problem is there appears to be 29 other devices which aren't there,
> but is detected.
Have you tried setting a slower cable speed? I've had things like this
happened when I used a too fast clock for JTAG. You can set the speed in
the iMPACT cable settings. The default is rather high, there have been
times when it wouldn't work unless I selected a slower speed.

HTH,
Sean



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