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On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote: > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote: > > > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote: > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com > > > > > wrote: > > > > > > >Does anyone know how I can generate a pulser of maximum repition rate > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate > > > > > >this signal before I use the actual pulser into the board > > > > > > I think you want a clock source. Here is one way you can generate it: > > > > > > `timescale 1ns/100fs > > > > > reg clk; > > > > > initial > > > > > begin > > > > > pck = 0; > > > > > forever clk = #10 ~clk; > > > > > end > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and > > > > > you can change the number 10 to your needs. > > > > > Please note that this is only for testbench usage and you can't > > > > > actually put this in your fpga. You have to use an oscillator on your > > > > > board to generate a similar clock to drive into your fpga. > > > > > > Muzaffer Kal > > > > > > DSPIA INC. > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > > > > Hi, > > > > > I was did make myself clear. I would like to have a variable pulesr, > > > > maximum 50 Mhz. > > > > > Thanks > > > > I think you made something very clear. > > > > Antti- Hide quoted text - > > > > - Show quoted text - > > > Okay, I made a grammatical blunder there! All jokes aside...I wanted > > to know if there is some code out there that would generate a variable > > pulse of max 50Mhz... > > > thanks again, > > You need to supply more info about your "variable pulse", such as > pulse width, duty cycle, and frequency. So for the high end (as > someone else suggested) it sounds like you want 50MHz with 50% duty > cycle (10ns HI / 10ns LO). > -Dave Pollum The specs are: minimum output pulse width: 10ns Pulse Pair Resolution: 20ns Maximum Repetition Rate (Periodic) 50MHzArticle: 138251
On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote: > On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > > > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote: > > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote: > > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com > > > > > > wrote: > > > > > > > >Does anyone know how I can generate a pulser of maximum repition rate > > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate > > > > > > >this signal before I use the actual pulser into the board > > > > > > > I think you want a clock source. Here is one way you can generate it: > > > > > > > `timescale 1ns/100fs > > > > > > reg clk; > > > > > > initial > > > > > > begin > > > > > > pck = 0; > > > > > > forever clk = #10 ~clk; > > > > > > end > > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and > > > > > > you can change the number 10 to your needs. > > > > > > Please note that this is only for testbench usage and you can't > > > > > > actually put this in your fpga. You have to use an oscillator on your > > > > > > board to generate a similar clock to drive into your fpga. > > > > > > > Muzaffer Kal > > > > > > > DSPIA INC. > > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > > > > > Hi, > > > > > > I was did make myself clear. I would like to have a variable pulesr, > > > > > maximum 50 Mhz. > > > > > > Thanks > > > > > I think you made something very clear. > > > > > Antti- Hide quoted text - > > > > > - Show quoted text - > > > > Okay, I made a grammatical blunder there! All jokes aside...I wanted > > > to know if there is some code out there that would generate a variable > > > pulse of max 50Mhz... > > > > thanks again, > > > You need to supply more info about your "variable pulse", such as > > pulse width, duty cycle, and frequency. So for the high end (as > > someone else suggested) it sounds like you want 50MHz with 50% duty > > cycle (10ns HI / 10ns LO). > > -Dave Pollum > > The specs are: > > minimum output pulse width: 10ns > Pulse Pair Resolution: 20ns > Maximum Repetition Rate (Periodic) 50MHz Basically, this isn't a constant clock signal .. the repetition varies over time. I am trying to mimic something like the following : http://www.aricorp.com/combo100.htm Thanks,Article: 138252
On Feb 10, 6:07=A0pm, uraniumore...@gmail.com wrote: > On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote: > > > > > On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote: > > > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote: > > > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.= com > > > > > > > wrote: > > > > > > > > >Does anyone know how I can generate a pulser of maximum repi= tion rate > > > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like t= o simulate > > > > > > > >this signal before I use the actual pulser into the board > > > > > > > > I think you want a clock source. Here is one way you can gene= rate it: > > > > > > > > `timescale 1ns/100fs > > > > > > > reg clk; > > > > > > > initial > > > > > > > begin > > > > > > > =A0 =A0 =A0 =A0 pck =3D 0; > > > > > > > =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk; > > > > > > > end > > > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns= low) and > > > > > > > you can change the number 10 to your needs. > > > > > > > Please note that this is only for testbench usage and you can= 't > > > > > > > actually put this in your fpga. You have to use an oscillator= on your > > > > > > > board to generate a similar clock to drive into your fpga. > > > > > > > > Muzaffer Kal > > > > > > > > DSPIA INC. > > > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > > > > > > Hi, > > > > > > > I was did make myself clear. I would like to have a variable pu= lesr, > > > > > > maximum 50 Mhz. > > > > > > > Thanks > > > > > > I think you made something very clear. > > > > > > Antti- Hide quoted text - > > > > > > - Show quoted text - > > > > > Okay, I made a grammatical blunder there! All jokes aside...I wante= d > > > > to know if there is some code out there that would generate a varia= ble > > > > pulse of max 50Mhz... > > > > > thanks again, > > > > You need to supply more info about your "variable pulse", such as > > > pulse width, duty cycle, and frequency. =A0 So for the high end (as > > > someone else suggested) it sounds like you want 50MHz with 50% duty > > > cycle (10ns HI / 10ns LO). > > > -Dave Pollum > > > The specs are: > > > minimum output pulse width: 10ns > > Pulse Pair Resolution: 20ns > > Maximum Repetition Rate (Periodic) 50MHz > > Basically, this isn't a constant clock signal .. the repetition varies > over time. I am trying to mimic something like the following :http://www.= aricorp.com/combo100.htm > > Thanks, I'm still confused. Are you trying to design hardware that mimics the pulse generator, i.e. you want code you will synthesize and program into the FPGA? Or do you mean you want a test bench that mimics the pulse generator to stimulate some other design during simulation? The two approaches would be very different. regards, GaborArticle: 138253
Under simulation mode,the two SATA GTPs(16bit) is connected with back- to-back .The ALIGN_COMMA_WORD parameter is set 2.From GTP A to GTP B is ok(4abc 7b4a---->4abc 7b4a). the data can be aligned at LSB. But From GTP B to GTP A is disalign.The comma is still aligned MSB(4abc 7b4a---->4a4a bc7b). . why? Ps,My same SATA GTP configure has been synthesized into FPGA. it can attahed HDD. why doesn't the simulation work?Article: 138254
Svenn Are Bjerkem wrote: > > Ext. clock => IBUFG => BUFG_1 => BUFG_2 => DCM_1/DCM_2/DCM3 > Hi Svenn, Route the IBUFG direct to your BUFGs instead of cascading the BUFGs. FWIW, if you can tell us more about what you're trying to achieve, we may be able to suggest alternative schemes. For example, why is the 7ns a problem? Perhaps tell us which FPGA family you're using; that may be relevant. Best, Syms.Article: 138255
On Feb 10, 3:13 pm, Gabor <ga...@alacron.com> wrote: > On Feb 10, 6:07 pm, uraniumore...@gmail.com wrote: > > > > > On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote: > > > > On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > > > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote: > > > > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote: > > > > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com > > > > > > > > wrote: > > > > > > > > > >Does anyone know how I can generate a pulser of maximum repition rate > > > > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate > > > > > > > > >this signal before I use the actual pulser into the board > > > > > > > > > I think you want a clock source. Here is one way you can generate it: > > > > > > > > > `timescale 1ns/100fs > > > > > > > > reg clk; > > > > > > > > initial > > > > > > > > begin > > > > > > > > pck = 0; > > > > > > > > forever clk = #10 ~clk; > > > > > > > > end > > > > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and > > > > > > > > you can change the number 10 to your needs. > > > > > > > > Please note that this is only for testbench usage and you can't > > > > > > > > actually put this in your fpga. You have to use an oscillator on your > > > > > > > > board to generate a similar clock to drive into your fpga. > > > > > > > > > Muzaffer Kal > > > > > > > > > DSPIA INC. > > > > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > > > > > > > Hi, > > > > > > > > I was did make myself clear. I would like to have a variable pulesr, > > > > > > > maximum 50 Mhz. > > > > > > > > Thanks > > > > > > > I think you made something very clear. > > > > > > > Antti- Hide quoted text - > > > > > > > - Show quoted text - > > > > > > Okay, I made a grammatical blunder there! All jokes aside...I wanted > > > > > to know if there is some code out there that would generate a variable > > > > > pulse of max 50Mhz... > > > > > > thanks again, > > > > > You need to supply more info about your "variable pulse", such as > > > > pulse width, duty cycle, and frequency. So for the high end (as > > > > someone else suggested) it sounds like you want 50MHz with 50% duty > > > > cycle (10ns HI / 10ns LO). > > > > -Dave Pollum > > > > The specs are: > > > > minimum output pulse width: 10ns > > > Pulse Pair Resolution: 20ns > > > Maximum Repetition Rate (Periodic) 50MHz > > > Basically, this isn't a constant clock signal .. the repetition varies > > over time. I am trying to mimic something like the following :http://www.aricorp.com/combo100.htm > > > Thanks, > > I'm still confused. Are you trying to design hardware that > mimics the pulse generator, i.e. you want code you will > synthesize and program into the FPGA? > > Or do you mean you want a test bench that mimics the > pulse generator to stimulate some other design during > simulation? > > The two approaches would be very different. > > regards, > Gabor If you can provide both that'll be good ..Article: 138256
Has anybody successfully used Xilinx FAT FS library for non system ace devices ? I would be interested hearing your stories. Alternatively, does anybody know of a stand alone FAT FS library ? Thanks, rudiArticle: 138257
On Feb 11, 9:17=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > Has anybody successfully used Xilinx FAT FS library for non > system ace devices ? I would be interested hearing your stories. > > Alternatively, does anybody know of a stand alone FAT FS library ? > > Thanks, > rudi DOSFS for EDK http://code.google.com/p/dev-kit/downloads/list AnttiArticle: 138258
On Feb 11, 2:01=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Svenn Are Bjerkem wrote: > > > Ext. clock =3D> IBUFG =3D> BUFG_1 =3D> BUFG_2 =3D> DCM_1/DCM_2/DCM3 > > Hi Svenn, > Route the IBUFG direct to your BUFGs instead of cascading the BUFGs. FWIW= , > if you can tell us more about what you're trying to achieve, we may be ab= le > to suggest alternative schemes. For example, why is the 7ns a problem? > Perhaps tell us which FPGA family you're using; that may be relevant. > Best, Syms. I am using Spartan-3A DSP 3400, sorry that I forgot to mention that, it was a bit late. What I am trying to acheive is to have a design that previously run on 50MHz external clock to use a 16MHz external clock and generate the internal frequencies with the DCMs. DCMs were present before the switch of external clock, but I didn't design that part of the system, and the system worked in the lab. Now I have 'the hat on' and have to care. Originally there were no BUFGs in the circuit. But suddenly ISE reported that the net between IBUFG and DCMs was routed on local net, I then inserted BUFG_2 by instantiation in the reset entity. Then ISE reported the net between IBUFG and BUFG_2 as local and I thought it had something to do with the shift register also being clocked directly from the IBUFG so I inserted BUFG_1 to isolate. Now I have learned that it may not be a good idea to put two BUFGs in a cascade, so I'll go back a few steps and inspect every change in FPGA editor. Manual place and route is not an option at this stage. The design change too much. If a preferred placement can be stored between P&R runs I'll try to do that. We still have a lot of ressources free, I use only 9 out of 24 BUFGMUXes and the rest is also below 50% utilization. The 7 ns delay is a problem only for those parts of the circuit that use reset. The reset release circuit get its clock after 0.03 ns, whereas the rest of the chip gets its clock after 0.03 + 7 ns. If this is the source of all the timing error reports. -- SvennArticle: 138259
On Tue, 10 Feb 2009 14:36:00 -0800 (PST), jleslie48 wrote: >> looking at the function contents, what is the purpose of this line: >> >> constant p: t_ubyte_array (0 to pgm'length-1) := pgm; >> >> in this context: >> >> -- Function to convert the generic value into ROM-contents format >> function contents(pgm: t_ubyte_array) return t_rom is >> constant p: t_ubyte_array (0 to pgm'length-1) := pgm; >> variable it: t_rom; >> begin >> it := (others => 0); >> for iloop in p'range loop >> it(iloop) := p(iloop); >> end loop; >> return it; >> end; >> >> It appears to me that constant 'p' is just a copy of pgm Yes, but with its subscript range normalized to (0 to N-1) regardless of what the incoming argument's subscript range might be. If you look at function tua() you'll find that it clones the input argument's range to its output. Given that the input is a string, its range is *probably* (1 to N), although even that is somewhat up for grabs. So the ROM-fill function normalizes the range so that the input argument is used exactly to fill the lowest few ROM locations. Normalization of unconstrained function inputs in this way is a standard VHDL trick, widely used by programmers like me who have learnt paranoia from a lifetime of failure :-) >> what is wrong with just: >> >> -- Function to convert the generic value into ROM-contents format >> function contents(pgm: t_ubyte_array) return t_rom is >> -- xxxxxxxxxx >> variable it: t_rom; >> begin >> it := (others => 0); >> for iloop in pgm'range loop >> it(iloop) := pgm(iloop); >> end loop; >> return it; >> end; If pgm() starts at 1, as it probably does, you'll get nothing planted in it(0). >> I tried it it synth's, implements and generates, but it doesn't run/ >> work, but why? Note that the ROM contents default to 0. So there's a HALT instruction in location 0 that is not overwritten by your program. It "works", but not in any way that you or I would find useful :-) >> this does work though: >> -- Function to convert the generic value into ROM-contents format >> function contents(pgm: t_ubyte_array) return t_rom is >> --constant p: t_ubyte_array (0 to pgm'length-1) := pgm; >> variable it: t_rom; >> begin >> it := (others => 0); >> for iloop in 0 to pgm'length-1 loop >> it(iloop) := pgm(iloop); >> end loop; >> return it; >> end; I suspect that's another example of XST being a little careless in its interpretation of the fine details of VHDL. If pgm(0) doesn't exist, as I suspect is the case, you should get an error from it. >another question, given 'the_program' >-- address....... 0 1 2 3 4 5 6 7 8 9 >-- data (char)... 'T' '2' 'M' 'h' 'e' 'l' 'l' 'o' NUL NUL >-- data (byte)... 84 50 77 104 101 109 109 111 0 0 > I'm not understanding the timing of events here: [snip] > after the gen_state finishes the delay_counter countdown, > its switches the gen_state to new_PC and the PC == 0. > on the next rising edge of the clock, the gen_state switches to > 'fetch' and the PC increments to '1' > on the next clock pulse, the gen_state is fetch and it tries > to set the operation to the rom_data, specifically, the_rom(1) > which is not an operation at all, but rather the data value of the > operation declared in the_rom(0). > Now I know I got something wrong, because this works, but my > 'stepping through' the code implies to me that the PC increment > that is part of the fetch will jump over the operation to the > operation's data. But the ROM read operation introduces a 1-clock pipeline delay, and the state machine is written to take account of that. If you add the ROM address and data to your waveform view you will probably see what's going on. I am not terribly proud of the way my ROM-reader state machine deals with this - the pipeline delay is handled in a rather non-uniform way across the various states - but as you say, it *does* work. It could be more cleanly coded, for sure. Left as an exercise for the student... Did you get my email of Feb.7th? I sent it to *both* the addresses you gave me. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138260
On Tue, 10 Feb 2009 11:44:43 -0800 (PST), jleslie48 wrote: >> It will still be a long way from Turing-completeness :-) >> and a very long way from doing any useful DSP :-( >but being able to scan a rom for specific signals, (label) >and caching them you don't consider a worthwhile process of a >DSP? OK, OK, I retract the cheap insult... the serious point behind it was that incremental refinement towards some ill-defined experimental goal may not be the best way to reach your more complicated but better-defined commercial goal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138261
Hi,
I am going to buy/build a Logic Analyzer, I need some help
to properly select some features.
My requirements:
- absolute minimum 16 channels
- state analysis 100 MHz minimum
- variable theresold (TTL/3.3V absolute minimum variable is
better)
- memory (don't know what to search for, 32Kbit/ch minimum?)
- UART, SPI. I2C AND 1-Wire
- export capabilities
- expandable (nice to have, custom plugins)
So far, there are these contenders:
- Intronix (http://www.pctestinstruments.com/)
389USD + 120USD customs + 30USD shipping = 539USD! =
423.794 EUR!
Probably the best, highly priced (hobbyst and customs!),
many channels, speediest and very few memory. No 1-Wire (It
may come in the future), no additional plugins, not
expandable
- ZeroPlus LA16064/LA160128
(http://www.zeroplus.com.tw/logic-analyzer_en/products.php?product_id=38)
(200EUR / 300EUR)
Best compromise, 16 channels(75MHz/100MHZ) or
100MHz/200MHz). This one has additional decode plugins, so I
could have:
- UART, I2C, SPI, 7 Segments (standard)
- additional 2 free plugins out of these:
http://www.zeroplus.com.tw/logic-analyzer_en/
I was planning to select 1-wire but cannot decide on the
other one I could get for free. What would you choose for
robotic usage?
I don't have any interest in audio, so maybe CANBUS could be
a good choice, I would get all just in case but they are
each in the 100-500 USD range.
What about simple Digital or Arithmetic Logic plugin?
- Sump FPGA Based Logic Analyzer
http://www.sump.org/projects/analyzer/
99USD for the Digilent board, probably about 150USD to
get the board here + the conditioning signal stuff needed
Very nice, many channels and fast, weak protection and
conditioning input needs work to be up to the task. It could
be expandable since the serial protocol is documented.
- OpenVeriFLA integrated logic Analyzer
0/99 USD for a FPGA development board (if not using the
same target), really difficult to me to understand, but it
could be worth the effort since it should be customizable
Any other low cost alternative to these ones?
TIA,
Giuseppe Marullo
Article: 138262Hi all, Please help me in this simple question: I've a ML505 board with a PS2 keyboard connected... I added the XPS PS2 INTERFACE and connected it to mb_plb I set the PS2_1_DATA port as external port and I modified the UCF file with: #### Keyboard Net Keyboard_pin LOC = T25; Net Keyboard_pin IOSTANDARD=LVCMOS18; My question is: what is the instruction I've to use in order to read the keyboard inputs? For XGPIO devices I used XGpio_mGetDataReg... but I did'n find the way to read ps2 port. I need to read these data in order to put them in a fsl bus coonected to a vhdl peripheral that will work as a home made scan code... Sorry for my bad english and for the noob question... DanieleArticle: 138263
On Tue, 10 Feb 2009 17:13:07 GMT, Nico Coesel wrote: >>...I wanted to deal with the case where M is >>a variable and in that case we end up with two >>adders which have to be cascaded somehow. > >You don't have to. Just say A=N-M and add A to the pulse accumulator. >A can be calculated in a seperate process. Indeed it can, but in what way is that different from "cascaded somehow"? As I and others have already pointed out, you can pipeline the N-M addition at zero cost in an FPGA; but you still need two adders. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138264
Svenn Are Bjerkem wrote: > On Feb 11, 2:01 am, "Symon" <symon_bre...@hotmail.com> wrote: >> Svenn Are Bjerkem wrote: >> >>> Ext. clock => IBUFG => BUFG_1 => BUFG_2 => DCM_1/DCM_2/DCM3 >> >> Hi Svenn, >> Route the IBUFG direct to your BUFGs instead of cascading the BUFGs. >> FWIW, if you can tell us more about what you're trying to achieve, >> we may be able to suggest alternative schemes. For example, why is >> the 7ns a problem? Perhaps tell us which FPGA family you're using; >> that may be relevant. Best, Syms. > > I am using Spartan-3A DSP 3400, sorry that I forgot to mention that, > it was a bit late. > > What I am trying to acheive is to have a design that previously run on > 50MHz external clock to use a 16MHz external clock and generate the > internal frequencies with the DCMs. DCMs were present before the > switch of external clock, but I didn't design that part of the system, > and the system worked in the lab. Now I have 'the hat on' and have to > care. > Read the DCM specification carefully. I think if your input frequency is less that 24MHz, or something like that, you need to use the CLKFX output to multiply frequencies up. OTOH, a quick look at the S3E datasheet I have handy says anything over 5MHz is OK, so you might be alright. > > Originally there were no BUFGs in the circuit. That would be bad. All clocks should come from a BUFG. Maybe you mean the BUFGs weren't instantiated, but were inferred? > But suddenly ISE > reported that the net between IBUFG and DCMs was routed on local net, > I then inserted BUFG_2 by instantiation in the reset entity. Then ISE > reported the net between IBUFG and BUFG_2 as local and I thought it > had something to do with the shift register also being clocked > directly from the IBUFG so I inserted BUFG_1 to isolate. ISE reports a lot of things! Some of them may be important, some not. If you need stuff coming out of the FPGA to be phase aligned with the clock going into the FPGA, then these direct clock connections to the DCMs/BUFGs are important. If you don't care about this, then you can ignore the warnings. > Now I have > learned that it may not be a good idea to put two BUFGs in a cascade, > so I'll go back a few steps and inspect every change in FPGA editor. > Try this:- Connect the clock input pin to a BUFG, call it BUFG_A. Connect the output of BUFG_A to the CLKIN of all the DCMs you require. Connect each of the DCMs to a BUFG, call them BUFG_B/C/D etc. Feedback the output of these BUFGs to the CLKFB of the respective DCM. This will keep the clocks phase aligned, as far as possible, to the input clock. > > Manual place and route is not an option at this stage. The design > change too much. If a preferred placement can be stored between P&R > runs I'll try to do that. We still have a lot of ressources free, I > use only 9 out of 24 BUFGMUXes and the rest is also below 50% > utilization. > Think carefully about your clock usage. If (say) CLK_A is simply twice the frequency of CLK_B, use CLK_A to clock all the FFs etc. in both CLK_A and CLK_B's domain. Simply enable the former CLK_B FFs every other CLK_A cycle. You save a clock domain and make it a trivial task to pass data between the domains. > > The 7 ns delay is a problem only for those parts of the circuit that > use reset. The reset release circuit get its clock after 0.03 ns, > whereas the rest of the chip gets its clock after 0.03 + 7 ns. If this > is the source of all the timing error reports. You should resynchronise the reset for each of your clock domains with a couple of FFs, I suggest. So, the signal reseting a FF being clocked by signal CLK_A, for example, should come from a FF clocked by CLK_A. Likewise for FFs clocked by CLK_B. For more detail on this stuff, I'd recommend reading UG331. It's all in there! Good luck, Syms.Article: 138265
> I've a ML505 board with a PS2 keyboard connected... > I added the XPS PS2 INTERFACE and connected it to mb_plb > I set the PS2_1_DATA port as external port Don't you need two pins for PS2? Data and clock? Cheers, JonArticle: 138266
On Feb 11, 2:32=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > On Feb 11, 9:17=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > > > Has anybody successfully used Xilinx FAT FS library for non > > system ace devices ? I would be interested hearing your stories. > > > Alternatively, does anybody know of a stand alone FAT FS library ? > > > Thanks, > > rudi > > DOSFS for EDK > > http://code.google.com/p/dev-kit/downloads/list > > Antti Thanks Antti ! rudiArticle: 138267
On 10 =D7=A4=D7=91=D7=A8=D7=95=D7=90=D7=A8, 22:55, naughty.z...@gmail.com w= rote: > I am working on a fairly large design, much larger than what I have > previously implemented in an FPGA. =C2=A0I am wondering what is the best > way to implement local reset circuits where they are needed. =C2=A0I've > noticed in a lot of older XAPPs that an FF tree was used to handle the > reset distribution. =C2=A0Also, what's the best way to go about making su= re > an enable signal does not have excessive fanout? =C2=A0In this case, it's > an init_done signal from a DDR2 memory interface going to the rest of > the design as an enable. =C2=A0Will the synthesis tools be smart enough t= o > replicate registers for the signal to reduce fanout and speed up the > design, or do I need to handle this myself in the VHDL? =C2=A0Thanks in > advance for your advice / comments. In my site I address reset issue. I recommend to synchronize the reset: "The reset signal is usually as loaded as your clock net. If you don't take care on your clock net, it will soon bite you as this net is clocking your design every cycle, when clock is enabled. =E2=80=9C http://bknpk.no-ip.biz/HWtips/asynchronousReset.htmlArticle: 138268
On Wed, 11 Feb 2009 10:45:30 +0100, "Giuseppe Marullo" <giuseppe.marullo@nospam.iname.com> wrote: >Hi, >I am going to buy/build a Logic Analyzer, I need some help >to properly select some features. > >My requirements: >- absolute minimum 16 channels >- state analysis 100 MHz minimum >- variable theresold (TTL/3.3V absolute minimum variable is >better) >- memory (don't know what to search for, 32Kbit/ch minimum?) >- UART, SPI. I2C AND 1-Wire >- export capabilities > >- expandable (nice to have, custom plugins) > >So far, there are these contenders: > >- Intronix (http://www.pctestinstruments.com/) > 389USD + 120USD customs + 30USD shipping = 539USD! = >423.794 EUR! > Probably the best, highly priced (hobbyst and customs!), >many channels, speediest and very few memory. No 1-Wire (It >may come in the future), no additional plugins, not >expandable They may have Euro-zone resellers. Guessing that based on their having German and French versions of the help files; a quick Google search turns up a Swiss site, at least. Try e-mailing the Intronix support line for info on who may be a reseller on that side of the pond. Note that the Intronix also includes a CAN interpreter. CANbus is pretty useful for control and monitoring apps. -- Rich Webb Norfolk, VAArticle: 138269
http://www.aipst.com/sata_device_model.tar.gz First read model_manual.pdf careful after download.Article: 138270
On 2=D4=C211=C8=D5, =CF=C2=CE=E710=CA=B154=B7=D6, "murl...@gmail.com" <murl= ...@gmail.com> wrote: > http://www.aipst.com/sata_device_model.tar.gz > > First read model_manual.pdf careful after download. sorry,http://www.aipst.com/sata_device_model.rarArticle: 138271
On Feb 11, 3:37 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > > Did you get my email of Feb.7th? I sent it to *both* the > addresses you gave me. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. No I did not receive any emails, and I went through my spam folder as well very strange can you send again please? jleslie48@yahoo.com jon@jonathanleslie.com jleslie@dhpconsultants.com should all work your normalizing the array index makes perfect sense. I've been c programming for so long I forgot that most languages allow the programmer to set the range as they like; its only C that always starts at 0. I had a feeling putting the program up on the testbench will answer my question. I'll give that a try. - JonArticle: 138272
I was not clear on what I want advice on. In the Virtex4, DCMs, according to the data sheet, need to be held in reset for 250ms. For this reset that is large, what is the best way to implement that - or is there a better way around this? I'm assuming a counter would not be a good method, as a counter for that would be large. In the other portions of the design, I was looking at using small counters to locally reset the logic in each area rather than using one giant global reset circuit. In the DDR2 controller, it needs to not do anything until init_done is asserted, which will then also enable another section of the design. That would be enabling a lot of logic, which I want to know if I need to perform any specific constructs in my code to reduce the fanout, or if the synthesis tools are actually smart enough to handle this.Article: 138273
On Feb 6, 10:43=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Marlboro wrote: > > I can't see those options in ISE 10.1i any more. > > > How can I do the map PAR in guide mode now? Anyone knows how to set > > this mode please ? > > Did you read the manual? The bit about guided mapping? > HTH., Syms. Oh yeah, thanks for suggestion, But they said the guide mode for individual process of mapping or PAR not available in 10.1 anymore, that's why you don't see it, instead they have a new one called 'smartguy' ;-)))Article: 138274
On Feb 11, 5:44=A0am, Jon Beniston <j...@beniston.com> wrote: > > I've a ML505 board with a PS2 keyboard connected... > > I added the XPS PS2 INTERFACE and connected it to mb_plb > > I set the PS2_1_DATA port as external port > > Don't you need two pins for PS2? Data and clock? > > Cheers, > Jon PS2 needs two pins, for data and clock. The falling clock edge indicates that the data line is valid. http://www.computer-engineering.org/ps2protocol/ is a good reference for the PS2 interface. Will
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