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On Nov 27, 6:24=A0pm, bish <bishes...@gmail.com> wrote: > On Nov 27, 10:08=A0pm, bish <bishes...@gmail.com> wrote: > > > > > > > On Nov 27, 6:14=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > > > > Not sure what the problem is with your code. =A0Here's an example wit= h > > > one timer. =A0It's 10.1, but there weren't any changes in the interru= pt > > > stuff between 9.2 and 10.1 (so I'm told). =A0This is based on a lab f= rom > > > one of Avnet's Speedway trainings. =A0I ran it on the Xilinx Spartan-= 3A > > > DSP 1800A Starter and verified that the interrupts are indeed > > > happening. =A0There is a bit file in the project directory if you don= 't > > > want to rebuild the project. > > > > Bryan > > > > The following file has been made available for you to download from > > > Avnet's File Transfer web site:http://xfer.avnet.com/uploads/Xil3S180= 0ADSP_Interrupt_v10.1.03.zip > > > I downloaded the timer_interrupt.bit file into FPGA using impact, the > > timer example worked FINE. > > It generated the required output and interrrupt was working. BUT > > > I could not use the system.xmp present inhttp://xfer.avnet.com/uploads/= Xil3S1800ADSP_Interrupt_v10.1.03.zip > > because > > I have edk 9.2i, but it was developed with later version of edk. > > > And here is the mysterious problem yet to be solved!! > > So I developed a base system and used xps interrupt controller and > > timer. The MHS file is: > > > # > > #######################################################################= ####=AD=AD### > > # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build > > EDK_Jm.16 > > # Sun Nov 16 21:24:15 2008 > > # Target Board: =A0Xilinx Spartan-3A DSP 1800A Starter Board Rev 1 > > # Family: =A0 =A0 =A0 =A0spartan3adsp > > # Device: =A0 =A0 =A0 =A0xc3sd1800a > > # Package: =A0 =A0 =A0 fg676 > > # Speed Grade: =A0 -4 > > # Processor: microblaze_0 > > # System clock frequency: 62.000000 MHz > > # On Chip Memory : =A0 8 KB > > # > > #######################################################################= ####=AD=AD### > > =A0PARAMETER VERSION =3D 2.1.0 > > > =A0PORT fpga_0_RS232_Uart_1_RX_pin =3D fpga_0_RS232_Uart_1_RX, DIR =3D = I > > =A0PORT fpga_0_RS232_Uart_1_TX_pin =3D fpga_0_RS232_Uart_1_TX, DIR =3D = O > > =A0PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ = =3D > > 125000000 > > =A0PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS= =3D RST > > =A0PORT dip_GPIO_in_pin =3D dip_GPIO_in, DIR =3D I, VEC =3D [0:7] > > =A0PORT push_GPIO_in_pin =3D push_GPIO_in, DIR =3D I, VEC =3D [0:3] > > =A0PORT led_GPIO_IO_pin =3D led_GPIO_IO, DIR =3D IO, VEC =3D [0:7] > > > BEGIN microblaze > > =A0PARAMETER HW_VER =3D 7.00.a > > =A0PARAMETER INSTANCE =3D microblaze_0 > > =A0PARAMETER C_INTERCONNECT =3D 1 > > =A0PARAMETER C_DEBUG_ENABLED =3D 1 > > =A0PARAMETER C_AREA_OPTIMIZED =3D 1 > > =A0BUS_INTERFACE DLMB =3D dlmb > > =A0BUS_INTERFACE ILMB =3D ilmb > > =A0BUS_INTERFACE DPLB =3D mb_plb > > =A0BUS_INTERFACE IPLB =3D mb_plb > > =A0BUS_INTERFACE DEBUG =3D microblaze_0_dbg > > =A0PORT RESET =3D mb_reset > > =A0PORT INTERRUPT =3D Interrupt > > END > > > BEGIN plb_v46 > > =A0PARAMETER INSTANCE =3D mb_plb > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PORT PLB_Clk =3D sys_clk_s > > =A0PORT SYS_Rst =3D sys_bus_reset > > END > > > BEGIN lmb_v10 > > =A0PARAMETER INSTANCE =3D ilmb > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PORT LMB_Clk =3D sys_clk_s > > =A0PORT SYS_Rst =3D sys_bus_reset > > END > > > BEGIN lmb_v10 > > =A0PARAMETER INSTANCE =3D dlmb > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PORT LMB_Clk =3D sys_clk_s > > =A0PORT SYS_Rst =3D sys_bus_reset > > END > > > BEGIN lmb_bram_if_cntlr > > =A0PARAMETER INSTANCE =3D dlmb_cntlr > > =A0PARAMETER HW_VER =3D 2.10.a > > =A0PARAMETER C_BASEADDR =3D 0x00000000 > > =A0PARAMETER C_HIGHADDR =3D 0x00003fff > > =A0BUS_INTERFACE SLMB =3D dlmb > > =A0BUS_INTERFACE BRAM_PORT =3D dlmb_port > > END > > > BEGIN lmb_bram_if_cntlr > > =A0PARAMETER INSTANCE =3D ilmb_cntlr > > =A0PARAMETER HW_VER =3D 2.10.a > > =A0PARAMETER C_BASEADDR =3D 0x00000000 > > =A0PARAMETER C_HIGHADDR =3D 0x00003fff > > =A0BUS_INTERFACE SLMB =3D ilmb > > =A0BUS_INTERFACE BRAM_PORT =3D ilmb_port > > END > > > BEGIN bram_block > > =A0PARAMETER INSTANCE =3D lmb_bram > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0BUS_INTERFACE PORTA =3D ilmb_port > > =A0BUS_INTERFACE PORTB =3D dlmb_port > > END > > > BEGIN xps_uartlite > > =A0PARAMETER INSTANCE =3D RS232_Uart_1 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_BAUDRATE =3D 115200 > > =A0PARAMETER C_ODD_PARITY =3D 0 > > =A0PARAMETER C_USE_PARITY =3D 0 > > =A0PARAMETER C_SPLB_CLK_FREQ_HZ =3D 62500000 > > =A0PARAMETER C_BASEADDR =3D 0x84000000 > > =A0PARAMETER C_HIGHADDR =3D 0x8400ffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT RX =3D fpga_0_RS232_Uart_1_RX > > =A0PORT TX =3D fpga_0_RS232_Uart_1_TX > > END > > > BEGIN clock_generator > > =A0PARAMETER INSTANCE =3D clock_generator_0 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_EXT_RESET_HIGH =3D 1 > > =A0PARAMETER C_CLKIN_FREQ =3D 125000000 > > =A0PARAMETER C_CLKOUT0_FREQ =3D 62500000 > > =A0PARAMETER C_CLKOUT0_PHASE =3D 0 > > =A0PARAMETER C_CLKOUT0_GROUP =3D NONE > > =A0PORT CLKOUT0 =3D sys_clk_s > > =A0PORT CLKIN =3D dcm_clk_s > > =A0PORT LOCKED =3D Dcm_all_locked > > =A0PORT RST =3D net_gnd > > END > > > BEGIN mdm > > =A0PARAMETER INSTANCE =3D debug_module > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_MB_DBG_PORTS =3D 1 > > =A0PARAMETER C_USE_UART =3D 1 > > =A0PARAMETER C_UART_WIDTH =3D 8 > > =A0PARAMETER C_BASEADDR =3D 0x84400000 > > =A0PARAMETER C_HIGHADDR =3D 0x8440ffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg > > =A0PORT Debug_SYS_Rst =3D Debug_SYS_Rst > > END > > > BEGIN proc_sys_reset > > =A0PARAMETER INSTANCE =3D proc_sys_reset_0 > > =A0PARAMETER HW_VER =3D 2.00.a > > =A0PARAMETER C_EXT_RESET_HIGH =3D 0 > > =A0PORT Slowest_sync_clk =3D sys_clk_s > > =A0PORT Dcm_locked =3D Dcm_all_locked > > =A0PORT Ext_Reset_In =3D sys_rst_s > > =A0PORT MB_Reset =3D mb_reset > > =A0PORT Bus_Struct_Reset =3D sys_bus_reset > > =A0PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst > > END > > > BEGIN xps_gpio > > =A0PARAMETER INSTANCE =3D push > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_GPIO_WIDTH =3D 4 > > =A0PARAMETER C_ALL_INPUTS =3D 1 > > =A0PARAMETER C_IS_BIDIR =3D 0 > > =A0PARAMETER C_BASEADDR =3D 0x8141c200 > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT GPIO_in =3D push_GPIO_in > > END > > > BEGIN xps_gpio > > =A0PARAMETER INSTANCE =3D dip > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_GPIO_WIDTH =3D 8 > > =A0PARAMETER C_ALL_INPUTS =3D 1 > > =A0PARAMETER C_IS_BIDIR =3D 0 > > =A0PARAMETER C_BASEADDR =3D 0x81420000 > > =A0PARAMETER C_HIGHADDR =3D 0x8142ffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT GPIO_in =3D dip_GPIO_in > > END > > > BEGIN xps_gpio > > =A0PARAMETER INSTANCE =3D led > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_GPIO_WIDTH =3D 8 > > =A0PARAMETER C_IS_BIDIR =3D 0 > > =A0PARAMETER C_BASEADDR =3D 0x81400000 > > =A0PARAMETER C_HIGHADDR =3D 0x8140ffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT GPIO_IO =3D led_GPIO_IO > > END > > > BEGIN xps_timer > > =A0PARAMETER INSTANCE =3D xps_timer_0 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_BASEADDR =3D 0x81418000 > > =A0PARAMETER C_HIGHADDR =3D 0x814181ff > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1 > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT Interrupt =3D xps_timer_0_Interrupt > > END > > > BEGIN xps_intc > > =A0PARAMETER INSTANCE =3D xps_intc_0 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_BASEADDR =3D 0x81414000 > > =A0PARAMETER C_HIGHADDR =3D 0x814141ff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT Irq =3D Interrupt > > =A0PORT Intr =3D xps_timer_0_Interrupt > > END > > > In xps_intc I have connected only timer interrupt to its Intr pin and > > other interrupts like > > from push buttons and other are NOT CONNECTED. > > In the configure ip.. option for xps interrupt controller I could not > change the no. of interrupt inputs (by default it is 2), as it is set > to 2 and disabled. > So I used two timers and connected interrupt pins of these timers to > interrupt controller just make intr inputs 2. Then again I checked > with the "timer.c" file from the link, and still the same result: > Timer example failed !!! > > This has already taken so many days and problem is becoming more > mysterious (but frustrating)!!! > > > > > Then I used "timer.c" provided in the link (I have not used external > > DDR2 SDRAM), and the result: > > > Starting Timer example > > Timer example FAILED > > > So, I am really confused here!! > > > > Click on the hyperlink or enter this URL into your web browser to > > > retrieve the file. > > > This file will remain on the server for approximately 5 days from the > > > date of the upload at which time it will be deleted. =A0Please be sur= e > > > to download it before the expiration time. > > > This file will expire on Dec =A01, 2008. > > > > File Size: 232357 Bytes > > > > On Nov 26, 12:22=A0am, bish <bishes...@gmail.com> wrote: > > > > > On Nov 26, 4:58=A0am, David <simianfe...@gmail.com> wrote: > > > > > > On Nov 26, 2:37=A0am, bish <bishes...@gmail.com> wrote: > > > > > > > On Nov 25, 12:25=A0pm, Matthias Alles <REMOVEallesCAPIT...@NOei= t.SPAMuni- > > > > > > > kl.de> wrote: > > > > > > > Hi! > > > > > > > > I wonder, whether "one_second_flag" is declared as volatile? = If not, the > > > > > > > compiler optimizes your if-statement in the while(1) loop awa= y. You can > > > > > > > check this by using mb-objdump. > > > > > > > I tried using the volatile for one_second_flag, still it does n= ot > > > > > > work. It just prints "the value of count =3D 1" once in termina= l and > > > > > > nothing happens then. > > > > > > > > Cheers, > > > > > > > Matthias > > > > > > > > bish schrieb: > > > > > > > > > I am trying to use a timer for regular interrupt in microbl= aze. I am > > > > > > > > using edk 9.2i and spartan 3a dsp 1800a. > > > > > > > > Even following a simple lab example widely used by beginner= s didn't > > > > > > > > work:http://users.utcluj.ro/~baruch/ssce/labor/EDK-L5-e.pdf > > > > > > > > > I have connected all the interrupt ports correctly as evide= nt from the > > > > > > > > following portion of the mhs file: > > > > > > > > BEGIN microblaze > > > > > > > > =A0PARAMETER HW_VER =3D 7.00.a > > > > > > > > ........... > > > > > > > > ........... > > > > > > > > PORT INTERRUPT =3D interrupt > > > > > > > > END > > > > > > > > > BEGIN xps_timer > > > > > > > > =A0PARAMETER INSTANCE =3D delay > > > > > > > > =A0PARAMETER HW_VER =3D 1.00.a > > > > > > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1 > > > > > > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200 > > > > > > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff > > > > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > > > > > > =A0PORT Interrupt =3D timer1 > > > > > > > > =A0PORT CaptureTrig0 =3D net_gnd > > > > > > > > END > > > > > > > > > BEGIN xps_intc > > > > > > > > =A0PARAMETER INSTANCE =3D xps_intc_0 > > ... > > read more =BB- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Hi, What compilator options do you use when compiling timer.c? Can you email me the .elf file? G=F6ranArticle: 136651
On Nov 28, 2:01=A0pm, Goran_Bilski <goran.bil...@xilinx.com> wrote: > On Nov 27, 6:24=A0pm, bish <bishes...@gmail.com> wrote: > > > On Nov 27, 10:08=A0pm, bish <bishes...@gmail.com> wrote: > > > > On Nov 27, 6:14=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > > > > > Not sure what the problem is with your code. =A0Here's an example w= ith > > > > one timer. =A0It's 10.1, but there weren't any changes in the inter= rupt > > > > stuff between 9.2 and 10.1 (so I'm told). =A0This is based on a lab= from > > > > one of Avnet's Speedway trainings. =A0I ran it on the Xilinx Sparta= n-3A > > > > DSP 1800A Starter and verified that the interrupts are indeed > > > > happening. =A0There is a bit file in the project directory if you d= on't > > > > want to rebuild the project. > > > > > Bryan > > > > > The following file has been made available for you to download from > > > > Avnet's File Transfer web site:http://xfer.avnet.com/uploads/Xil3S1= 800ADSP_Interrupt_v10.1.03.zip > > > > I downloaded the timer_interrupt.bit file into FPGA using impact, the > > > timer example worked FINE. > > > It generated the required output and interrrupt was working. BUT > > > > I could not use the system.xmp present inhttp://xfer.avnet.com/upload= s/Xil3S1800ADSP_Interrupt_v10.1.03.zip > > > because > > > I have edk 9.2i, but it was developed with later version of edk. > > > > And here is the mysterious problem yet to be solved!! > > > So I developed a base system and used xps interrupt controller and > > > timer. The MHS file is: > > > > # > > > #####################################################################= ######=AD=AD=AD### > > > # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build > > > EDK_Jm.16 > > > # Sun Nov 16 21:24:15 2008 > > > # Target Board: =A0Xilinx Spartan-3A DSP 1800A Starter Board Rev 1 > > > # Family: =A0 =A0 =A0 =A0spartan3adsp > > > # Device: =A0 =A0 =A0 =A0xc3sd1800a > > > # Package: =A0 =A0 =A0 fg676 > > > # Speed Grade: =A0 -4 > > > # Processor: microblaze_0 > > > # System clock frequency: 62.000000 MHz > > > # On Chip Memory : =A0 8 KB > > > # > > > #####################################################################= ######=AD=AD=AD### > > > =A0PARAMETER VERSION =3D 2.1.0 > > > > =A0PORT fpga_0_RS232_Uart_1_RX_pin =3D fpga_0_RS232_Uart_1_RX, DIR = =3D I > > > =A0PORT fpga_0_RS232_Uart_1_TX_pin =3D fpga_0_RS232_Uart_1_TX, DIR = =3D O > > > =A0PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ= =3D > > > 125000000 > > > =A0PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIG= IS =3D RST > > > =A0PORT dip_GPIO_in_pin =3D dip_GPIO_in, DIR =3D I, VEC =3D [0:7] > > > =A0PORT push_GPIO_in_pin =3D push_GPIO_in, DIR =3D I, VEC =3D [0:3] > > > =A0PORT led_GPIO_IO_pin =3D led_GPIO_IO, DIR =3D IO, VEC =3D [0:7] > > > > BEGIN microblaze > > > =A0PARAMETER HW_VER =3D 7.00.a > > > =A0PARAMETER INSTANCE =3D microblaze_0 > > > =A0PARAMETER C_INTERCONNECT =3D 1 > > > =A0PARAMETER C_DEBUG_ENABLED =3D 1 > > > =A0PARAMETER C_AREA_OPTIMIZED =3D 1 > > > =A0BUS_INTERFACE DLMB =3D dlmb > > > =A0BUS_INTERFACE ILMB =3D ilmb > > > =A0BUS_INTERFACE DPLB =3D mb_plb > > > =A0BUS_INTERFACE IPLB =3D mb_plb > > > =A0BUS_INTERFACE DEBUG =3D microblaze_0_dbg > > > =A0PORT RESET =3D mb_reset > > > =A0PORT INTERRUPT =3D Interrupt > > > END > > > > BEGIN plb_v46 > > > =A0PARAMETER INSTANCE =3D mb_plb > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PORT PLB_Clk =3D sys_clk_s > > > =A0PORT SYS_Rst =3D sys_bus_reset > > > END > > > > BEGIN lmb_v10 > > > =A0PARAMETER INSTANCE =3D ilmb > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PORT LMB_Clk =3D sys_clk_s > > > =A0PORT SYS_Rst =3D sys_bus_reset > > > END > > > > BEGIN lmb_v10 > > > =A0PARAMETER INSTANCE =3D dlmb > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PORT LMB_Clk =3D sys_clk_s > > > =A0PORT SYS_Rst =3D sys_bus_reset > > > END > > > > BEGIN lmb_bram_if_cntlr > > > =A0PARAMETER INSTANCE =3D dlmb_cntlr > > > =A0PARAMETER HW_VER =3D 2.10.a > > > =A0PARAMETER C_BASEADDR =3D 0x00000000 > > > =A0PARAMETER C_HIGHADDR =3D 0x00003fff > > > =A0BUS_INTERFACE SLMB =3D dlmb > > > =A0BUS_INTERFACE BRAM_PORT =3D dlmb_port > > > END > > > > BEGIN lmb_bram_if_cntlr > > > =A0PARAMETER INSTANCE =3D ilmb_cntlr > > > =A0PARAMETER HW_VER =3D 2.10.a > > > =A0PARAMETER C_BASEADDR =3D 0x00000000 > > > =A0PARAMETER C_HIGHADDR =3D 0x00003fff > > > =A0BUS_INTERFACE SLMB =3D ilmb > > > =A0BUS_INTERFACE BRAM_PORT =3D ilmb_port > > > END > > > > BEGIN bram_block > > > =A0PARAMETER INSTANCE =3D lmb_bram > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0BUS_INTERFACE PORTA =3D ilmb_port > > > =A0BUS_INTERFACE PORTB =3D dlmb_port > > > END > > > > BEGIN xps_uartlite > > > =A0PARAMETER INSTANCE =3D RS232_Uart_1 > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_BAUDRATE =3D 115200 > > > =A0PARAMETER C_ODD_PARITY =3D 0 > > > =A0PARAMETER C_USE_PARITY =3D 0 > > > =A0PARAMETER C_SPLB_CLK_FREQ_HZ =3D 62500000 > > > =A0PARAMETER C_BASEADDR =3D 0x84000000 > > > =A0PARAMETER C_HIGHADDR =3D 0x8400ffff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT RX =3D fpga_0_RS232_Uart_1_RX > > > =A0PORT TX =3D fpga_0_RS232_Uart_1_TX > > > END > > > > BEGIN clock_generator > > > =A0PARAMETER INSTANCE =3D clock_generator_0 > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_EXT_RESET_HIGH =3D 1 > > > =A0PARAMETER C_CLKIN_FREQ =3D 125000000 > > > =A0PARAMETER C_CLKOUT0_FREQ =3D 62500000 > > > =A0PARAMETER C_CLKOUT0_PHASE =3D 0 > > > =A0PARAMETER C_CLKOUT0_GROUP =3D NONE > > > =A0PORT CLKOUT0 =3D sys_clk_s > > > =A0PORT CLKIN =3D dcm_clk_s > > > =A0PORT LOCKED =3D Dcm_all_locked > > > =A0PORT RST =3D net_gnd > > > END > > > > BEGIN mdm > > > =A0PARAMETER INSTANCE =3D debug_module > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_MB_DBG_PORTS =3D 1 > > > =A0PARAMETER C_USE_UART =3D 1 > > > =A0PARAMETER C_UART_WIDTH =3D 8 > > > =A0PARAMETER C_BASEADDR =3D 0x84400000 > > > =A0PARAMETER C_HIGHADDR =3D 0x8440ffff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg > > > =A0PORT Debug_SYS_Rst =3D Debug_SYS_Rst > > > END > > > > BEGIN proc_sys_reset > > > =A0PARAMETER INSTANCE =3D proc_sys_reset_0 > > > =A0PARAMETER HW_VER =3D 2.00.a > > > =A0PARAMETER C_EXT_RESET_HIGH =3D 0 > > > =A0PORT Slowest_sync_clk =3D sys_clk_s > > > =A0PORT Dcm_locked =3D Dcm_all_locked > > > =A0PORT Ext_Reset_In =3D sys_rst_s > > > =A0PORT MB_Reset =3D mb_reset > > > =A0PORT Bus_Struct_Reset =3D sys_bus_reset > > > =A0PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst > > > END > > > > BEGIN xps_gpio > > > =A0PARAMETER INSTANCE =3D push > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_GPIO_WIDTH =3D 4 > > > =A0PARAMETER C_ALL_INPUTS =3D 1 > > > =A0PARAMETER C_IS_BIDIR =3D 0 > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200 > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT GPIO_in =3D push_GPIO_in > > > END > > > > BEGIN xps_gpio > > > =A0PARAMETER INSTANCE =3D dip > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_GPIO_WIDTH =3D 8 > > > =A0PARAMETER C_ALL_INPUTS =3D 1 > > > =A0PARAMETER C_IS_BIDIR =3D 0 > > > =A0PARAMETER C_BASEADDR =3D 0x81420000 > > > =A0PARAMETER C_HIGHADDR =3D 0x8142ffff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT GPIO_in =3D dip_GPIO_in > > > END > > > > BEGIN xps_gpio > > > =A0PARAMETER INSTANCE =3D led > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_GPIO_WIDTH =3D 8 > > > =A0PARAMETER C_IS_BIDIR =3D 0 > > > =A0PARAMETER C_BASEADDR =3D 0x81400000 > > > =A0PARAMETER C_HIGHADDR =3D 0x8140ffff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT GPIO_IO =3D led_GPIO_IO > > > END > > > > BEGIN xps_timer > > > =A0PARAMETER INSTANCE =3D xps_timer_0 > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_BASEADDR =3D 0x81418000 > > > =A0PARAMETER C_HIGHADDR =3D 0x814181ff > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1 > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT Interrupt =3D xps_timer_0_Interrupt > > > END > > > > BEGIN xps_intc > > > =A0PARAMETER INSTANCE =3D xps_intc_0 > > > =A0PARAMETER HW_VER =3D 1.00.a > > > =A0PARAMETER C_BASEADDR =3D 0x81414000 > > > =A0PARAMETER C_HIGHADDR =3D 0x814141ff > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > =A0PORT Irq =3D Interrupt > > > =A0PORT Intr =3D xps_timer_0_Interrupt > > > END > > > > In xps_intc I have connected only timer interrupt to its Intr pin and > > > other interrupts like > > > from push buttons and other are NOT CONNECTED. > > > In the configure ip.. option for xps interrupt controller I could not > > change the no. of interrupt inputs (by default it is 2), as it is set > > to 2 and disabled. > > So I used two timers and connected interrupt pins of these timers to > > interrupt controller just make intr inputs 2. Then again I checked > > with the "timer.c" file from the link, and still the same result: > > Timer example failed !!! > > > This has already taken so many days and problem is becoming more > > mysterious (but frustrating)!!! > > > > Then I used "timer.c" provided in the link (I have not used external > > > DDR2 SDRAM), and the result: > > > > Starting Timer example > > > Timer example FAILED > > > > So, I am really confused here!! > > > > > Click on the hyperlink or enter this URL into your web browser to > > > > retrieve the file. > > > > This file will remain on the server for approximately 5 days from t= he > > > > date of the upload at which time it will be deleted. =A0Please be s= ure > > > > to download it before the expiration time. > > > > This file will expire on Dec =A01, 2008. > > > > > File Size: 232357 Bytes > > > > > On Nov 26, 12:22=A0am, bish <bishes...@gmail.com> wrote: > > > > > > On Nov 26, 4:58=A0am, David <simianfe...@gmail.com> wrote: > > > > > > > On Nov 26, 2:37=A0am, bish <bishes...@gmail.com> wrote: > > > > > > > > On Nov 25, 12:25=A0pm, Matthias Alles <REMOVEallesCAPIT...@NO= eit.SPAMuni- > > > > > > > > kl.de> wrote: > > > > > > > > Hi! > > > > > > > > > I wonder, whether "one_second_flag" is declared as volatile= ? If not, the > > > > > > > > compiler optimizes your if-statement in the while(1) loop a= way. You can > > > > > > > > check this by using mb-objdump. > > > > > > > > I tried using the volatile for one_second_flag, still it does= not > > > > > > > work. It just prints "the value of count =3D 1" once in termi= nal and > > > > > > > nothing happens then. > > > > > > > > > Cheers, > > > > > > > > Matthias > > > > > > > > > bish schrieb: > > > > > > > > > > I am trying to use a timer for regular interrupt in micro= blaze. I am > > > > > > > > > using edk 9.2i and spartan 3a dsp 1800a. > > > > > > > > > Even following a simple lab example widely used by beginn= ers didn't > > > > > > > > > work:http://users.utcluj.ro/~baruch/ssce/labor/EDK-L5-e.p= df > > > > > > > > > > I have connected all the interrupt ports correctly as evi= dent from the > > > > > > > > > following portion of the mhs file: > > > > > > > > > BEGIN microblaze > > > > > > > > > =A0PARAMETER HW_VER =3D 7.00.a > > > > > > > > > ........... > > > > > > > > > ........... > > > > > > > > > PORT INTERRUPT =3D interrupt > > > > > > > > > END > > > > > > > > > > BEGIN xps_timer > > > > > > > > > =A0PARAMETER INSTANCE =3D delay > > > > > > > > > =A0PARAMETER HW_VER =3D 1.00.a > > > > > > > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1 > > > > > > > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200 > > > > > > > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff > > > > > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > > > > > > > =A0PORT Interrupt =3D timer1 > > > > > > > > > =A0PORT CaptureTrig0 =3D net_gnd > > > > > > > > > END > > > > > > > > > > BEGIN xps_intc > > > > > > > > > =A0PARAMETER INSTANCE =3D xps_intc_0 > > > ... > > > read more =BB- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > > - Show quoted text - > > Hi, > > What compilator options do you use when compiling timer.c? mb-gcc The compiler option for "debug and optimization" is: Debug level: Generate Debug symbols(-g) Optimization Level: No Optimization(-00) > Can you email me the .elf file? I have emailed you with the elf file. > > G=F6ranArticle: 136652
"Martin Sauer" <msau@displaign.de> wrote in message news:ggo2po.370.1@news.msc-ge.com... > Hi, > > I want to dither rgb-video signals with a Lattice ECP2 FPGA and I don't > have any idea how I should do this. Can you give me some tips for this > problem. It depends on how sophisticated you need to be. How many bits are you starting with, and how many will you end with. At its simplest, you can do a simple 1-d error feedback. That involves feeding your signal through an adder / register, and feeding the dropped bits back to the adder input. There are more sophisticated (and complicated) 2-d approaches, but try the 1-d first, and see how it works for you. PeteArticle: 136653
FPGA's tend to get called EPLD's by some people here at work - mainly those who are not hardware engineers and of the hardware engineers that do, it tends to be the ones that have been around for a long while. Is there technically a difference? I cant relly find much reference to EPLD anywhere, other than the fact it stands for electrically programmable logic device. Sounds kind of ok, but its not quite a field programmable gate array.Article: 136654
On Nov 27, 4:40=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > Hi Kolja, > > "Kolja Sulimma" <ksuli...@googlemail.com> wrote in message > > news:a48f4020-7f8a-4ce8-949a-e27397d7a370@q9g2000yqc.googlegroups.com... > > > > > Using the Virtex-5 PLL you should get less jitter. > > Maybe. Maybe not. I do not believe that "PLLs always reduce the jitter > inherent on a reference clock." even though Xilinx claim this rubbish in > their V5 user guide. (UG190 (v4.3) pg.91). Here's a counter-example.http:= //www.edn.com/contents/images/6475013.pdf > > Whatever, the OP's question is too vague to meaningfully answer. He fails= to > indicate what frequency of jitter he is interested in. Jitter is generall= y > defined from 10Hz upwards, but often 1UI of jitter at 10Hz is > inconsequential, but 1UI at 10MHz probably will be a bother. > > FWIW, common sources of noise which will produce jitter include power sup= ply > noise, SSOs, other clocks in the design. Trying to stop these coupling in= to > the outputs when they are all present on a single FPGA may be difficult. Thanks for all your answers! You are right I was not very clear. What I would like to do is to replace some ECL logic by a small FPGA or PLD. I do not need to be very fast, a 100MHz clock is enough. I am interested in the high frequency jitter and in the low frequency delay changes. I will only have as inputs an LVDS serial link to configure the functionallity, a clock input and a couple of LVDS outputs. Cheers PabloArticle: 136655
On Nov 28, 8:32=A0am, colin <colin_toog...@yahoo.com> wrote: > On 24 Nov, 16:34, palvarez <pabloalvarezsanc...@gmail.com> wrote: > > > > > > > Hi, > > > Have you had a look at the new FMC standard (VITA 57)? It looks > > extremely promising as nowadays many designs are based on a simple > > FPGA with variations on the front pannel. =A0Sofar I have only seen FMC > > developments for high perfomance plataforms based on Virtex5, but I > > feel that a great benefit would appear when using a flexible low > > budget carrier with flexible low cost front pannels. > > > Check this article for quick intro to VITA 57 > > >http://www.vmecritical.com/articles/id/?3575 > > > What do you think? > > > Cheers > > > pablo > > You can get the pinout from Xilinx, they use it on a dev board. > However, I've been trying to get the proper spec from VITA for ages > but it hasn't been formerly released yet. Presumably VMETRO & Xilinx > are VITA members and have a pre-release. > > Colin- Hide quoted text - > > - Show quoted text - Hi, In principle on can get the specs from http://www.vita.com/fmc.html. I have also tried to get it this week but there is an unusual delay.. Cheers pabloArticle: 136656
On Nov 27, 2:00=A0pm, iajzens...@gmail.com wrote: > I have submitted the following article from the New York Times to > stimulate interest and activity. > > November 25, 1999 > WHAT'S NEXT; When a Gizmo Can Invent a Gizmo > By ANNE EISENBERG > > IF Dr. Frankenstein's monster had published a best seller, who would > have gotten the rights to that intellectual property? > > His inventor up in the castle, of course. > > Tough luck for the monster, but these are still early days for > intellectual property rights for thinking machines. No one has > seriously proposed that a computer should receive a share of the > profits from an invention -- at least not yet. But other problems > related to the ownership of items invented by computers are already > being debated in preparation for the time, probably in about 10 years, > when such inventions will be commonplace, said David E. Goldberg, an > engineer and a professor at the University of Illinois at Urbana- > Champaign. > > Computers are already making inroads in the area of intellectual > property as they design antennas, gas turbines and integrated > circuits. Much of the work in this field of automatic discovery is > preliminary and a lot of it is proprietary and therefore secret, but > what can be seen provides tantalizing glimpses of a future in which > computers work day and night -- no breaks for lunch -- to come up with > original solutions with very little help from their programmers. > > http://query.nytimes.com/gst/fullpage.html?res=3D9D04EEDB1F3CF936A15752..= . Computers might be programmed to explore a range of parameters for a design, but that is NOT DESIGN. two key quotes: 1. <q> Dr. Koza and his colleagues have been creating electrical circuits using evolutionary computing. ''We recognize when these circuits infringe upon existing patented circuits because we know the existing circuits as textbook inventions,'' he said. ''But in our hundreds of runs, we've probably already invented many other circuits but haven't yet spotted them.'' </q> IOW the human seems to be making the final decision. 2. <q> Many inventions in the future will routinely be handled by computers. ''No one would think of building a skyscraper with thousands of workers,'' Dr. Goldberg said. ''Similarly, no one will think about solving a problem without getting the magnitude of intellectual leverage that is similar to the mechanical leverage of the steam engine.'' </q> No one says that because we use cranes to build a building that the cranes designed the building. The real problem is this is all about the legal issue. Companies already own the patents derived from their engineers' inventions. Now they want to extend that reach to anyone's work that uses their computers and software. It is only a question of how much greed the legal system will allow.Article: 136657
palvarez <pabloalvarezsanchez@gmail.com> wrote: > Hi, > In principle on can get the specs from > http://www.vita.com/fmc.html. I have also tried to get it this > week but there is an unusual delay. > Cheers > pablo pablo, I searched the site but couldn't find anywhere to download the specs. Do you have to join to get their open standard? Here's the membership page where they talk about "free standards": ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Regular Membership ($2,500 per year) includes free product directory listings on VITA websites, free listings in VITA's Member News page, full participation in the VITA Standards Organization, free standards and discounts on the VMEbus Handbook, participation on VITA's marketing committee, discounts for VITA sponsored conferences, discounts on ads on VITA's website, and access to VITA's members only webpages. Sponsor Membership ($25,000 per year) includes all the benefits of regular membership plus a seat on VITA's board of directors. To join VITA, simply download the VITA Membership Application form and email or send it to VITA with your payment. http://www.vita.com/join.html ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ If their free standard costs $2,500, I'll find another way to do the same thing. Regards, Mike MonettArticle: 136658
Tricky wrote: > FPGA's tend to get called EPLD's by some people here at work - mainly > those who are not hardware engineers and of the hardware engineers > that do, it tends to be the ones that have been around for a long > while. > > Is there technically a difference? I cant relly find much reference to > EPLD anywhere, other than the fact it stands for electrically > programmable logic device. Sounds kind of ok, but its not quite a > field programmable gate array. http://en.wikipedia.org/wiki/Erasable_programmable_logic_device "Erasable" programmable logic device This is a venerable term, and springs from the fact the very first PLDs were Fuse based, then EPROM based, and finally Erasable arrived. Once everyone was making Erasable PLDs, they morphed into SPLD/CPLD. -jgArticle: 136659
Ed Prochak wrote:
> Computers might be programmed to explore a range of parameters for a
> design, but that is NOT DESIGN.
>
> two key quotes:
>
> 1. <q> Dr. Koza and his colleagues have been creating electrical
> circuits using evolutionary computing. ''We recognize when these
> circuits infringe upon existing patented circuits because we know the
> existing circuits as textbook inventions,'' he said. ''But in our
> hundreds of runs, we've probably already invented many other circuits
> but haven't yet spotted them.'' </q>
>
> IOW the human seems to be making the final decision.
As long as humans are the consumers, it will stay like this. Machines
designing and building products for other machines to buy is sci-fi
territory: Stanislaw Lem or John Sladek. Sladek's _Mechasm_ is more openly
hilarious, but it has society saved from the runaway system. In Lem's
comedies, the system has become society.
Earlier this year Slashdot or some such mentioned a piece of research that
could have been Dr. Koza's. Somebody was using genetic methods to develop
an FPGA program for image recognition. The winner showed definite signs of
alien design:
- when the program was copied into another FPGA chip, it didn't work.
- on examination, the program included clusters of interconnected gates with
no obvious connection to the inputs or outputs. Reminiscent of junk DNA,
except that if they were changed, the program stopped working.
Changing the margins of gates by drawing current in nearby circuit
bits?? ??? Some newby designs brought to comp.arch.embedded show this kind
of unearthly brilliance. (Mind you, however bad this would be in a
product, it's very interesting as a research result.)
Maybe because I'm more firmly stuck in the software side than others in
c.a.e I'm more impressed by things like this. It seems that right now
we're seeing the results of society taken over by a runaway system for
producing esoteric financial instruments of no use to anyone but the system
itself. On the one hand, the BBB tranche of a CDO re-securitized and
re-sliced for sale as AAA, AA, A, BBB grade securities; on the other an
irreproducible FPGA program that works for no recognizable reason. Anybody
see a difference? I/O bandwidth, maybe.
Mel.
Article: 136660On Nov 28, 3:18=A0pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Tricky wrote: > > FPGA's tend to get called EPLD's by some people here at work - mainly > > those who are not hardware engineers and of the hardware engineers > > that do, it tends to be the ones that have been around for a long > > while. > > > Is there technically a difference? I cant relly find much reference to > > EPLD anywhere, other than the fact it stands for electrically > > programmable logic device. Sounds kind of ok, but its not quite a > > field programmable gate array. > > http://en.wikipedia.org/wiki/Erasable_programmable_logic_device > > "Erasable" programmable logic device > > This is a venerable term, and springs from the fact the very first > PLDs were Fuse based, then EPROM based, and finally Erasable arrived. > Once everyone was making Erasable PLDs, they morphed into SPLD/CPLD. > > -jg The old fogies at my place of work still refer to FPGA's and all other programmable logic as PAL's. Having worked with PAL's, GAL's, CPLD's and FPGA's, I prefer to use the proper term for each to be clear about the type of device I'm using. Of course there are vendors of programmable logic (like Lattice) that call some FPGA's "CPLD's" in an attempt to unseat CPLD's with their smaller non-volatile FPGA's. For me, the difference is in the architecture of the internals (LUT + FF vs. AND/OR macrocell) that determines which is a CPLD or FPGA, not size or volatility of configuration. "EPLD" is a term I must have missed along the way... Regards, GaborArticle: 136661
In message
<4b286d30-8e6a-405a-9599-8700670b1d29@j32g2000yqn.googlegroups.com>,
Gabor <gabor@alacron.com> wrote
>
>The old fogies at my place of work still refer to FPGA's and all other
>programmable logic as PAL's. Having worked with PAL's, GAL's, CPLD's
>and FPGA's, I prefer to use the proper term for each to be clear about
>the type of device I'm using. Of course there are vendors of
>programmable
>logic (like Lattice) that call some FPGA's "CPLD's" in an attempt to
>unseat CPLD's with their smaller non-volatile FPGA's. For me, the
>difference
>is in the architecture of the internals (LUT + FF vs. AND/OR
>macrocell)
>that determines which is a CPLD or FPGA, not size or volatility of
>configuration.
>
>"EPLD" is a term I must have missed along the way...
>
Were some of the 'names' trademarked so other vendors invented
alternative names?
--
Alan
news2006 {at} amac {dot} f2s {dot} com
Article: 136662Hi, thank you for your answer. I want to dither 10 bit to 8 bit rgb-video signals. martin Pete Fraser schrieb: > "Martin Sauer" <msau@displaign.de> wrote in message > news:ggo2po.370.1@news.msc-ge.com... >> Hi, >> >> I want to dither rgb-video signals with a Lattice ECP2 FPGA and I don't >> have any idea how I should do this. Can you give me some tips for this >> problem. > > It depends on how sophisticated you need to be. > How many bits are you starting with, and how many will you end with. > > At its simplest, you can do a simple 1-d error feedback. > That involves feeding your signal through an adder / register, and > feeding the dropped bits back to the adder input. > > There are more sophisticated (and complicated) 2-d approaches, > but try the 1-d first, and see how it works for you. > > Pete > >Article: 136663
Hello everyone, I am a newbie for fpga devices so I want to write driver for xilinx spartan iie xc2s50e chipset. How to start for this case ? Could you give me any suggest or idea for this. Regards.Article: 136664
"Martin Sauer" <msau@displaign.de> wrote in message news:ggr16s.1sk.1@news.msc-ge.com... > Hi, > > thank you for your answer. I want to dither 10 bit to 8 bit rgb-video > signals. So try the 1-d approach and see how you like it. Treat the components independent of each other. Take each component, and feed it into input A of a 10-bit adder, followed by a 10-bit register. The eight msbs of the register are your output. The two lsbs of the register get fed back to the two lsbs of adder input B. You need to fill in the input B msbs with zeros, or sign extend, depending on whether you regard your RGB as signed or unsigned. You can get a lot more sophisticated with 2-d error feedback, but the 1-d approach should be fine for most applications. Check out: Using the 8 bit CCIR Recommendation 601 digital interface Croll, M.G.; Devereux, V.G.; Weston, M. Broadcasting Convention, 1988. IBC 1988., International Volume , Issue , 23-27 Sep 1988 Page(s):268 - 271 PeteArticle: 136665
berte wrote:
> I am a newbie for fpga devices so I want to write driver for xilinx
> spartan iie xc2s50e chipset.
This is not possible because the xc2s50e is a blank slate.
There are no registers for an OS to talk to until
somebody defines the operation and writes, tests and
compiles some hdl code to implement it.
> How to start for this case ?
Think about what this driver would do
if it were already working.
-- Mike Treseler
Article: 136666I am fairly new to working with FPGAs, have created only a few projects, and want to know how to determine whether or not your design is any good. Simulation works, on-board program works. Besides normal functionality, what should I be focusing on when designing FPGAs? ----------------------------------------------------------------------- 1. Come up with project idea 2. Work out general functionality 3. Draw Block Diagram 4. Rework general functionality 5. Write out Flow Charts for each module 6. Start coding 7. Simulate 8. Program target device 9. Test/Error checkingArticle: 136667
Hello, I am in the process of porting a project of mine from the Cyclone Nios Development Kit to the Terasic DE1 board. The main reason for this is to be able to run on less expensive hardware and thus make the project available to more people (hence "get a better board" is not really an easy answer.) My interest is mostly in computing projects, so my views are certainly biased in that direction. Unfortunately, I have run into a few issues with the DE1 board. I thought I'd post them here (and please let me know if there is a better place to send this) in the hope that a future board (Cyclone III-based, maybe?) might address these. Please don't get me wrong - this is a great board at a great price; I think, however, that a few things would make it even better. 1. The SD card slot only connects a handful of signals. In particular, it does not connect the two switch pins on the socket (card detect and write protect.) This makes it much harder than it needs to be to handle card removal and insertion. 2. Similarly, the serial port doesn't connect more than the transmit and receive signals, even though there is a 2/2 transceiver on the board. Having at least DTR/DCD or RTS/CTS would have been a plus; a "real" serial port with 3/5 signals would of course be even better. 3. While I'm dreaming, I would *love* to see a USB-A or -AB connector and/or an Ethernet PHY (not a fullblown Ethernet controller) connected to the FPGA. That would make the DE1 a dream board in my book. -hpaArticle: 136668
cid <nihonshuu@gmail.com> wrote in news:294e2bd5-5d90-46e9-b2d7- 4edba5e27be9@w1g2000prm.googlegroups.com: > I am fairly new to working with FPGAs, have created only a few > projects, and want to know how to determine whether or not your design > is any good. > > Simulation works, on-board program works. > > Besides normal functionality, what should I be focusing on when > designing FPGAs? > > ----------------------------------------------------------------------- > 1. Come up with project idea > 2. Work out general functionality > 3. Draw Block Diagram > 4. Rework general functionality > 5. Write out Flow Charts for each module > 6. Start coding > 7. Simulate > 8. Program target device > 9. Test/Error checking > At around step 3 (Draw Block Diagram) you should identify clock domain crossings (and asynchronous signals), and how they will be treated. Doing this early during your design process tends to produce a design with a small number of clock domain crossings, in well defined places. This can save you much grief later on. At some point (possibly 3 or 5) you should have identified functional blocks (VHDL: entities, Verilog: modules). If you break down the design right, each of these blocks will have a relatively independent function. This means they can be tested independently. Testing at this level is a lot faster and easier than testing the design for the entire chip. My experience is that most development takes place using these independent module test benches. The "top level" test bench tend to be used more once the design is integrated (which usually happens in the latter part of the schedule). Cheers, AllanArticle: 136669
Hi, Is it possible to build a unit on fpga where alerting pre-recorded messages: sms, voice messages can be sent using possibly the ambiant wireless network? if yes, how? i am not looking for the hardware architecture, i can work this on my own. i am rather looking for the means to achieve this: what kind of theory in the context of communication and broadcating in general i should read about to achieve this goal and how to be able to use the ambiant wireless ( landline?) network to send these messages. any papers/books titles will be greatly appreciated CheersArticle: 136670
On 30 Nov, 15:05, Karl <karl.polyt...@googlemail.com> wrote: > Hi, > Is it possible to build a unit on fpga where alerting pre-recorded > messages: sms, voice messages can be sent =A0using possibly the ambiant > wireless network? if yes, how? i am not looking for the hardware > architecture, i can work this on my own. i am rather looking for the > means to achieve this: what kind of theory =A0in the context of > communication and broadcating in general i should read about to > achieve this goal and how to be able to use the ambiant wireless > ( landline?) network to send these messages. any papers/books titles > will be greatly appreciated > > Cheers Why do you need an FPGA for this? LeonArticle: 136671
"Karl" <karl.polytech@googlemail.com> wrote in message news:f8493c3f-0629-472a-8ff4-1e7551887a7b@f20g2000yqg.googlegroups.com... > Hi, > Is it possible to build a unit on fpga where alerting pre-recorded > messages: sms, voice messages can be sent using possibly the ambiant > wireless network? if yes, how? i am not looking for the hardware > architecture, i can work this on my own. i am rather looking for the > means to achieve this: what kind of theory in the context of > communication and broadcating in general i should read about to > achieve this goal and how to be able to use the ambiant wireless > ( landline?) network to send these messages. any papers/books titles > will be greatly appreciated Do you mean "will someone supply me with the design for a GSM modem in a form that I can load into an FPGA". Noting that if they did, this item would allow the purchasor to reverse engineer the design into an ASIC, I very much doubt it. timArticle: 136672
On Nov 30, 6:23=A0am, Allan Herriman <allanherri...@hotmail.com> wrote: > cid <nihons...@gmail.com> wrote in news:294e2bd5-5d90-46e9-b2d7- > 4edba5e27...@w1g2000prm.googlegroups.com: > > > > > I am fairly new to working with FPGAs, have created only a few > > projects, and want to know how to determine whether or not your design > > is any good. > > > Simulation works, on-board program works. > > > Besides normal functionality, what should I be focusing on when > > designing FPGAs? > > > ----------------------------------------------------------------------- > > 1. Come up with project idea > > 2. Work out general functionality > > 3. Draw Block Diagram > > 4. Rework general functionality > > 5. Write out Flow Charts for each module > > 6. Start coding > > 7. Simulate > > 8. Program target device > > 9. Test/Error checking > > At around step 3 (Draw Block Diagram) you should identify clock domain > crossings (and asynchronous signals), and how they will be treated. =A0 > Doing this early during your design process tends to produce a design > with a small number of clock domain crossings, in well defined places. = =A0 > This can save you much grief later on. > > At some point (possibly 3 or 5) you should have identified functional > blocks (VHDL: entities, Verilog: modules). =A0If you break down the desig= n > right, each of these blocks will have a relatively independent function. = =A0 > This means they can be tested independently. =A0Testing at this level is = a > lot faster and easier than testing the design for the entire chip. =A0My > experience is that most development takes place using these independent > module test benches. =A0The "top level" test bench tend to be used more > once the design is integrated (which usually happens in the latter part > of the schedule). > > Cheers, > Allan 1. Come up with project idea 2. Work out general functionality 3. Draw Block Diagram (identify clock domain crossings) 4. Rework general functionality (identify entities/modules) 5. Write out Flow Charts for each module 6. Start coding individual modules 7. Simulate individual modules 8. Code "top-level" module 9. Simulate "top-level" module 10. Program target device 11. Test/Error checking (on-board)Article: 136673
Hi, I am student using spartan 3a dsp 1800 board with EDK/ise 9.2i . In EDK I had used BSB to create new project using default configuration for the following peripherals:- 1) microblaze (with bram 64KB) ,clock 2)RST32_UART 3)LED ,PUSH, DIP. 4)DDR2 SDRAM using MPMC peripheral I had used all default settings to the end of bsb. When i downloaded bitseam in the board , i got MEMORY TEST FAILURE (for 32 ,16 and 8 bit) message in hyperterminal . But other peripherals are working fine. I can't understand what the problem is. Does any body has solution?Article: 136674
Hello, I am a newbie and I would like some guidance. I am using Actel AGL060. What is the typical jitter for logic done in the AGL060? What design issues influence that jitter? What design rules to follow to minimize jitter? What jitter can be expected in a 74AC counter for example? How can we generate predictable jitter levels of 1, 5, 10, 15 and 20 psec in the AGL060, assuming those are all possible? How can I use a AGL060 to improve our jitter measurement level. How do we use an external delay to improve jitter measurement? Your comments are appreciated.
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