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Nemesis <gnemesis2001@gmail.com> writes: > On Apr 16, 12:48 pm, Nemesis <gnemesis2...@gmail.com> wrote: > >> > How long is your reset pulse? There's a min pulse width requirement >> > on Step 1 devices, and as I recall, it's a few clock cycles, whereas >> > (again IIRC) on V-II is was only 2 ns. >> >> It is about 4 us. But right now I read on the V4 user guide that 200ms >> is required!! >> I implemented a pulse stretcher ...and I'm waiting the generating >> process. > > I just tested the new bitfile with the 200ms DCM reset ... it seems to > work fine. > We'll see :-) Excellent - and I see I'll have to go and peruse the datasheet further! 200ms is alot longer than I recall! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 131251
I need help. I get this error when I rout my design for my spartan 3:
WARNING:Route:438 - The router has detected an unroutable situation due to
local congestion. The router will finish the
rest of the design and leave one or more connections as unrouted. The
cause of this behavior might be putting too
much logic into a single CLB. To allow you to use FPGA editor to isolate
the problems, the following is a list of (up
to 10) such congested connections:
What can I do?
I use about 81% of the slice capacity.
Device utilization summary:
---------------------------
Selected Device : 3s200vq100-5
Number of Slices: 1570 out of 1920 81%
Number of Slice Flip Flops: 1662 out of 3840 43%
Number of 4 input LUTs: 2420 out of 3840 63%
Number used as logic: 2412
Number used as Shift registers: 8
Number of IOs: 27
Number of bonded IOBs: 27 out of 63 42%
Number of BRAMs: 4 out of 12 33%
Number of MULT18X18s: 9 out of 12 75%
Number of GCLKs: 5 out of 8 62%
Number of DCMs: 2 out of 4 50%
Article: 131252>There has to be a way to do this, right? If this is VHDL, then there isn't. Well-known limitation of the language. Most simulators have a work-around. For ModelSim this is 'SignalSpy'.Article: 131253
Mark wrote: > I need help. Don't we all... > I get this error when I rout my design for my spartan 3: > > WARNING:Route:438 - The router has detected an unroutable situation > due to local congestion. The router will finish the > rest of the design and leave one or more connections as unrouted. > The cause of this behavior might be putting too > much logic into a single CLB. To allow you to use FPGA editor to > isolate the problems, the following is a list of (up > to 10) such congested connections: > > What can I do? > Hi Mark, I suggest you use FPGA editor to isolate the problems. If only you had a list of congested connections! Other alternatives including searching the internet for something like "The router has detected an unroutable situation". There's this newfangled thing called 'Google' (perhaps you've heard of it?) that you might use. HTH., Syms. p.s. Post a few of the listed congested connections so we can actually help you. Your FPGA is nowhere near being full. My guess is maybe you've used too many clocks in an IOB tile, but who can tell unless you post the information?Article: 131254
"Mark" <Mark@mark.mark> wrote in message news:480718d2$0$90272$14726298@news.sunsite.dk... >I need help. I get this error when I rout my design for my spartan 3: > > WARNING:Route:438 - The router has detected an unroutable situation due to > local congestion. The router will finish the > rest of the design and leave one or more connections as unrouted. The > cause of this behavior might be putting too > much logic into a single CLB. To allow you to use FPGA editor to isolate > the problems, the following is a list of (up > to 10) such congested connections: > > What can I do? I hit something similar some time ago when I was using incremental synthesis in Precision (feed through ISE via smartguide). The design was around 80% full but failed to route. When I turned off incremental synthesis it routed it OK. If you are not using incremental synthesis/P&R then try changing your synthesis/P&R settings. Hans www.ht-lab.com > > I use about 81% of the slice capacity. > > Device utilization summary: > --------------------------- > > Selected Device : 3s200vq100-5 > > Number of Slices: 1570 out of 1920 81% > Number of Slice Flip Flops: 1662 out of 3840 43% > Number of 4 input LUTs: 2420 out of 3840 63% > Number used as logic: 2412 > Number used as Shift registers: 8 > Number of IOs: 27 > Number of bonded IOBs: 27 out of 63 42% > Number of BRAMs: 4 out of 12 33% > Number of MULT18X18s: 9 out of 12 75% > Number of GCLKs: 5 out of 8 62% > Number of DCMs: 2 out of 4 50% > >Article: 131255
I have never used the FPGA editor before, but im going to read about it now. :-) "Symon" <symon_brewer@hotmail.com> wrote in message news:fu78hi$hi4$1@aioe.org... > HTH., Syms. What is HTH., Syms?Article: 131256
"Dan K" <danielgkNOSPAM@visi.com> wrote in message
news:MyvNj.109$ui2.25@fe184.usenetserver.com...
> There has to be a way to do this, right?
...
>
> or:
>
> if(UUT/instance_1/txcomstart /= '0') then
> error <= x"0103";
> end if;
>
>
> I've tried just about everything I can think of and nothing seems to work.
>
As mentioned by Robert if you use Modelsim then look up SignalSpy which is
very powerful and dead easy to use. If you use Riviera then you might be
able to use VHDL2007/8. I am not 100% sure if the VHDL2007/8 syntax below
is correct but it might look something like this:
txcomstart <= <<signal .UUT.instance_1.txcomstart : std_logic_vector >>;
if(txcomstart /= '0') then
error <= x"0103";
end if;
Any Riviera user would like to comment on this?
Hans
www.ht-lab.com
Article: 131257Thank you, i will try that. "HT-Lab" <hans64@ht-lab.com> wrote in message news:D7GNj.46980$4f4.21941@newsfe6-win.ntli.net... > > "Mark" <Mark@mark.mark> wrote in message > news:480718d2$0$90272$14726298@news.sunsite.dk... >>I need help. I get this error when I rout my design for my spartan 3: >> >> WARNING:Route:438 - The router has detected an unroutable situation due >> to local congestion. The router will finish the >> rest of the design and leave one or more connections as unrouted. The >> cause of this behavior might be putting too >> much logic into a single CLB. To allow you to use FPGA editor to >> isolate the problems, the following is a list of (up >> to 10) such congested connections: >> >> What can I do? > > I hit something similar some time ago when I was using incremental > synthesis in Precision (feed through ISE via smartguide). The design was > around 80% full but failed to route. When I turned off incremental > synthesis it routed it OK. If you are not using incremental synthesis/P&R > then try changing your synthesis/P&R settings. > > Hans > www.ht-lab.com > > >> >> I use about 81% of the slice capacity. >> >> Device utilization summary: >> --------------------------- >> >> Selected Device : 3s200vq100-5 >> >> Number of Slices: 1570 out of 1920 81% >> Number of Slice Flip Flops: 1662 out of 3840 43% >> Number of 4 input LUTs: 2420 out of 3840 63% >> Number used as logic: 2412 >> Number used as Shift registers: 8 >> Number of IOs: 27 >> Number of bonded IOBs: 27 out of 63 42% >> Number of BRAMs: 4 out of 12 33% >> Number of MULT18X18s: 9 out of 12 75% >> Number of GCLKs: 5 out of 8 62% >> Number of DCMs: 2 out of 4 50% >> >> > >Article: 131258
And where can I find this setting? "HT-Lab" <hans64@ht-lab.com> wrote in message news:D7GNj.46980$4f4.21941@newsfe6-win.ntli.net... > I hit something similar some time ago when I was using incremental > synthesis in Precision (feed through ISE via smartguide). The design was > around 80% full but failed to route. When I turned off incremental > synthesis it routed it OK. If you are not using incremental synthesis/P&R > then try changing your synthesis/P&R settings.Article: 131259
On Thu, 17 Apr 2008 11:26:19 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >Mark wrote: >> I need help. > >Don't we all... > >> I get this error when I rout my design for my spartan 3: >> >> WARNING:Route:438 - The router has detected an unroutable situation >> due to local congestion. >> What can I do? >> >Hi Mark, >I suggest you use FPGA editor to isolate the problems. If only you had a >list of congested connections! >Other alternatives including searching the internet for something like "The >router has detected an unroutable situation". There's this newfangled thing >called 'Google' (perhaps you've heard of it?) that you might use. >HTH., Syms. >p.s. Post a few of the listed congested connections so we can actually help >you. Your FPGA is nowhere near being full. My guess is maybe you've used too >many clocks in an IOB tile, but who can tell unless you post the >information? What Symon said. Plus, peruse the synthesis report (.syr) for WARNINGs that might give you a clue; e.g. related somehow to the signals or components listed.. With 5 GCLKs it is possible that you are using all 5 GCLKS in one half of the FPGA (there is a limit of 4 in each corner) but I would expect different errors there. One other possible conflict : if you are using BRAMs as 32 or 36 wide, the Spartan-3 needs to share connections with the multipliers (this is avoided if you use twice the number of BRAMs but only 16 or 18 bits from each). Since you are using 4 BRAMs + 9 Mults this is a possible candidate, but unlikely. Two other things to try: (1) target a larger FPGA to see if the problem is inherent in the design, or somehow related to capacity (2) run MAP and PAR with a different "cost table entry" (set the -t flag to 2 or 3..99) in case placement has just randomly painted itself into a corner. - BrianArticle: 131260
On Apr 16, 7:01=A0pm, "Dan K" <danielgkNOS...@visi.com> wrote: > There has to be a way to do this, right? > > If I want to test a signal in the UUT, I just have to do this in my > testbench: > > =A0 =A0if(txcomstart /=3D '0') =A0then > =A0 =A0 =A0 =A0 =A0error <=3D x"0103"; > =A0 =A0end if; > > But what if the UUT contains an instance, instance_1 (instance.vhd) and th= e > signal I want to test is in there? > I can bring it out of instance_1 and into the UUT and test it, but isn't > there an easier way? > As others have mentioned, SignalSpy may give you what you want to do, but I'd also suggest that if you get in the habit of designing components and testbenches to test those components that you won't need to have a testbench dig down into the hierarchy in the first place. 1. Create a testbench for 'instance.vhd' and validate that 'instance.vhd' is working as expected. 2. Now that 'instance.vhd' is a tested known good widget, it can be included in 'UUT' and a testbench created for UUT. The things that the UUT testbench tests are the outputs of UUT, there is no need for testing signals internal to UUT or anything that it may happen to instantiate. If you think creating testbenches for each individual entity/ architecture is more trouble than it's worth (and in some cases it might be) then you're implicitly saying you're willing to debug those things working at a higher level in the design hierarchy. Even in that situation though, every single one of those embedded widgets all the way up and down the design hierarchy will all still have some effect that can be tested for all the way back up to the top level and therefore by a system level testbench. One could conclude from that observation that there is only a need for a system level testbench and that would technically be correct, but in all but the simplest designs would be a serious problem since it is not likely that a system level testbench model would adequately cover and test all of the possible usage scenarios (i.e. how it works in the real world). If you really want to see if some signal in some widget buried down in the hierarchy is working as intended but don't want to create a testbench to verify proper operation, then simply add the signal to the wave window and view that it is working as intended. Kevin JenningsArticle: 131261
On Apr 1, 10:24=A0pm, Dave Pollum <vze24...@verizon.net> wrote: > On Mar 31, 4:04 pm, Sunn <sun...@gmail.com> wrote: > > Does webpack 10.1 require modelsim for simulation? ps help me!! If need th= en what is an appropirate modelsim for vista? > > > > > Hi, please forgive me for any ignorance in this question, but I am > > really lost. > > > I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But > > it just doesn't seem to work. > > > Now I am not very familiar with these programs, I am using them > > because I am doing a school course that uses FPGA and they use Xilinx > > and Modelsim... I have used them in the labs, but here I am just > > having trouble to install them. > > > I am able to installed Xilinx ISE Webpack 9.2i, but I cannot find > > Modelsim in it, so I googled for Modelsim, installed it, but it > > doesn't do anything. > > > I just don't know what's going on or where should I look at... I just > > want to install the programs!! > > > Does anyone have any guides on how to get it install and running on > > Linux? (Kernel 2.6) > > > Thanks. > > I know that Xilinx works with universities to supply boards, chips, > and software at very low costs to students (speak up Austen). =A0Perhaps > Modeltech (Modelsim) has a similar program. =A0Have you talked to your > prof about this? =A0And even for us non-students, there is a free, but > limited, version of Modelsim that is available from the Xilinx > website. > HTH > -Dave Pollum- Hide quoted text - > > - Show quoted text -Article: 131262
On Apr 16, 6:01 pm, "Dan K" <danielgkNOS...@visi.com> wrote: > There has to be a way to do this, right? > > If I want to test a signal in the UUT, I just have to do this in my > testbench: > > if(txcomstart /= '0') then > error <= x"0103"; > end if; > > But what if the UUT contains an instance, instance_1 (instance.vhd) and the > signal I want to test is in there? > I can bring it out of instance_1 and into the UUT and test it, but isn't > there an easier way? > > like maybe: > > if(/instance_1/txcomstart /= '0') then > error <= x"0103"; > end if; > > or maybe its this???: > if(\instance_1\txcomstart /= '0') then > error <= x"0103"; > end if; > > or: > > if(UUT/instance_1/txcomstart /= '0') then > error <= x"0103"; > end if; > > I've tried just about everything I can think of and nothing seems to work. > > Thanks > > Dan If you are testing the internal signal completely within the context of the internal entity/architecture in which it appears, then you can create either a procedure or a function called by an assertion statement within that architecture, to monitor that signal. The procedure could update a scoreboard, etc. to manage error status and reporting, or just handle reporting locally. It can be turned on and off based on a generic, or simply escaped with synthesis_on/off comments if you always want it simulated. Assertion statements are generally ignored by synthesis only, so any function they called would be ignored automatically. One of the advantages of this method is that it is automatically available to be used with any testbench that includes the entity/architecture. Design it, test it, integrate it; the test goes with the functionality wherever it is used. Of course this requires modifying the source code to insert your checking code. If you have separate personnel/organizations for design and verification, then the functions/procedures need to be stubbed out in a package and inserted into the design by the designer, then that package can be maintained by the verification folks. If this signal is a port on a buried instance somewhere, and you used components and configurations to build up the hierarchy, you could use a configuration to replace the architecture of interest with a different "wrapper" architecture that re-instances the entity/ architecture and includes instrumentation code around it. This is one of the few situations where I would consider the overhead and pain of components and configurations to be worthwhile. AndyArticle: 131263
Hi, I=B4ve problems with my custom IP core with simple DMA capability (Master on PLB). The DMA transfer from the core=B4s BRAM (32bit wide) to Memory does not work properly. Every second word is missing. With direct BRAM access it works well. Does anybody have any ideas? Thx in advance.Article: 131264
Hi, does anyone know how to use a 2nd FSL peripheral attached to microblaze? This is what I did. I have attached 2 peripherals, let's say we call it peripheral1 and peripheral2 to the microblaze's FSL bus. now here comes the problem. Using the commands putfsl(val,0) and getfsl(val,1), I am able to write and read from peripheral 1 respectively. However, when I do putfsl(val,2) and getfsl(val,3), nothing happens from peripheral2; I thought i was supposed to write and read from peripheral 2 respectively by these commands. I have been struggling with this for a while...any of your inputs would really be great. :D --- excerpt from system.mhs file BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 PARAMETER C_FSL_LINKS = 2 PARAMETER C_USE_FPU = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb BUS_INTERFACE SFSL0 = peripheral1_to_microblaze_0 ## IS THE ID 1? BUS_INTERFACE MFSL0 = microblaze_0_to_peripheral1 ## IS THE ID 0? BUS_INTERFACE SFSL1 = peripheral2_0_to_microblaze_0 ## IS THE ID 3? BUS_INTERFACE MFSL1 = microblaze_0_to_peripheral2 ## IS THE ID 2? PORT CLK = sys_clk_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END otherwise, how to determine the corresponding ID of the FSL peripherals? I have looked through fsl_v20.pdf but dun see anything useful. thanks a million! ChrisArticle: 131265
Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? The brute force method is fairly maddening. I'd be curious to hear if anybody has any 'tricks of the trade' here. Also, just out of curiosity, how many of you do your own PCB layout, versus farming it out? It would certainly save us a lot of money to buy the tools and do it ourselves, but it seems like laying out a board out well requires quite a bit of experience, especially a 6-8 layer board with high pin count FPGA's. We're just setting up a hardware shop here, and although I've been doing FPGA and board schematics design for a while, it's always been at a larger company with resources to farm the layout out, and we never did anything high-speed to really worry about the board layout too much. Thanks in advance for your opinions. DaveArticle: 131266
On Apr 17, 8:21 pm, waing gyi <waing....@gmail.com> wrote: > On Apr 1, 10:24 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > On Mar 31, 4:04 pm, Sunn <sun...@gmail.com> wrote: > > > Does webpack 10.1 require modelsim for simulation? ps help me!! If need then what is an appropirate modelsim for vista? > > > > Hi, please forgive me for any ignorance in this question, but I am > > > really lost. > > > > I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But > > > it just doesn't seem to work. > > > > Now I am not very familiar with these programs, I am using them > > > because I am doing a school course that uses FPGA and they use Xilinx > > > and Modelsim... I have used them in the labs, but here I am just > > > having trouble to install them. > > > > I am able to installed Xilinx ISE Webpack 9.2i, but I cannot find > > > Modelsim in it, so I googled for Modelsim, installed it, but it > > > doesn't do anything. > > > > I just don't know what's going on or where should I look at... I just > > > want to install the programs!! > > > > Does anyone have any guides on how to get it install and running on > > > Linux? (Kernel 2.6) > > > > Thanks. > > > I know that Xilinx works with universities to supply boards, chips, > > and software at very low costs to students (speak up Austen). Perhaps > > Modeltech (Modelsim) has a similar program. Have you talked to your > > prof about this? And even for us non-students, there is a free, but > > limited, version of Modelsim that is available from the Xilinx > > website. > > HTH > > -Dave Pollum- Hide quoted text - > > > - Show quoted text - ------------------------------------------------------ You can download ModelSim XE from Xilinx website and request the license key after installing the software. If you do not want to pay for the license fee, then install free version (Starter Edition). Another way to get ModelSim is to download from Mentor Graphics website (http://www.model.com/resources/student_edition/ student_download.asp). They provide free ModelSim PE Student Edition for academic use. You also need to request the license key. For simulation within ISE WebPACK environment, you need to set the simulator preference. From ISE menu, click Edit --> Preferences, ISE General -> Integrated Tools. Then set the ModelSim simulator path to ModelSim executable binary, i.e,. C:\Modeltech_xe_starter\win32xoem \modelsim.exe. Hope it is helpful. chumnarnArticle: 131267
Hey everybody, Just started using Xilinx XST as my synthesis tool and I'm just looking for the command line instruction (or GUI) to set the design frequency, I was using precision where it was "setup_design - frequency=66". Anyone know the equivalent command for XST? My eyes cant seem to find it in the documentation! :-( Cheers, Rob.Article: 131268
Dave wrote:
> Does anybody out there have a good methodology for determining your
> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean?
> The brute force method is fairly maddening. I'd be curious to hear if
> anybody has any 'tricks of the trade' here.
The best way to get good pinouts is to finish a working
prototype of the hdl code before making the board.
I let place and route make the first cut unconstrained
and then clean up from there.
> Also, just out of curiosity, how many of you do your own PCB layout,
Not me.
Whoever does this,
should do it all day long, every day.
> It would certainly save us a lot of money to
> buy the tools and do it ourselves,
The first pass might save some money,
but by the time you have a working board
you will be in the hole.
> but it seems like laying out a
> board out well requires quite a bit of experience, especially a 6-8
> layer board with high pin count FPGA's.
That is correct.
-- Mike Treseler
Article: 131269On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> wrote: >Does anybody out there have a good methodology for determining your >optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >The brute force method is fairly maddening. I'd be curious to hear if >anybody has any 'tricks of the trade' here. > >Also, just out of curiosity, how many of you do your own PCB layout, >versus farming it out? It would certainly save us a lot of money to >buy the tools and do it ourselves, but it seems like laying out a >board out well requires quite a bit of experience, especially a 6-8 >layer board with high pin count FPGA's. > >We're just setting up a hardware shop here, and although I've been >doing FPGA and board schematics design for a while, it's always been >at a larger company with resources to farm the layout out, and we >never did anything high-speed to really worry about the board layout >too much. Thanks in advance for your opinions. > >Dave Sure wish there was a slick way of doing FPGA pinouts. I usually use graph paper and figure out the FPGA pinout to other parts to minimize routing snarls. I do pcb layouts on my own and other folks designs. Our boards have high-speed routing, switching power supplies, and high-gain analog stuff; sometimes all on the same board. Unless the service bureau has someone who understands how to lay out such circuitry and place sensitive analog stuff near digital junk, it is more trouble to farm out than do it yourself if you want the board to work on the first cut. Doing your own layout will take a lot of learning to master the PCB layout program and what your board vendor can handle. It will take 5 to 10 complicated boards to become mildly proficient at layout. I don't know about saving cost. Your time may be better spent doing other activities rather than learning about layout and doing the layouts. The upside to doing your own layout - you control the whole design from start to finish. If you have a challenging layout, you'll have a much higher probability of having a working board on the first try which has hidden savings (getting to market earlier <- less troubleshooting + less respins). --- MarkArticle: 131270
robquigley@gmail.com wrote:
> Just started using Xilinx XST as my synthesis tool and I'm just
> looking for the command line instruction (or GUI) to set the design
> frequency, I was using precision where it was "setup_design -
> frequency=66".
To learn the tool, just give ISE
a known good synchronous hdl design file.
It will tell you what Fmax is,
and draw you an rtl schematic.
Then read the docs and the command files it made.
-- Mike Treseler
Article: 131271On Apr 16, 1:34 am, Michael <nleah...@gmail.com> wrote: > On Apr 15, 2:10 pm, Kevin Neilson > > > > <kevin_neil...@removethiscomcast.net> wrote: > > > Also - is there a Xilinx simulator that is built into ISE? I am > > > following a Xilinx tutorial (http://www.xilinx.com/support/techsup/ > > > tutorials/tutorials9.htm) and it first says "Whether you use > > > the ModelSim simulator or the ISE Simulator with this tutorial, you > > > will achieve the same results." suggesting there is a fully functional > > > tutorial built into ISE, and then two paragraphs down it says "In > > > order to use this tutorial, you must install ModelSim on your > > > computer.". So that just confused me. > > > > Thanks! > > > > -Michael > > > The most recent version of ISIM (the ISE simulator) is much faster and > > has a new parser so it supports the language(s) much better. The user > > interface is a bit coarser and the waveform viewer is not as nice as > > Modelsim's, but it might work well for you. I didn't consider this > > because it's not really free, since ISE isn't free, but if you already > > have ISE it might be a good option. -Kevin > > I'm confused - I just downloaded the "ISE WebPACK 9.2i" a couple days > ago and didn't pay a thing. (and it never asked me to pay a thing). > Does this have a built in simulator, or is it only the version that > you pay for that has a built in simulator? Thanks, > > -Michael ----------------------------------------------------- ISE WebPACK 9.2i does not include the HDL simulator. Therefore, you need to install it (ModelSIM XE) separately. There is a WebPack10.1 now, but I haven't check it if it also include the simulator. chumnarnArticle: 131272
qrk wrote: > On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> > wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. >> >> Also, just out of curiosity, how many of you do your own PCB layout, >> versus farming it out? It would certainly save us a lot of money to >> buy the tools and do it ourselves, but it seems like laying out a >> board out well requires quite a bit of experience, especially a 6-8 >> layer board with high pin count FPGA's. >> >> We're just setting up a hardware shop here, and although I've been >> doing FPGA and board schematics design for a while, it's always been >> at a larger company with resources to farm the layout out, and we >> never did anything high-speed to really worry about the board layout >> too much. Thanks in advance for your opinions. >> >> Dave > > Sure wish there was a slick way of doing FPGA pinouts. I usually use > graph paper and figure out the FPGA pinout to other parts to minimize > routing snarls. > > I do pcb layouts on my own and other folks designs. Our boards have > high-speed routing, switching power supplies, and high-gain analog > stuff; sometimes all on the same board. Unless the service bureau has > someone who understands how to lay out such circuitry and place > sensitive analog stuff near digital junk, it is more trouble to farm > out than do it yourself if you want the board to work on the first > cut. > Or find a good layouter and develop a long-term business relationship. My layouter knows just from looking at a schematic which areas are critical. He's a lot older than I am and that is probably one of the reasons why his stuff works without much assistance from me. Nothing can replace a few decades of experience. > Doing your own layout will take a lot of learning to master the PCB > layout program and what your board vendor can handle. It will take 5 > to 10 complicated boards to become mildly proficient at layout. I > don't know about saving cost. Your time may be better spent doing > other activities rather than learning about layout and doing the > layouts. ... Yep, that's why I usually do not do my own layouts. Occassionally I route a small portion of a circuit and send that to my layouter. No DRC or anything, just to show him how I'd like it done. > ... The upside to doing your own layout - you control the whole > design from start to finish. If you have a challenging layout, you'll > have a much higher probability of having a working board on the first > try which has hidden savings (getting to market earlier <- less > troubleshooting + less respins). > > --- > Mark -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131273
Dave wrote: > Does anybody out there have a good methodology for determining your > optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > The brute force method is fairly maddening. I'd be curious to hear if > anybody has any 'tricks of the trade' here. > > Also, just out of curiosity, how many of you do your own PCB layout, > versus farming it out? It would certainly save us a lot of money to > buy the tools and do it ourselves, but it seems like laying out a > board out well requires quite a bit of experience, especially a 6-8 > layer board with high pin count FPGA's. > > We're just setting up a hardware shop here, and although I've been > doing FPGA and board schematics design for a while, it's always been > at a larger company with resources to farm the layout out, and we > never did anything high-speed to really worry about the board layout > too much. Thanks in advance for your opinions. > > Dave Hi Dave, I layout my own PCBs. Unlike Mike T., I don't let the FPGA tools pick the pinout. That said, it is important to consider carefully consider nets which might have tight timing, e.g. clocks. I reason that there is a lot more flexibility in the FPGA routing than on my PCB, and it's cheaper, so I can save most time and money by being flexible in the pinout. I set the banks the nets are to go on, and firm up the detailed pinout by swapping pins on the FPGAs banks during the PCB layout process. You need some experience in what your HDL code is gonna look like to be able to do this, but there you go. If you are adept at FPGA work, you'll find learning a PCB layout tool is a piece of cake. I also use laser drilled microvias from layer 1 to 2, which make the layout of big BGAs easier and saves layers. SI is easier also. The price is usually less this way; the layers outweigh the via expense. You don't need buried vias, IME. Some of my FPGA buddies and I have had bad experiences with contract PCB people. Sometimes they are knowledgeable and talented, but sometimes they are dogmatic idiots, and sometimes they are useless. If you go the contract route, it's important to closely monitor what they get up to so you find out early doors which type they are. Like you and Mike say, it depends a lot on your experience. If you've worked closely with your layout guys in the past, that'll be a big help to you. For sure, there's more than one way to skin a cat, but I enjoy PCB layout. YMMV, good luck with it. Cheers, Syms. p.s. One benefit to laying out the PCB yourself is that it can help you spot stupid mistakes in the circuit as you go. It forces you to look very closely at the layout.Article: 131274
Joerg wrote: > > > Yep, that's why I usually do not do my own layouts. Occassionally I > route a small portion of a circuit and send that to my layouter. No > DRC or anything, just to show him how I'd like it done. > Hi Joerg, That's a excellent middle way. Cheers, Syms.
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