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hi dave, i have measured power consumption in a large number of fpga's, mostly actels. for most models, with no dc loads and static conditions and inputs at cmos levels, the current is less than 1 mA. for many models, the current is less than 200 uA. the original 2.0 um a1020's were about 3.2 mA or so. the amount of current is very repeatable and the level is a function of the model device and feature size it was built at. generally, the current comes from the internal charge pump which provides bias. note, however, there is a intial current transient which exceeds this amount significantly. i don't know the altera 7k family but 70 mA (350 mW) is a lot. i have tested some quicklogic pasic1 devices and their current was in the 3-5 mA range, a bit long ago for me to remember exactly. note that the quicklogic devices use the amorphous silicon antifuses which tend to have higher leakage currents than the ono actel antifuse, particularly at higher temps, i beleive. also, i have tested some chip express qyh580 laser programmable gate arrays (lpga). this ~70,000 gate model had a utilization of approximately 50%. the static device current was essentially 0. i have some altera 5192's on some boards. i don't have exact current measurements on those devices but it was noted to be, er, kind of warm to the finger. generally, for measuring current, i look at static current, current in the clock distribution system, and current consumed by gates. anyways, i would disagree with your statement one about "high power consumption of fpga" and think it most probably strongly depends on the fpga design. hope this helps, rk ______________________________________ David Bokaie <dbokaie@ix.netcom.com> wrote in article <33F1DA46.2AF4@ix.netcom.com>... > In our latest design we have notice that our Altera 7K FPGA is drawing > roughly 100ma of current. Stopping the clock to the chip only reduced > the power consumption by 30%. I was wondering if there is any study out > there that > > 1) explains the high power consumption of FPGA > 2) compare power consumption between different FPGA vendors > and different technology family. > > Please send/or copy your responses to davidb@proxim.com > > Thanks, > > David >Article: 7201
In article <33F1DA46.2AF4@ix.netcom.com>, David says... > >In our latest design we have notice that our Altera 7K FPGA is drawing >roughly 100ma of current. Stopping the clock to the chip only reduced >the power consumption by 30%. I was wondering if there is any study out >there that > > 1) explains the high power consumption of FPGA > 2) compare power consumption between different FPGA vendors > and different technology family. > >Please send/or copy your responses to davidb@proxim.com > >Thanks, > >David I agree with Richard, this definitely is a lot. The only case in which I have seen *significant* amount of static current consumption is in the case of a FPGA using NMOS transistors as routing switches, but even in that case the static current keeps around 5 or 10 mA for 30000 gates equivalent device. It looks like that should be a design problem ;( Take care, Julio -- ============================================================== Julio Faura e-mail: faura@sidsa.es tel: 34 1 803 50 52 fax: 34 1 803 95 57 http://www.sidsa.es SIDSA Parque Tecnologico de Madrid c/Isaac Newton 28760 TRES CANTOS (MADRID) SPAIN ==============================================================Article: 7202
Alex Lait wrote: > In article <33f242de.660155416@news.m.iinet.net.au>, > daveb@iinet.net.au > says... > > rstevew@armory.com (Richard Steven Walz) wrote: > > > > [snip] > > :Last I looked, Altera had bought Intel's FlexPLD's and called them > FlashLOGIC > > :or such and they are FPGA's that are SRAM and EEFLash programmable > with a > > :LPT-JTAG cable I have the plans for that uses just one '244. I > don't do PLD > > :that big, so I haven't bothered, but that sounds like what you just > asked > > :for. Yes? No? All you need to do is hunt down the command to dump > the SRAM > > :to EEFlash, (they want to sell you software to do that one tiny > bit, but it > > :is a well known code), and you got it!! I THINK I still have that > info! > > :Write or call them! www.altera.com . > > :-Steve > > > > ISP has to be the way to go for this kind of thing. However Altera > do > > not (afaik) offer free design software. A colleague is using Altera > > extensively, and confirms the "Bit Blaster" (ISP adapter) is just a > > '244 sold at a high price. > > > > This seems to be the problem, everyone charges mega-$ either to > > design, or to program the brutes. > > > > I am using the Lattice 1016 devices (2K gates claimed). I got the > design > software free from Lattice. I don't think you can download it but you > > can request a free cdrom with it. It supports all Lattice devices > from > GAL to ispLSI1016. The software to develop the larger devices (up to > 8K > gates) is just $500 US. The software is based on the Data IO Synario > package and supports schematic as well as text design entry and > functional simulation. The only portion of the package I find lacking > is > the timing analyses. There is a module to do some static timing but > that > seems to be it. > > These devices are ISP and the programer is extremely simple. > Schematics > are available in most of the Lattice data sheets for the ISP devices. > It > is just a 74HC367 attached to a parallel port. > > The thing I like it that the part (ispLSI1016 90MHz) are around $15 > CAN. > each in quantities of 10. > > I am not associated with Lattice or anyone else :) > > Alex Lait APS now sells the Lattice software metioned above for $370.00. It is not officially listed yet. We will be packaging it with the Accolade VHDL Synthesis tool, but it can also be gotten stand alone. Just drop me a line if you need these tools. We are trying to put together complete Synthesis and Router solutions for XILINX, LUCENT, VANTIS, ACTEL, QUICKLOGIC, ALTERA and LATTICE. The Accolade VHDL tool handles syntheis for these, and we currently have the routing options available for XILINX/LATTICE/VANTIS. We are working on the others, and they should be available soon. You can check out all our kits at: http://www.associatedpro.com/aps -- ---------------------------------------------------------------- Richard Schwarz, President Associated Professional Systems (APS) EDA and Communications Tools http://www.associatedpro.com richard@associatedpro.com 410.569.5897 fx:410.661.2760Article: 7203
David R Brooks wrote: > Sam Falaki <Falaki@uqtr.uquebec.ca> wrote: > > :> >> Has somebody tested the free actel software? Is it worth to > download? > :> >> Is programmer support included? Is the ACTIVATOR needed or is > there > :> >> a free design for a simple programming hardware. > : > :I managed to compile VHDL and target a very wide range of devices > :without even going through any tutorial or reading any "help" > :whatsoever. It's really easy to use. You can kind of guess your > :way along and next thing you know you're done. I liked it. > > The software may be free (and good), but what else do you need to get > > working silicon? A big-bucks programmer, maybe? The bottom line is the > > cost of _all_ tools necessary. > > Please, will one of the SRAM-based FPGA vendors put out something > similar? So we (the great impoverished <g>) can actually put their > chips to work in real systems. > > -- Dave Brooks <http://www.iinet.net.au/~daveb> > PGP public key: finger daveb@opera.iinet.net.au > servers daveb@iinet.net.au > fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34 > What's all this? see http://www.iinet.net.au/~daveb/crypto.html Dave, Have you checked out our kits at http://www.associatedpro.com/aps Our XILINX kits are inexpensive and we have been able to set up plans for the *impoverished* at times which could perhaps meet your needs. (we all are, or were there once). -- ---------------------------------------------------------------- Richard Schwarz, President Associated Professional Systems (APS) EDA and Communications Tools http://www.associatedpro.com richard@associatedpro.com 410.569.5897 fx:410.661.2760Article: 7204
In article <33f242de.660155416@news.m.iinet.net.au>, daveb@iinet.net.au says... > rstevew@armory.com (Richard Steven Walz) wrote: > > [snip] > :Last I looked, Altera had bought Intel's FlexPLD's and called them FlashLOGIC > :or such and they are FPGA's that are SRAM and EEFLash programmable with a > :LPT-JTAG cable I have the plans for that uses just one '244. I don't do PLD > :that big, so I haven't bothered, but that sounds like what you just asked > :for. Yes? No? All you need to do is hunt down the command to dump the SRAM > :to EEFlash, (they want to sell you software to do that one tiny bit, but it > :is a well known code), and you got it!! I THINK I still have that info! > :Write or call them! www.altera.com . > :-Steve > > ISP has to be the way to go for this kind of thing. However Altera do > not (afaik) offer free design software. A colleague is using Altera > extensively, and confirms the "Bit Blaster" (ISP adapter) is just a > '244 sold at a high price. > > This seems to be the problem, everyone charges mega-$ either to > design, or to program the brutes. > I am using the Lattice 1016 devices (2K gates claimed). I got the design software free from Lattice. I don't think you can download it but you can request a free cdrom with it. It supports all Lattice devices from GAL to ispLSI1016. The software to develop the larger devices (up to 8K gates) is just $500 US. The software is based on the Data IO Synario package and supports schematic as well as text design entry and functional simulation. The only portion of the package I find lacking is the timing analyses. There is a module to do some static timing but that seems to be it. These devices are ISP and the programer is extremely simple. Schematics are available in most of the Lattice data sheets for the ISP devices. It is just a 74HC367 attached to a parallel port. The thing I like it that the part (ispLSI1016 90MHz) are around $15 CAN. each in quantities of 10. I am not associated with Lattice or anyone else :) Alex LaitArticle: 7205
Did anybody check the data book That power consumption is probably just about right for an Altera 7K CPLD! EdArticle: 7206
Hello, I ordered a Altera 10K100GC503. I have search for AMP amd 3M but no such high pin counts PGA socket for this device, does anyone know where can I order a 503 pins PGA socket for this device? Thank you! Roger Yau R & D Engineer Easson Precision Ltd. http://www.net.polyu.edu.hk/~rogeryauArticle: 7207
Yau Man Wai , Roger wrote:
>
> Hello,
> I ordered a Altera 10K100GC503. I have search for AMP amd
> 3M but no such high pin counts PGA socket for this device, does
> anyone know where can I order a 503 pins PGA socket for this device?
> Thank you!
Try BERG electronics (McKenzie Socket Division). Part #
pza503h011A-43ABS
I don't want to be mis-leading, but I had scribbled this
number down on a piece of scratch paper and I think that
when I ordered the sockets that one of the digits/letters
is wrong. Sorry, but I don't remember which one. However
you can call Berg at (510)651-12700. BTW, this is not a
ZIF socket.
Scott
--
__o
I buy pizza instead of gas. \<
(*)/(*)
Article: 7208The Altera MAX 7000 devices are CPLDs. In general, CPLDs have a much higher quiescent current than do most FPGA devices. For example, there is a diagram on page 234 in the Altera 1996 data book showing Icc vs. Frequency for the EPM7128E (MAX7128). In non-turbo mode (i.e. low power), the graph starts at about 55 mA. In turbo mode (i.e. high speed) the graph starts at about 150 mA. What you are seeing is probably typical, but the value is part specific. If you are using a smaller MAX device, you'll see a correspondingly smaller Icc. I have not seen a specific study of power consumption of difference devices. In general true FPGA devices are lower power than most CPLD devices, the exception is probably the Philip's CoolRunner CPLDs. The quiescent current for most FPGAs is significantly less than for most comparably-sized CPLDs. At higher frequencies, the dynamic current becomes the dominant factor. FYI, there is also an article in the August 1, 1997 edition of EDN magazine entitled, "Programmable Logic: Beat the heat on power consumption", beginning on page 57. There is also a chart on page 76 entitled "Representative power-optimized programmable logic devices". For a complete listing of FPGA and CPLD companies' web-sites, see 'http://www.optimagic.com/companies.html' and 'http://www.optimagic.com/summary.html'. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com David Bokaie <dbokaie@ix.netcom.com> wrote in article <33F1DA46.2AF4@ix.netcom.com>... | In our latest design we have notice that our Altera 7K FPGA is drawing | roughly 100ma of current. Stopping the clock to the chip only reduced | the power consumption by 30%. I was wondering if there is any study out | there that | | 1) explains the high power consumption of FPGA | 2) compare power consumption between different FPGA vendors | and different technology family. | | Please send/or copy your responses to davidb@proxim.com | | Thanks, | | David |Article: 7209
>So tell them that you have redesigned and are going to program the >FPGA from a micro. If they jack up the price, then design them out, >and (please) provide documentary evidence to this newsgroup. I'm sure >somebody would be happy to stick a few K of GIF's on a web site to >prove the point. I do quite a few projects every year, and the decision on whether to use a prom or program from a microprocessor is up to the client. Sometimes you just gotta use the prom, though. As far as the PROM pricing goes....I personally don't care if they gouge people or not. I do consulting work, and my clients usually make the final choice of product (XILINX, Lattice, ORCA, Altera, ASICS, etc)...I just present them with options. You have to look at the total system price...but people very often forget to do that. >I personally would cease designing with any manufacturers product who >attempted to blackmail me in such a way. It's not like Xilinx is the >only vendor out there. The real problem here is proprietary architectures and software...not some miniscule techno issue like PROMs. The faster we get out of proprietary parts and tools, the faster we can turn the FPGA into a commodity product. It'll kill the manufacturers' margins, but that's okay. The bottom line is that 'gates are gates'. Ultimately, the FPGA will be an interchangeable commodity. A few years ago the PAL was hot stuff, but today they've just become 'me too' products. FPGAs will go the same route in a few years. >Maybe the perceived threat was from a desparate salesman? I still >can't believe it's Xilinx policy to blackmail customers with massive >price rises. I have no idea if it's an orchestrated issue. All I know is what I see and the people I talk to. Sometimes if it looks like a duck, walks like a duck and quacks like a duck...then it is a duck. All that I ask is that the manufacturers sell me the gates, answer my questions and stop asking me for proprietary information. WadeArticle: 7210
I am currently looking for a hard IP core for a serial transciever able to function at 1.25+ Gbit/Sec. Has anyone seen any ASIC technology that provides this core as a purchasable macrofunction? If anyone has any experience in this field I would appreciate some direction. So far all I have found is LSI Logic w/ their Gigablaze Technology. Thanks In Advance: Dean Susnow Dean_Susnow@ccm.co.intel.comArticle: 7211
David, A suggestion; see my article on programmable logic power consumption in the August 1, 1997 issue of EDN magazine. Also on our website <http://www.ednmag,com>. Hope it helps! <dbokaie@ix.netcom.com> wrote: >In our latest design we have notice that our Altera 7K FPGA is drawing >roughly 100ma of current. Stopping the clock to the chip only reduced >the power consumption by 30%. I was wondering if there is any study out >there that > > 1) explains the high power consumption of FPGA > 2) compare power consumption between different FPGA vendors > and different technology family. > >Please send/or copy your responses to davidb@proxim.com > >Thanks, > >David Brian Dipert Technical Editor EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) edndipert@worldnet.att.net Visit me at <http://members.aol.com/bdipert>Article: 7212
>[snip] >Xilinx didn't lose a >EEPROM sale there: there never was one. Is XILINX selling EEPROMs yet (i.e. electrically erasable proms)? Last time I checked you had to buy Lucent parts if you wanted an electrically alterable one. The XILINX parts were all 'burn once and throw away'.Article: 7213
Sorry if a post has been made like this, but my news server crashed and finally (thank God) burned. But I have an unusual take on Xilinx programming, perhaps... My stuff goes into telephony applications -- powered up for (hopefully) years on end, no technicians around to press the "reset" switch, so we ALWAYS have a microprocessor that scans the RAM array to be sure it hasn't been corrupted. We use the venerable 8052, which just doesn't have enough room to hold RAM array and verification information, so we use Xicor EEPROMs to hold the Xilinx data (EPROMs consume too much space). Since they're Electrically Eraseable, there's no waste, and Xicor makes Xilinx look sick, price-wise. But, you can't reset them and stream-read them like the Xilinx parts, so you HAVE to have a microprocessor. I'd love to use the Xilinx EPROMs, if they could just cost in ... their interface is admirably simple.Article: 7214
There is an ever growing list of free, downloadable software for FPGA or CPLD design at 'http://www.optimagic.com/lowcost.html'. Some of these are demo versions, where you have access to only a few devices but others, like the Actel software, are more comprehensive. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 7215
Roger,
The following is from the Altera web site (www.altera.com) and was found by
searching on the word "socket" in the solutions database. Hope this helps...
Wayne
Begin included text --------------------------------------------------------
Sockets for 503-pin PGA packages are shown below:
Zero-Insertion-Force Sockets
============================
Vendor Part Number Type Price Phone Number
---------------------------------------------------------------------------
AMP 382876-6 Note (1) --- (800) 522-6752
(800) 331-9857 x05410
Yamaichi NP-236-102002-AC01601 Lever Arm $220 (408) 456-0797
3M/Textool 2-0503-01357-050-019-002 Lever Arm $350 (800) 3M-HELPS
(800) 421-2244
End included text --------------------------------------------------------
In article <33F334B7.7F9E@net.polyu.edu.hk>,
"Yau Man Wai , Roger" <rogeryau@net.polyu.edu.hk> wrote:
>Hello,
> I ordered a Altera 10K100GC503. I have search for AMP amd
>3M but no such high pin counts PGA socket for this device, does
>anyone know where can I order a 503 pins PGA socket for this device?
>Thank you!
>
>Roger Yau
>R & D Engineer
>Easson Precision Ltd.
>http://www.net.polyu.edu.hk/~rogeryau
Article: 7216Wade D. Peterson wrote: > > >[snip] > >Xilinx didn't lose a > >EEPROM sale there: there never was one. > > Is XILINX selling EEPROMs yet (i.e. electrically erasable proms)? > Last time I checked you had to buy Lucent parts if you wanted an > electrically alterable one. The XILINX parts were all 'burn once and > throw away'. Info. on Atmel ISP EEPROM (that's electrically erasable not OTP EPROM like the other manufactures parts) can be obtained from the Atmel web site.... http://www.atmel.com/atmel/products/prod22.htm Now supplying industries first 5v AND 3.3V only (programming voltage) ISP configurators. Martin Mason AT17Cxxx Series Marketing and Apps. Atmel Corp.Article: 7217
<<<COMPUTER HARDWARE / SOFTWARE>>>
UP TO 70 % OFF !!!
http://members.aol.com/Auction1st
<>><><><=<=>=>><><<<
Article: 7218
peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote:
>>[snip]
>>Xilinx didn't lose a
>>EEPROM sale there: there never was one.
>
>Is XILINX selling EEPROMs yet (i.e. electrically erasable proms)?
>Last time I checked you had to buy Lucent parts if you wanted an
>electrically alterable one. The XILINX parts were all 'burn once and
>throw away'.
>
Altera are the same.
Amazing isn't it. You want 100K+ gates, no problemo. You want a
simple re-useable method of reprogramming it. Oh dear :-(
The effort being expended by these two companies to put more and more
gates into these magic black boxes is simply enormous. How many
designers are working on their ¼ million parts? What tiny fraction of
that effort would be required to develop simple flash/EE prom? Is the
process technology _that_ different?
Thank heaven for Atmel.
Just my 2p
Julian
--
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
Hardware development eng. August Systems Ltd
---------------------------------------------------------------------
Article: 7219Alex Lait wrote: >I am using the Lattice 1016 devices (2K gates claimed). I got the design >software free from Lattice. I don't think you can download it but you >can request a free cdrom with it. It supports all Lattice devices from >GAL to ispLSI1016. The software to develop the larger devices (up to 8K >gates) is just $500 US. The software is based on the Data IO Synario >package and supports schematic as well as text design entry and >functional simulation. The only portion of the package I find lacking is >the timing analyses. There is a module to do some static timing but that >seems to be it. > >These devices are ISP and the programer is extremely simple. Schematics >are available in most of the Lattice data sheets for the ISP devices. It >is just a 74HC367 attached to a parallel port. > >The thing I like it that the part (ispLSI1016 90MHz) are around $15 CAN. >each in quantities of 10. > >I am not associated with Lattice or anyone else :) > >Alex Lait ** Plug Mode On ** We (Philips CoolRunner Fast Zero Power CPLDs) offer several free/inexpensive design options today: * XPLA Designer 32 - $Free! Supports both our 3V and 5v 32 Macrocell Devices, Includes our own tool (which does HDL Synthesis and AC Sim), and Synario schematic capture, ABEL HDL, and sim > May be requested at www.coolpld.com * XPLA Designer Contest Kit $99 Includes XPLA Designer - the full tool that supports 3v & 5V 32/64/128 and future devices (free updates via the Web), a 5V PZ5128 (128 macrocell) ISP Prototyping Board, PC-ISP download software, and PC-ISP parallel port to JTAG ISP download cable (we do provide info on making this cable yourself). Order code PZCONTEST - corresponds to a contest running in the USA, the kit is available at this promotional price worldwide. *PZLCP - Low cost PC Windows based programmer - base config (44-pin PLCC support) $395. ** Plug Mode Off ** - mark Mark Aaldering mma@rt66.com Mark.Aaldering@abq.sc.philips.comArticle: 7220
In article <33F3D722.7218@imxtech.com>, Bill Ewing <bewing@imxtech.com> wrote:
>...so we ALWAYS have a microprocessor...
> We use the venerable 8052, which just doesn't have enough room to hold
>RAM array and verification information, so we use Xicor EEPROMs to hold
>the Xilinx data (EPROMs consume too much space). Since they're
>Electrically Eraseable, there's no waste, and Xicor makes Xilinx look
>sick, price-wise. But, you can't reset them and stream-read them like
>the Xilinx parts, so you HAVE to have a microprocessor...
Do remember that you can now get cheap uCs in 8-pin packages, so the
overhead of having a microprocessor present has gotten quite low. Not
zero, but low.
--
Committees do harm merely by existing. | Henry Spencer
-- Freeman Dyson | henry@zoo.toronto.edu
Article: 7221Xilinx is doing some things that I'm realy impressed with. They are doing away with anything that they have to pay a royalty on. They did a one-time lisence with Aldec to distribute SusieCad. That one had to set them back BIG bucks. Aldec is about as mercenary as anyine I've ever dealt with. THey are writing their own ABLE compiler to replace XAble. What that means is that they now control the bottom line price of their software. If you talk nice to one of their reps, you may get a copy of their developement system for very little, basicly the cost of media and handling. I got one at a seminar for $99. > Dave, >Have you checked out our kits at http://www.associatedpro.com/aps Our >XILINX kits are inexpensive and we have been able to set up plans for >the *impoverished* at times which could perhaps meet your needs. (we all >are, or were there once). >-- >---------------------------------------------------------------- >Richard Schwarz, President >Associated Professional Systems (APS) >EDA and Communications Tools >http://www.associatedpro.com >richard@associatedpro.com >410.569.5897 fx:410.661.2760 Remove the "nospam." to get at my email address. I appologize for the no spam address, but I'm real tired of email trash.Article: 7222
can anybody compare this tool with other comparable tools? how easy is it to learn?how is the support? thnaks umesh __________________________________________________________________ Undertake something that is difficult,it will do u good; Unless u try to do something beyond what u have already mastered you will never grow -:Ronald E Osborn __________________________________________________________________Article: 7223
Our group is interested in strengthening its competence in the hardware/software codesign area and have vacant position for researcher/postdoc for a couple of years. Further information is available at "http://www.idi.ntnu.no/adm/utlysn970717.html#postdoce". Information on the university is available at "http://www.ntnu.no/faksent/indexe.html" and on our department at "http://www.idi.ntnu.no/indexe.html". (The deadline is 20th august) Lasse Natvig Department of Computer and Information Science (IDI) Norwegian University of Science and Technology (NTNU) N-7034 Trondheim, NORWAY / E-mail: Lasse.Natvig@idt.ntnu.no URL: http://www.idi.ntnu.no/~lasseArticle: 7224
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