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No, I did not, because the misc_logic is written in Verilog and I have no idea about Verilog, so I "ported" that piece of code to VHDL. The code in Verilog is as follows: always @(posedge clk) pci_int_or <= (~pci_inta) | (~pci_intb) | (~pci_intc) | (~pci_intd) | (~pci_inte) | (~pci_intf) | (~pci_core_intr_a) | (sbr_int); Which I wrote in VHDL as: process(clk) if(clk'event and clk='1') then pci_merge <= pci_sbr or not pci_inta or not pci_intb or not pci_inc or not pci_ind or not pci_inte or not pci_intf ot not pci_core_intr_a; end if; end process; The pci_merge signal is connected to the interrupt zero pin, which is the same that is using in the base configuration provided by Xilinx. I have also modified the xparameters_ml300.h generated by the EDK in order to get the linux kernel using that interrupt for all PCI devices. I think both codes are doing the same, aren't they? However, the base configuration from Xilinix is using a really old opb2pci bridge (if I try using it I get an error because it is deprecated) and I'm using the latest one. Both cores have the same interrupt lines, but I do not know if they are compatible. My first guess was that maybe in the current core the pci_int<a> lines are active in high, so instead of merging the signals inverting the pci_int<a> and making a logical or I didn't invert them. Unfortunately the result was the same :(. Right now I am merging all the signals as shown on the previous VHDL code but not using pci_inte, pci_intf pci_core_intr_a, which I think there are not used by my hardware configuration. With this schema only the PCI-IDE controller is getting interrupts. I will try to also include the pci_core_intr_a in the merge logic. But, as you can guess, I am trying different configurations without knowing what I am really doing. IsaacArticle: 97876
Ivan, I posted the full link twice - sorry you did not get it from my first posting. Info on Paul's website says tested on V2Pro only - as of today I can confirm that it works completly 'out of the box' on V4FX also inclusive ehternet. No issues. Just build load and run. I had not tested networking yesterday, actually its a board where ethernet has not been tester before at all, I only had the UCF file setup, and when I booted ppclinux, well even network worked, I only had to ping :) AnttiArticle: 97877
Hi Guys Does anyone have a CLB / LUT/ FF/ BRAM count for the microblaze with and without the FPU on a Spartan 3 ? I'm trying to do some estimation...Article: 97878
Sounds like you want someone else to do the estimation :-)Article: 97879
s3-1000 MB: 4.0 cache NO FPU integer mul lmb ram opb gpio Number of MULT18X18s 7 out of 24 29% Number of Slices 1486 out of 7680 19% Number of SLICEMs 251 out of 3840 6% same, with no FPU and no imul Number of Slices 788 out of 7680 10% Number of SLICEMs 244 out of 3840 6%Article: 97880
Antti wrote: > Ivan, Hi Antti, > > I posted the full link twice - sorry you did not get it from my first > posting. Info on Paul's website says tested on V2Pro only - as of > today I can confirm that it works completly 'out of the box' on V4FX > also inclusive ehternet. No issues. Just build load and run. Don't worry. Thanks. I have a Virtex-II Pro FPGA, but it is interesting to know that it works on Virtex-4 FX too. > > I had not tested networking yesterday, actually its a board where > ethernet has not been tester before at all, I only had the UCF file > setup, and when I booted ppclinux, well even network worked, I > only had to ping :) It sounds good!! ;) Regards, IvanArticle: 97881
Mark McDougall wrote: > Jim Granville wrote: > > > The simplest export scheme is SPI, which is also much faster than > > i2c. i2c also has poorer noise immunity, so that needs watching in a > > Motor Controller app. That said, if you can only get your DACs in > > i2c, then the decision is made for you. An i2c master will need a > > manager state engine, to handle ACK/NACK instances, and bus lockup > > recovery, as well as organise the address / data. -jg > > There are both I2C and SPI (master) cores on opencores. I've used both > and they work for me. > > Regards, > Mark DAC's are also available in many interfaces. I've used the LTC1660 from Linear Tech. These have a very simple serial interface and you can string them in series if you need more than 8 voltages. Going from FPGA to FPGA you may want to do your own simple serial interface instead of either SPI or I2C. Depending on how many wires you're willing to use you may simplify your design significantly by using point-to-point connections instead of a common multi-master bus like I2C. Good Luck, GaborArticle: 97882
I just converted a quad port 2r2w to F/Fs this morning; luckily, it was easy to simplify. You don't give enough info - are the clocks related? How big is it? Do you have higher frequency clocks available? Curious that you should have a library with no 2rw memories in it. Can you tell us whose it is? It sounds like it may too new to be usable. SeanArticle: 97883
XST can fail that way if output files are read-only (XST can't overwrite them). On Mon, 27 Feb 2006 09:23:00 +0100, Matthias Alles <alles@rhrk.uni-kl.de> wrote: >Hi, > >I encounter a serious problem with xst when I try to synthesize a >design. The design consists of several components that synthesize fine >for themselves. However when I want to synthesize the top entity, that >only plugs the simple components together, xst fails during the low >level synthesis without giving me any reason WHY synthesis failed. >It's the same for ISE 6.3, 7.1 and 8.1. >Is there a way to find out why xst fails, something like a debug or >verbose mode? Or has anyone an idea how to isolate the problem? > >Thanks in advance! >MatthiasArticle: 97884
Eric Smith schrieb: >>If there are any outputs that depend on less than 14 inputs push those >>into BlockRAMs. > > > There aren't; they all need more than 50. Didn't you say something about 25 inputs? Kolja SulimmaArticle: 97885
Eric Smith schrieb: > Kolja Sulimma <news@sulimma.de> writes: > ISE seems to understand this part just fine; I wasn't sure whether > a comparison with "X" in the literal would work: > > p126 <= '1' when i_word = "X1X...10" > else '0'; That would not work. There are IEEE comparison functions to do that (using '-' not 'X') but our version is just as good. I thought you had don't cares in the function: p126 <= '1' when .... else '-'; I think you really need multi level resynthesis to get anything suitable for an FPGA. In principle ISE should do that, but this is a rather extreme case that it is not tuned for. I am not a big fan of BDDs, but in your case it might be worthwhile to give it a try. ISE should be better in flattening circuits of high depth than refactoring SOPs. http://www.consiste.dimap.ufrn.br/~sergio/vis/glu-1.4/src/cuBdd/doc/ Kolja SulimmaArticle: 97886
I've been trying to follow your problem and now have time to lend some help. I'm going to approach this from a black-box design point of view. First question is how are in implementing it or what language are you using (VHDL, Verilog or something else)? What size device are you looking to create (data and address bus width)? Or are you trying to create a library device? What device and signals in the original design being used? DerekArticle: 97887
Antti, Any chance you can report some power consumption numbers and the clock rate of the PPC? Particularly the power delta between MB linux and PPC linux? I'm on the hook to produce an embedded linux platform at under 2 watts and I'm anxious to know how hard it will be. Thanks, Clark "Antti" <Antti.Lukats@xilant.com> wrote in message news:1141141108.784065.172110@i40g2000cwc.googlegroups.com... > Setting up MicroBlaze-uClinux on new FPGA board is a matter of hours - > with PPC linux, well there are gurus around claiming that it can be > done > within 4 hours - so far I have been very sceptical against such claims > mainly as I had until 10 minutes ago never created a Xilinx FPGA PPC > system with linux booting capability > > So my schedule was > > 1 New V4 PPC system with EDK (complete from scratch) > 2 ppc u-boot, compile test working > 3 ppc uClinux, build load run, console prompt > ================== > => 2.5 days work > > that is a defenetly more than 4 hours, but hey I believe > now that some guy with extensive linux-ppc-fpga experience > could have managed it all in 4 hours. First time try til > succesful linux prompt its just me who needed a bit more :) > > When its done it always simple, the PPC capable linux SoC > requirements are actually same as for the microblaze uclinux > ram, intc, timer, uart, > then load linux.bin start and you get console prompt! > > so my way to working PPC (uc)linux (with MMU !) was > > 1 VMWARE player, KDE 3.5/SUSE > 2 http://www.itee.uq.edu.au/~pml/uclinux_powerpc/ > 3 build > 4 WinXP, EDK 8.1 SP1, BSB new design, add uart, timer, plb sdram > 5 configure, start bootloader, > 6 wath the uclinux to boot up > > I had to run synthesis maybe 8 or 9 times to get 'linux-ready' > bitstream, and I spend lots of time trouble shooting the kernel > as I used old version (make copied the new kernel to tftboot > not to tftpboot from where I fetched it...) > > jipii jeee!!! > > Antti > PS at the same clock frequency the V4 PPC design seems to > use less power (V4FX12-363 is not warm at all!) then similar > microblaze design in the same device >Article: 97888
Hallo, has someone found some example about hard temac and how to connect it to plb bus and broadom phy layer of the module? Many Thanks Marco ToschiArticle: 97889
Hi Clark, I dont have comparison results, I commented mostly on the 'finger' feeling data I can give: V4FX12-SF363, everything clocked from 72MHz, the SoC has plb sdram (3.3V powered), uartlite, timer, ethernet, development platfrom HydraXC-50 on LEEB eval board, some info (also picture of the modue on eval board) http://www.hydraxc.com power consumption as measurer from 5V supply 160ma when FPGA not configured, 250ma when configured (eg running FULL linux) hope this helps :) if you use lower powered memory and any other power lowering tricks you should be able to get nice system with 2W power consumption, of course you can have options to increase, or lower the clock to get higher performance or lower consumption, optionally you may lower the 1.2 a little this is nondocu by xilinx (they have not specified it) - Lattice is offering low power mode for LatticeSC where the core running at 1.0 (not 1.2) is giving power advantage with timing lowered by 35 % (from memory maybe less), similar trick should be possible for Xilinx also, or even better self adjustable core regulator that adjust the voltage as of performance needed. AnttiArticle: 97890
I dont think so. dont be lazy - adding TEMAC to PLB is exactly 2 mouseclicks in EDK give it a try! AnttiArticle: 97891
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1141232593.803644.24780@u72g2000cwu.googlegroups.com... >I dont think so. > dont be lazy - adding TEMAC to PLB is exactly 2 mouseclicks in EDK give > it a try! > > Antti > I have tried using plb_temac, but I have some troubles with connecting the phy layer. Where I sould connect the signals mdc and mdio?Article: 97892
Hi all, I want to use a small cricuit (written in verilog and was designed using ISE 3) in an other project using ISE 8.1. the problem is that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is an error. why this occur ?Article: 97893
Presumably this depends on what ASIC libraries you have. There is no inherent reason that an ASIC library could not include dual-port memories. Apparently the original poster's didn't.Article: 97894
That is a clever solution that I hadn't thought of. Of course, your VALID_BIT array needs the capabilities of a true dual-port memory. So this doesn't really build a dual-port memory just out of RAMs. It builds it from 4 RAMs and a smaller dual-port memory (just as many elements, but only 1 bit wide). You would have to build that smaller dual-port memory out of flip-flops. The result still might be smaller than building the full-size memory out of flip-flops.Article: 97895
Hello, I have this question and I have no idea if this is a simulator quirck or bad design. I am designing a pulse reconstruction type of design (Pulse processing application). I use the incoming pulse stream and delay it by 30 us and output it. What I am observing is that the pulse characterstics (only pulse width) of the first output pulse is different(shorter pulse width) even though its just a delayed version of the input. This happens only with the first pulse that is delayed and all the pulses following have the right pulse width. I am observing this in a functional as well as in a timing simulation. I suspect there is some problem with the design but just wanted to get an opinion. Maybe its the simulator? Thanks MORPHEUSArticle: 97896
How do you delay the pulse stream? Rgds Andr=E9Article: 97897
>What FPGA? xilinx xc3s200 >What I/O supply voltage? 3.3v >How fast? a bit faster than 1 MHz >For others you may want to use special level translators or perhaps 3.3 >volt buffers with 5v compatible I/O. Anybody have links to level translator components, or a 3.3v buffer with 5v i/o? >Also, what logic family are you using on the 5v side - TTL TTL RichArticle: 97898
"Marco T." <marc@blabla.com> schrieb im Newsbeitrag news:du4khs$765$1@nnrp.ngi.it... > > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1141232593.803644.24780@u72g2000cwu.googlegroups.com... >>I dont think so. >> dont be lazy - adding TEMAC to PLB is exactly 2 mouseclicks in EDK give >> it a try! >> >> Antti >> > > I have tried using plb_temac, but I have some troubles with connecting the > phy layer. > > Where I sould connect the signals mdc and mdio? > nnect them same way as for non hard temac! should not be any different, or what is your problem exactly? AnttiArticle: 97899
Well ... they've put out yet another (minor) release, and it's still broken. It's been over a month now. I've been focused on ECS, since I like schematic entry, since that's what my clients want. The other parts of ISE seem to be similarly broken, though. There are icons that don't work, the windows that pop up at certain times in what once was "normal" processing disappear and there's no way to get them back, and so on ... I'm still using v6.3.03 with some success, but I'm unable to figure out how to do anything useful with v8.1.02. Why would XILINX allow such a gigantic step backward? Richard
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z