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Silly me. I made a mistake. ;-( Should have known better, will come up with another solution. Peter Alfke > From: TommyInTheNews@numba-tu.com > Newsgroups: comp.arch.fpga > Date: Tue, 09 Mar 2004 17:21:56 GMT > Subject: Re: Release asynchrounous resets synchronously > > Peter Alfke wrote: >> Eh, what? Unfortunately anonymos... > > Sorry, Tommy Thorn, tommy at numba-tu dot com. > >> Each first level LUTs detects (output High) that exactly one of its inputs >> is High. >> The second tier LUT detects that exactly one of the first-tier LUT outputs >> is high, which mans that there is exactly one High input. >> Agreed ? > > Did you actually read what I wrote? It doesn't work. > > Take for example 16'b1111_1110_1100_0001, only one of the nibbles has > exactly one bit high, so the first tier LUTs goes 0 0 0 1, which has > exactly one bit set and your scheme would say that's a valid state. > > You need to distinguish 0, 1, and more, thus use roughly twice the LUTs. > > Thanks, > > Tommy > >Article: 67276
"Jack Moderatz" <jyhur@wanadoo.nl> wrote: > Currently I need binary bit stream file(configuration file) examples (any > applications are okay) for analysis.........Can somebody tell me how I can > obtain them? Connect a logic analyzer and boot the board. -- Mike TreselerArticle: 67277
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<404d756d@news.starhub.net.sg>... > well, maybe that is why i couldnt simulate the Samsung SmartMedia model with > Modelsim... > How do I find out which is the right simulator? Call Samsung? --aArticle: 67278
SRL16's are great for small reordering tasks too.
John_H wrote:
> konerusreeram@yahoo.com (sree) wrote in message news:<195eee74.0403090047.1e494af9@posting.google.com>...
> > Hi,
> > i am new to FPGA's and vhdl.i need to design a sorter of N numbers 32
> > bit each.i know sorting algorithms bubble sort.But i found that in
> > fpga's we can do bit comparision parallel and there are fast sort
> > methods i can use.i saw a couple but not sure how to implement on
> > virtex-II xc2v1000 which has a 100MHz clock.If some body have an
> > hardware discrption or digital schematic please let me know.i
> > appreciate their help
> > thank you
> > sree
>
> Do you need all 32 values at the same time such that you're processing
> N values on *every* clock expecting the sorted values with a few clock
> cycles latency, a new sorted list on every clock?
>
> Is your time less critical? Do you need one value at a time from
> highest to lowest or vice-versa? Do you just need the value or do you
> need to know which entry it was in the original list?
>
> As a for-instance, the bitonic sort will give a great parallel sort
> algorithm providing a list of N sorted elements every clock but with a
> huge amount of resources to accommodate the parallelism.
>
> BlockRAMs are great for doing manipulation of the large numbers for
> comparisons between 2 entries every clock cycle making them handy for
> some sort algorithms.
>
> If you read the values in one at a time, some of the sorting can be
> performed as you build up your array rather than waiting until it's
> fully in place.
>
> So - state your needs.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67279konerusreeram@yahoo.com (sree) wrote: > i am new to FPGA's and vhdl.i need to design a sorter of N numbers 32 > bit each.i know sorting algorithms bubble sort. Well, that's more fun than a vending machine. A vhdl prototype might include: An array of constants for input, An array of variables for the sort process. A rollover counter variable to loop through the array until done. A procedure to swap array values-- called once per clock. A done boolean to remember if no swaps were need on the last pass. --Mike TreselerArticle: 67280
Hi, Go read http://www.engr.sjsu.edu/crabill/module06.pdf I've got an example of a bubble sort, written in Verilog. This was meant to illustrate how you can take sequential algorithms from a CS text and implement them in hardware. And get lackluster results. Then, there is an example of an odd-even transposition sort, which is a parallel algorithm for sorting. The result is compared to the bubble sort in terms of fmax. Hope that helps, Eric sree wrote: > > Hi, > i am new to FPGA's and vhdl.i need to design a sorter of N numbers 32 > bit each.i know sorting algorithms bubble sort.But i found that in > fpga's we can do bit comparision parallel and there are fast sort > methods i can use.i saw a couple but not sure how to implement on > virtex-II xc2v1000 which has a 100MHz clock.If some body have an > hardware discrption or digital schematic please let me know.i > appreciate their help > thank you > sreeArticle: 67281
Peter,
Consider the case where you have 1 input high to one of your luts, and 2 inputs
high to another lut. It is clearly an illegal state, as it has two extra '1' bits,
but it will be detected as OK by your circuit because exactly one LUT is indicating
one input on. Each group of four requires two outputs to distinguish 0,1 or more
than 1 input on.
Peter Alfke wrote:
> Eh, what? Unfortunately anonymos...
>
> Each first level LUTs detects (output High) that exactly one of its inputs
> is High.
> The second tier LUT detects that exactly one of the first-tier LUT outputs
> is high, which mans that there is exactly one High input.
> Agreed ?
> Peter Alfke
>
> > From: user@domain.invalid
> > Newsgroups: comp.arch.fpga
> > Date: Tue, 09 Mar 2004 05:24:26 GMT
> > Subject: Re: Release asynchrounous resets synchronously
> >
> > Peter Alfke wrote:
> >> LUTs are very efficient "illegal state" detectors.
> >> Let's say you have a 16-state one-hot machine. Four LUTs can each detect
> >> "exactly one of my inputs is High", and a fifth LUT does the same with the
> >> four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it
> >> from there...
> >
> > Eh, what? So the first tier LUT compute f, where
> > f(a,b,c,d) = 1 iff a+b+c+d = 1, else 0.
> > For the 5th LUT we have the same property that a legal 16-state would
> > map exactly one of the four first tier LUTs to 1, thus it sounds like
> > what you have in mind is something like this:
> >
> > f({f(s[3:0]), f(s[7:4]), f(s[11:8]), f(s[15:12])})
> >
> > but this could accept states like 16'b1111_1110_1100_0001.
> >
> > I don't see how you can detect legal states with only five four-input LUTs.
> >
> >
> > Peter, the FPGA reset question has come many times. What does Xilinx
> > recommend in general? Async-reset+Sync-release, all-sync, or all-async?
> > Which uses fewest resources?
> >
> > Thanks,
> >
> > Tommy
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67282"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<104rmkoja30hm04@news.supernews.com>... > Altera has a simple "Security Bit" that is supposed to keep other > programmers from being able to read your config from either the FPGA or its > config device. I have no idea how secure this actually is in practice. I > guess it might at least throw up a hurdle to to some? > > Ken > > "millim" <merlin1974@gmx.at> wrote in message > news:8e53c613.0403080739.aa1236b@posting.google.com... > > I am trying to find an efficient and simple way to protect > > prototypes from cloning. > > > > One idea relies on using the serial number of the FPGA device, > > because in any prototyping phase only a hand full devices are > > present. But is there an embedded hardware register in the FPGA device, > > which contains a unique serial number? > > > > regards Over the years a few customers have claimed that they could break the security bit on MAX devices. We tested them by giving them secured devices and asked them to give us back the programming file. None were successful. For the specific question of an embedded serial number - Altera has just introduced a new line of CPLD called MAX II. This device family has a User Flash Memory of up to 8 kilobits, enough to store serial numbers and plenty more. For details on the family and the User Flash Memory, check out the technical literature on: http://www.altera.com/literature/lit-max2.jsp Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 67283
In article <8e53c613.0403080739.aa1236b@posting.google.com>, millim <merlin1974@gmx.at> wrote: >I am trying to find an efficient and simple way to protect >prototypes from cloning. > >One idea relies on using the serial number of the FPGA device, >because in any prototyping phase only a hand full devices are >present. But is there an embedded hardware register in the FPGA device, >which contains a unique serial number? If you are using a Xilinx, the V2/V2Pro bitfile encryption is a VERY high barrier for an attacker to cross: I'd comfortably protect a $10K secret, and uncomfortably protect a $100K secret from a malicious, capable adversary. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67284
rickman <spamgoeshere4@yahoo.com> wrote in message news:<4044BE39.A2074EB8@yahoo.com>...
>
> This is exactly what I am talking about. Even though the synthesis tool
> is capable of inverting a FF input and output in the logic equations so
> that a reset to zero operates as a preset to one, there has to be a way
> to tell the tool in your HDL that it needs to do this on a given FF.
>
> *That* is what I am asking about.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
Rick,
The way to do this (set a certain register to appear to power up high,
on power up or on chip wide reset) is to use the POWER_UP_LEVEL=HIGH
assignment.
This creates a DFFE that will appear to power up to high after a
chip-wide reset. As we do not have hardware to implement this option
for core FFs on ACEX parts it will be implemented by inverting the
input and output to the DFF. The altera_attribute syntax will only
work in Quartus Integrated Synthesis. Synplify and Leonardo may have a
similar attribute; otherwise, you can make the POWER_UP_LEVEL
assignment from the Assignment Editor in the Quartus UI.
Here's a code example that shows how to do this:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY wysiwyg;
USE wysiwyg.stratix_components.all;
ENTITY attr2 IS
PORT (
data, clk, ena : IN std_logic;
o : OUT std_logic
);
END ;
ARCHITECTURE rtl OF attr2 IS
SIGNAL tmp : STD_LOGIC;
ATTRIBUTE ALTERA_INTERNAL_OPTION : string;
ATTRIBUTE ALTERA_INTERNAL_OPTION OF tmp : SIGNAL IS "POWER_UP_LEVEL
= HIGH";
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1';
IF ena = '1' THEN
tmp <= data;
END IF;
END process;
o <= tmp;
END ;
There is no other good way of doing this in your VHDL: the chip-wide
reset is not specified as part of the VHDL code you write, it is
hardware that comes "free" with every FF.
Sincerely,
Greg Steinke
gregs@altera.com
Altera Corporation
Article: 67285
"SneakerNet" <nospam@nospam.org> wrote in message news:<Qea3c.6567$Nc3.108000@news.xtra.co.nz>...
> Hi Subroto
>
> Thanks for the clarification.. This means I must have used my own code to
> generate the 12.5MHz. Oh well back to using the logic.
> Thanks again
>
> Regards
>
> "Subroto Datta" <sdatta@altera.com> wrote in message
> news:41a3c.22164$cY5.21375@newssvr31.news.prodigy.com...
> > Hi Sneakernet,
> >
> > You cannot implement their desired output frequency of 12.5 Mhz using the
> > Cyclone PLL without going out of spec.
> >
> > The Cyclone PLL does have a minimum output frequency limit, which is a
> > function of the PLL's minimum VCO frequency. The minimum VCO frequency is
> > 491Mhz, and the maximum output divider counter size is 32, which results
> in
> > a minimum output frequency of approximately 15.3 Mhz (i.e.491/32).
> >
> > Page 4-31 of the device handbook gives the PLL frequency specs. The input
> > frequency has to be between 15.625 MHz and 464 MHz for the
> > fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the
> slowest
> > (-8) speed grade. See
> > http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.
> >
> > - Subroto Datta
> > Altera Corp.
> >
> >
> > "SneakerNet" <nospam@nospam.org> wrote in message
> > news:Ow43c.6282$Nc3.101499@news.xtra.co.nz...
> > > Hello Ppl
> > >
> > > I have actually already asked this question before but I need help
> again.
> > >
> > > I'm using a Nios Development Board (50MHz Oscillator, FPGA = Cyclone
> > > EP1C20F400C7). I'm using Quartus II v4.0 Build 190
> > > I need to generate a clock speed of 12.5MHz. While I have my own vhdl
> code
> > > that can do this, I can't use the ALTPLL to do this for me.
> > >
> > > How can i do this? When I try to generate a speed of 12.5MHz using
> > > MegaFunction Wizard in Quartus it complains ('Post divider max count
> > > exceeded')
> > > Does this mean there is a lower limit? Is there a way to achieve this
> speed
> > > using ALTPLL and the above specs?
> > >
> > > Thanks
> > >
> > >
> >
> >
SneakerNet,
You can take the 50 mhz clock into a 2 bit counter and take the output
of the MSB for 12.5 MHz. This can drive a global clock tree within the
device to minimize skew between all registers driven by the 12.5 MHz.
The only drawback is that you will have some skew between the 50 mhz
and 12.5 mhz domains, so you need to be careful with data transfers
across the domains.
Or you could take a 25 MHz PLL output and divide by 2 with a TFF. A
variety of options here.
Sincerely,
Greg Steinke
gregs@altera.com
Altera Corporation
Article: 67286Hi, I'm trying to configure the Spartan-3 FPGA in-system. I ported the source code that's in the application note xapp058 from Xilinx. The entry fucntion xsvfExecute is called and returns 0. But the FPGA isn't working and the clock signal we're expecting is not there. The same FPGA code is flashed into a serial flash and it works in this way. Anyone has some idea? Your help is really appreciated. AlexArticle: 67287
My design which used to work fine with ISE 4.2 is not working at all with ISE 6.2. While I debug it to figure out what went wrong, is it possible for people to download old version of ISE webpack from somewhere ? Sumit ------ http://www.c-nit.netArticle: 67288
cdufourfour@yahoo.ca (john) wrote in message > I know I can change the counters values but I don't know the out-spec > limits of the PLL such as : > -input frequency min max (out-spec) > -minimum frequency of VCO (out spec) > -Specifications of the loop-filter inside the VCO > > The altpll primitive is the same for ALTERA Stratix and Cyclone > devices. I use Cyclone FPGA and I don't know what parameters concern > Cyclone (cauz Stratix PLLs are much more parameterable) ... John, For Cyclone PLL, the input frequency limits vary by speed grade: Speed grade Min Max -6 15.625 464 -7 15.625 428 -8 15.625 387 VCO range is 500 to 1000 MHz. For more details, please see the Cyclone Handbook: Chapter 4: DC & Switching Characteristics http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf and Chapter 6: Using PLLs in Cyclone Devices http://www.altera.com/literature/hb/cyc/cyc_c51006.pdf Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 67289
In the spirit of friendly competition, I want to point out that Xilinx DCMs
have no problem whatsoever dividing 50 MHz by 4 and maintaining phase
coherence.
Please no flames...
Peter Alfke
> From: gregs@altera.com (Greg Steinke)
> Organization: http://groups.google.com
> Newsgroups: comp.arch.fpga
> Date: 9 Mar 2004 11:34:10 -0800
> Subject: Re: Using ALTPLL
>
> "SneakerNet" <nospam@nospam.org> wrote in message
> news:<Qea3c.6567$Nc3.108000@news.xtra.co.nz>...
>> Hi Subroto
>>
>> Thanks for the clarification.. This means I must have used my own code to
>> generate the 12.5MHz. Oh well back to using the logic.
>> Thanks again
>>
>> Regards
>>
>> "Subroto Datta" <sdatta@altera.com> wrote in message
>> news:41a3c.22164$cY5.21375@newssvr31.news.prodigy.com...
>>> Hi Sneakernet,
>>>
>>> You cannot implement their desired output frequency of 12.5 Mhz using the
>>> Cyclone PLL without going out of spec.
>>>
>>> The Cyclone PLL does have a minimum output frequency limit, which is a
>>> function of the PLL's minimum VCO frequency. The minimum VCO frequency is
>>> 491Mhz, and the maximum output divider counter size is 32, which results
>> in
>>> a minimum output frequency of approximately 15.3 Mhz (i.e.491/32).
>>>
>>> Page 4-31 of the device handbook gives the PLL frequency specs. The input
>>> frequency has to be between 15.625 MHz and 464 MHz for the
>>> fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the
>> slowest
>>> (-8) speed grade. See
>>> http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.
>>>
>>> - Subroto Datta
>>> Altera Corp.
>>>
>>>
>>> "SneakerNet" <nospam@nospam.org> wrote in message
>>> news:Ow43c.6282$Nc3.101499@news.xtra.co.nz...
>>>> Hello Ppl
>>>>
>>>> I have actually already asked this question before but I need help
>> again.
>>>>
>>>> I'm using a Nios Development Board (50MHz Oscillator, FPGA = Cyclone
>>>> EP1C20F400C7). I'm using Quartus II v4.0 Build 190
>>>> I need to generate a clock speed of 12.5MHz. While I have my own vhdl
>> code
>>>> that can do this, I can't use the ALTPLL to do this for me.
>>>>
>>>> How can i do this? When I try to generate a speed of 12.5MHz using
>>>> MegaFunction Wizard in Quartus it complains ('Post divider max count
>>>> exceeded')
>>>> Does this mean there is a lower limit? Is there a way to achieve this
>> speed
>>>> using ALTPLL and the above specs?
>>>>
>>>> Thanks
>>>>
>>>>
>>>
>>>
>
>
> SneakerNet,
> You can take the 50 mhz clock into a 2 bit counter and take the output
> of the MSB for 12.5 MHz. This can drive a global clock tree within the
> device to minimize skew between all registers driven by the 12.5 MHz.
> The only drawback is that you will have some skew between the 50 mhz
> and 12.5 mhz domains, so you need to be careful with data transfers
> across the domains.
>
> Or you could take a 25 MHz PLL output and divide by 2 with a TFF. A
> variety of options here.
>
> Sincerely,
> Greg Steinke
> gregs@altera.com
> Altera Corporation
Article: 67290
Hi Greg
Thanks for the contribution. I have something similar going right now.
Cheers
"Greg Steinke" <gregs@altera.com> wrote in message
news:5c1de958.0403091134.416775f3@posting.google.com...
> "SneakerNet" <nospam@nospam.org> wrote in message
news:<Qea3c.6567$Nc3.108000@news.xtra.co.nz>...
> > Hi Subroto
> >
> > Thanks for the clarification.. This means I must have used my own code
to
> > generate the 12.5MHz. Oh well back to using the logic.
> > Thanks again
> >
> > Regards
> >
> > "Subroto Datta" <sdatta@altera.com> wrote in message
> > news:41a3c.22164$cY5.21375@newssvr31.news.prodigy.com...
> > > Hi Sneakernet,
> > >
> > > You cannot implement their desired output frequency of 12.5 Mhz using
the
> > > Cyclone PLL without going out of spec.
> > >
> > > The Cyclone PLL does have a minimum output frequency limit, which is a
> > > function of the PLL's minimum VCO frequency. The minimum VCO
frequency is
> > > 491Mhz, and the maximum output divider counter size is 32, which
results
> > in
> > > a minimum output frequency of approximately 15.3 Mhz (i.e.491/32).
> > >
> > > Page 4-31 of the device handbook gives the PLL frequency specs. The
input
> > > frequency has to be between 15.625 MHz and 464 MHz for the
> > > fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the
> > slowest
> > > (-8) speed grade. See
> > > http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.
> > >
> > > - Subroto Datta
> > > Altera Corp.
> > >
> > >
> > > "SneakerNet" <nospam@nospam.org> wrote in message
> > > news:Ow43c.6282$Nc3.101499@news.xtra.co.nz...
> > > > Hello Ppl
> > > >
> > > > I have actually already asked this question before but I need help
> > again.
> > > >
> > > > I'm using a Nios Development Board (50MHz Oscillator, FPGA = Cyclone
> > > > EP1C20F400C7). I'm using Quartus II v4.0 Build 190
> > > > I need to generate a clock speed of 12.5MHz. While I have my own
vhdl
> > code
> > > > that can do this, I can't use the ALTPLL to do this for me.
> > > >
> > > > How can i do this? When I try to generate a speed of 12.5MHz using
> > > > MegaFunction Wizard in Quartus it complains ('Post divider max count
> > > > exceeded')
> > > > Does this mean there is a lower limit? Is there a way to achieve
this
> > speed
> > > > using ALTPLL and the above specs?
> > > >
> > > > Thanks
> > > >
> > > >
> > >
> > >
>
>
> SneakerNet,
> You can take the 50 mhz clock into a 2 bit counter and take the output
> of the MSB for 12.5 MHz. This can drive a global clock tree within the
> device to minimize skew between all registers driven by the 12.5 MHz.
> The only drawback is that you will have some skew between the 50 mhz
> and 12.5 mhz domains, so you need to be careful with data transfers
> across the domains.
>
> Or you could take a 25 MHz PLL output and divide by 2 with a TFF. A
> variety of options here.
>
> Sincerely,
> Greg Steinke
> gregs@altera.com
> Altera Corporation
Article: 67291Hi, In Altera's ACEX 1k family datasheet there is an absolute maximimum rating: Iout output current, per pin min = 25; max = 25 mA Does it apply only to IO pin's or as well to power/gnd pins ? If it does not applay to VCC/GND pins what are the constrains for them? I drive 16 LED's, 10mA per each. I don't know if i need any external dirver (some HC chip) or not. Best regards, PawelArticle: 67292
It seems ISE 6.2 uses one hot encoding for state machines even if I specify fsm encoding type to be user in synthesis options. This is really odd. Why would Xilinx do that ? Also How do I force FSM encoding type to be user. Sumit ------ http://www.c-nit.netArticle: 67293
john wrote: > Thanks ... > > My purpose is to implement a True Random Number Generator like Viktor > Fischer in his article "True Random Number Generator in Reconfigurable > Devices" http://www.kemt.fei.tuke.sk/publication/Drutarovsky/ches2002.pdf > . > > I know I can change the counters values but I don't know the out-spec > limits of the PLL such as : > -input frequency min max (out-spec) > -minimum frequency of VCO (out spec) > -Specifications of the loop-filter inside the VCO > > The altpll primitive is the same for ALTERA Stratix and Cyclone > devices. I use Cyclone FPGA and I don't know what parameters concern > Cyclone (cauz Stratix PLLs are much more parameterable) ... You could look at some of the spread spectrum clock generators, from companies like Cypress, or Maxim ? On these you can control the spread to some extent, and they are RC in nature, so that should help them be gaussian relative to the FPGA crystal. One real problem with an on-chip PLL that you are trying to wiggle deliberately, is it will tend to noise-lock to any comb harmonics from the digital portions - so smooth freq control is unlikely, and quasi random is the best you could expect. -jgArticle: 67294
Ray Andraka wrote:
> Peter,
>
> Consider the case where you have 1 input high to one of your luts, and 2 inputs
> high to another lut. It is clearly an illegal state, as it has two extra '1' bits,
> but it will be detected as OK by your circuit because exactly one LUT is indicating
> one input on. Each group of four requires two outputs to distinguish 0,1 or more
> than 1 input on.
I think Peter was partly correct. You can protect/correct a 16 stage
One-Hot engine against illegal states with 5 LUTs, but it will not
recover in a single clock cycle.
Simplest topology is to have 15 shifters, and #16 loads a HI ONLY if
all Prev15 are 000000000000000, if not, it simply waits until
the bogus ones ripple out.
-jg
>
> Peter Alfke wrote:
>
>
>>Eh, what? Unfortunately anonymos...
>>
>>Each first level LUTs detects (output High) that exactly one of its inputs
>>is High.
>>The second tier LUT detects that exactly one of the first-tier LUT outputs
>>is high, which mans that there is exactly one High input.
>>Agreed ?
>>Peter Alfke
>>
>>
>>>From: user@domain.invalid
>>>Newsgroups: comp.arch.fpga
>>>Date: Tue, 09 Mar 2004 05:24:26 GMT
>>>Subject: Re: Release asynchrounous resets synchronously
>>>
>>>Peter Alfke wrote:
>>>
>>>>LUTs are very efficient "illegal state" detectors.
>>>>Let's say you have a 16-state one-hot machine. Four LUTs can each detect
>>>>"exactly one of my inputs is High", and a fifth LUT does the same with the
>>>>four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it
>>>>from there...
>>>
>>>Eh, what? So the first tier LUT compute f, where
>>>f(a,b,c,d) = 1 iff a+b+c+d = 1, else 0.
>>>For the 5th LUT we have the same property that a legal 16-state would
>>>map exactly one of the four first tier LUTs to 1, thus it sounds like
>>>what you have in mind is something like this:
>>>
>>>f({f(s[3:0]), f(s[7:4]), f(s[11:8]), f(s[15:12])})
>>>
>>>but this could accept states like 16'b1111_1110_1100_0001.
>>>
>>>I don't see how you can detect legal states with only five four-input LUTs.
>>>
>>>
>>>Peter, the FPGA reset question has come many times. What does Xilinx
>>>recommend in general? Async-reset+Sync-release, all-sync, or all-async?
>>>Which uses fewest resources?
>>>
>>>Thanks,
>>>
>>>Tommy
>>>
>
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
>
>
Article: 67295I have been going nuts with a Spartan 2 and 18v04 during configuration with a JTAG cable (III) and impact 6.1. 1. The mode pins are set for boundary scan. 2. If I run the cable with a 5v reference: a. Chain initialization will succeed 99% of the time. b. EPROM programming/verify will succeed 95% of the time. c. FPGA programming/verify will fail verify 100% of the time and the FPGA is left with what appears to be wrong IOB configuration; starts drawing a great deal of power. d. If I run IDCODE looping, it will fail before my defined 1000 loops are completed. 3. If I run the cable with 3.3v reference (which it should be anyway), I cannot get through the Chain initialization 100% of the time. I get up to 10 unknown devices reported. I have pulled out a previously designed board and reprogrammed it without any problems, to verify the software/drivers/cables. I have checked for noise on the power and JTAG lines, didn't find anything alarming. If anyone has any suggestions, your input would be GREATLY appreciated. Thanks!Article: 67296
Here is the URL for my evaluation of metastability in Virtex-II Pro flip-flops: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?multPartNum=1&sTechX_ID=p a_metastability Peter Alfke, Xilinx Applications ============================ > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Mon, 08 Mar 2004 18:10:44 +1300 > Subject: lattice metastable info > > I see lattice have just posted a Metastable document. > > I recall Peter A. made some Virtex measurements, but > looking back at the Xilinx web, I can only find the venerable XAPP 096. > - is there anything more up to date / based on newer silicon ? > > -jg >Article: 67297
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > If you are using a Xilinx, the V2/V2Pro bitfile encryption is a VERY > high barrier for an attacker to cross: I'd comfortably protect a $10K > secret, and uncomfortably protect a $100K secret from a malicious, > capable adversary. I'd expect the cost of extracting a valid decrypted bitstream from the part to be even higher than that. You have to do it without losing the backup power to the part long enough for cells to change state. This makes a lot of the otherwise promising avenues of attack difficult if not impossible. For instance, you're not likely to be able to decap the part and microprobe it. (Microprobing probably wouldn't work anyhow, as the signals you need for bistream extraction are likely below metal.) It is more likely that a successful attack would result from some sort of "social engineering", and even the fanciest protection features built into the FPGA aren't going to protect from that.Article: 67298
it seems your professor is fooling you...i guess designing a decent FPGA chip will require a big team of engineers and top of the line Cadence & Mentor softwares...be prepared to pay hundreds of thousands US$ for the licenses alone...besides, it seems u r from a Chinese university... Tong <nospam@cuhk.edu.hk> wrote in message news:c2km7a$ko9$1@justice.itsc.cuhk.edu.hk... > hi all, > > I am a undergraduate studying VLSI and Magic manul layout. My professor have > asked us to design an FPGA chip using Magic. > I am confused in how to build the switch box and look up table. Could anyone > kindly recommend some website or books that gives detail explanation on > these stuff. > > Thanks a lot. > > Regards, > Tong > >Article: 67299
On Tue, 09 Mar 2004 15:14:41 +0100, Magnus Danielson <magda@netinsight.net> wrote: >Cheers, >Magnus - who defeated the SDH/SONET scrambler with a customized ping! OOOhhhh! What protocol was running over the SONET? Was it POS? Allan.
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