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hayhoe@nortelnetworks.com (Brent A. Hayhoe) writes:
> >2. The EAB in the 20KE has a content addressable memory mode. This is very useful
> >for sorting and searching. If your DSP application would benefit from this
> >capability, this may tip the scales in favor of the 20KE
>
> Agreed again, althoug Xilinx have inferred that they have a CAM solution, but I don't
> know anything more than that.
Do anyone know what kind of size you can get with the CAM?
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 16701Just wanted to say: Very Nice Web Sight Steven K. Knapp <sknapp@optimagic.com> wrote in message news:7j60l6$2u0@dfw-ixnews3.ix.netcom.com... > Visit the web's largest independent on-line information source for > programmable logic, The Programmable Logic Jump Station. > > * FREE downloadable FPGA and CPLD design software > * Information on devices, boards, books, consultants, etc. > * FAQ plus tutorials on VHDL and Verilog > > > http://www.optimagic.com/index.shtml > > > > Featuring: > --------- > > > --- FREE Development Software --- > > > Free and Low-Cost Software - http://www.optimagic.com/lowcost.shtml > Free, downloadable demos and evaluation versions from all the major > suppliers. > > > --- Frequently-Asked Questions (FAQ) --- > > > Programmable Logic FAQ - http://www.optimagic.com/faq.html > A great resource for designers new to programmable logic. > > > > --- FPGAs, CPLDs, FPICs, etc. --- > > > Recent Developments - http://www.optimagic.com/index.shtml > Find out the latest news about programmable logic. > > > Device Vendors - http://www.optimagic.com/companies.html > FPGA, CPLD, SPLD, and FPIC manufacturers. > > > Device Summary - http://www.optimagic.com/summary.html > Who makes what and where to find out more. > > > Market Statistics - http://www.optimagic.com/market.html > Total high-density programmable logic sales and market share. > > > > --- Development Software --- > > > Design Software - http://www.optimagic.com/software.html > Find the right tool for building your programmable logic design. > > > Synthesis Tutorials - http://www.optimagic.com/tutorials.html > How to use VHDL or Verilog. > > > > --- Related Topics --- > > > FPGA Boards - http://www.optimagic.com/boards.html > See the latest FPGA boards and reconfigurable computers. > > > Design Consultants - http://www.optimagic.com/consultants.html > Find a programmable logic expert in your area of the world. > > > Research Groups - http://www.optimagic.com/research.html > The latest developments from universities, industry, and > government R&D facilities covering FPGA and CPLD devices, > applications, and reconfigurable computing. > > > News Groups - http://www.optimagic.com/newsgroups.html > Information on useful newsgroups. > > > Related Conferences - http://www.optimagic.com/conferences.html > Conferences and seminars on programmable logic. > > > Information Search - http://www.optimagic.com/search.html > Pre-built queries for popular search engines plus other > information resources. > > > The Programmable Logic Bookstore - http://www.optimagic.com/books.html > Books on programmable logic, VHDL, and Verilog. Most can be > ordered on-line, in association with Amazon.com > > > > . . . and much, much more. > > > Bookmark it today! > > > ANN: The Industry's Largest Independent Information Source of FPGAs and > CPLDs (www.optimagic.com) > >Article: 16702
BOIN´s Semiconductor Linkpage has been updated. You can find now more than 1450 semiconductor related links. Please visit http://www.boin-gmbh.com/linkpage/linkpage.htm If you would like to add a link please send the URL, the name of the company and the name of the category to: webmaster@boin-gmbh.com. If your company would like to advertise on Boin´s Semiconductor Linkpage please send an e-mail to: info@boin-gmbh.com. If you have any ideas or suggestions how to improve the website or if you want to suggest new categories contact: webmaster@boin-gmbh.com. Download your FREE Evaluation Copy of WAFERMAP for Win95/ NT at http://www.boin-gmbh.com!Article: 16703
Here is a sample of what you can do...
-- Assume say a 1Mhz clock then 100 clock ticks would be 100 us.
constant ONE_HUN_US_DELAY : integer := 100;
...
if rst = 1 then
-- initilaze
fsm <= s0;
elsif (clk'event and clk='1') then
fsm <= next_state;
end if;
...
case fsm is
when s0 =>
counter1 := ONE_HUN_US_DELAY;
next_state <= s1;
when s1 =>
counter1 := counter1 - 1;
if (counter1 = 0) then
next_state <= s3;
end if;
when s3 =>
-- etc etc etc...
...
Hope this is what you were looking for.
Jarek Patrzalek <patrzal@natlab.research.philips.com> wrote in message
news:3753A570.B370ACA8@natlab.research.philips.com...
>
> I am a beginner in VHDL coding and I would like to place
> a fixed delay in my (synchronous) finite state machine,
> but I do not want to use "external" counter or to implement
> a certain number of "idle" states in FSM.
> Is it possible (and reasonable) to use a kind of iteration
> scheme ("for" loop) within FSM state(s)?
>
> Jarek
Article: 16704All, I have generated several RAMs using Coregen and instantiated them in my design. I used a .coe file to define initial values and use the .mif file Coregen generates to initialize the RAM during RTL simulation. All of that works fine. My question is, how do these initial values get put into the actual design, i.e. how are they incorporated in the bit stream used to program the FPGA. The initial values are not (I don't think) in the edif file coregen creates. Do I have to put something in the .ucf or .ncf file to define these initial values? If so, what is the syntax? Or, do I have to add this during synthesis using some attribute? I want to put a different value in every location of the RAM. Again, in simulation with the .mif file, it works fine. Please advise. TMArticle: 16705
Jonathan Feifarek <feifarek@removethis.ieee.org> wrote: : Tim Tyler wrote: :> I would like to see *reversible* FPGAs, composed of large numbers of :> Fredkin gates - or equivalent reversible logic. [...] : My first time to across this term. After a quick search, I came across : this site [ http://www.vxm.com/21R.30.html ] which (after discussing : bacteria as switching devices) makes this statement: : "The question then becomes how to commercially build this Fredkin : device. It may be possible to create it out of semiconductor materials, : but Toffolli thinks that a Fredkin gate would be 'very tough to : implement in silicon.'" Fredkin gates are very simple: Three inupts, three outputs, LUT: \ I I I O O O +-------+-------+ | 0 0 0 | 0 0 0 | | 0 0 1 | 0 0 1 | | 0 1 0 | 0 1 0 | | 0 1 1 | 1 0 1 | | 1 0 0 | 1 0 0 | | 1 0 1 | 0 1 1 | | 1 1 0 | 1 1 0 | | 1 1 1 | 1 1 1 | +-------+-------+ The same number of bits are always set in the inputs and the outputs. Bits are just copied from the input to the respectibe output, except when the third input is set in which case the first two inputs are "swapped around" on their way through. No information is created or destroyed by such a gate - in contrast to say an AND or OR gate - which typically translates information directly into heat. There is no difficulty in implementing this type of gate in any sort of hardware - but the 'trick' is ensuring that the "logical" lack of need for any sort of power supply or heat dissipation structures actually translates in practice into low power consumption and low heat generation characteristics. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Small change can often be found under seat cushions.Article: 16706
John McCluskey <J.McCluskey@ieee.org> wrote: : It seems that destroying information requires energy, and making the : computation reversible permits (in principle) performing a computation at : zero energy cost. This is correct. Presumably the second law of thermodynamics will rear its ugly head and mean that any physical implementation can only approach this state. However if using reversible logic, an approach can at least be made. Todays irreversible boolean gates will mean that large thermal sinks are required to stop termal noise from swamping the computation. "Heat" and "power" should be modelled as an information process within the device rather than translated into actual thermal noise and then vacuumed away. : The fly in the ointment, or course, is that zero energy computations take : an infinite amount of time to compute, since they randomly reverse as : much as they go forward. The more energy you put into the computation, : the faster you can make it go. I have not encountered this notion before. I am not sure of it's physical basis. I have certainly never heard of the "random reversing" issue. The main benefit of reversibility is that no energy loss is necessarily involved in actually performing the calculations - of course the signals themselves will still need a physical basis and their initial creation (or, in practice, their observation) will still need to consume some power. As far as I know something which is the computational equivalent of superconductivity remains theoretically possible; indeed, superconductivity provides a positive example of how a physical process might approach the limit of requiring very little in the way of a power supply. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com The more I learn about people, the more I like my cat.Article: 16707
The initial values do indeed get passed through the edif file using the INIT property. If the initial values are all zero for a particular LUT, then the INIT property is not placed on that LUT. If it is missing, then the default of all zeros is used. You can see the initial values if you generate a RAM component using a COE initial values file. After generating it, go into the edif file with a text editor and do a search on the string "INIT". You will find lines similar to " (property INIT (string "0f03c0f0"))" which correspond to the initial values in the COE file. Tom McLaughlin wrote: > All, > I have generated several RAMs using Coregen and instantiated them in my > design. I used a .coe file to define initial values and use the .mif > file Coregen generates to initialize the RAM during RTL simulation. All > of that works fine. > > My question is, how do these initial values get put into the actual > design, i.e. how are they incorporated in the bit stream used to program > the FPGA. The initial values are not (I don't think) in the edif file > coregen creates. Do I have to put something in the .ucf or .ncf file to > define these initial values? If so, what is the syntax? Or, do I have > to add this during synthesis using some attribute? I want to put a > different value in every location of the RAM. Again, in simulation with > the .mif file, it works fine. > > Please advise. > TM -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16708
You could always use Leonardo to read in the Altera EDIF and then retarget
towards Xilinx.
I use this quite a lot when I need a quick (but slightly dirty conversion)
Regards,
David Hawke.
Xilinx.
Bill Gates wrote in message <7j69in$9nf$1@tourist.gnt.net>...
>Unfortunately the EDIF that Max+plus gave you uses parts available for the
>particular
>chip family that was selected by the Max tools and the Xilinx part you want
>to use
>does not have the same parts (i.e. AND1 for instance). If you get this to
>actually work
>I would be amazed.
>
>If you have the original VHDL code (that is if you didnt use Max's AHDL or
>some
>schematic entry) then I would use that instead by either compiling it in
>Xilinx or some
>"better" tool like leonardo or synplicity.
>
>Good luck... maybe someone else has a suggestion as to how to edit the edif
>file
>or something to that nature.
>
>
>Vitolo <setel@mx3.redestb.es> wrote in message
>news:7j0s18$h9b29@SGI3651ef0...
>> Hi, all:
>>
>> I need convert a ALTERA design(MAX+PLUSII) into a XILINX design
>(Foundation
>> F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist into
>> Schematic Editor of Foundation. I complet the design with the new
>component
>> (IBUF, OBUF, pads) and save. When i try export the netlist in a XNF file,
>> ihave a error message ("Missing AND1 model or library error") then i
>export
>> in a VHD file and have ("Cannot read pin descriptors for AND1") error.
>>
>> I want to generate a VHDL file (XILINX Foundation compatible) from a EDIF
>> ,or other, ALTERA file. How i can to do?
>>
>>
>>
>
>
Article: 16709
Registration is Open and Call for Papers - 1999 MAPLD International
Conference
September 28-30, 1999
Kossiakoff Conference Center
The Johns Hopkins University- Applied Physics Laboratory
Laurel, Maryland
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Registration.html
The 2nd annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address
devices, technologies, usage, reliability, fault tolerance,
radiation susceptibility, and applications of programmable devices
and adaptive computing systems in military and aerospace systems.
The program will consist of oral and poster technical presentations
and industrial exhibits. This international conference is open to US
and foreign participation and is unclassified. There will be one
classified session at the secret level, for U.S. citizens only. For
additional conference information, please see Programmable
Technologies Web Site (http://rk.gsfc.nasa.gov).
Abstracts are being solicited in all aspects of the use of programmable
elements, devices, and systems for military and aerospace applications.
These include: PALs, FPGAs, PROMs, Programmable Substrates, FPIC,
Programmable Analog Circuits, adaptive computing systems and related
technologies.
Topics include (but are not limited to) the following:
- System on a Chip
- Advanced Devices, Technologies, and Software and Their Impact on
Critical System Reliability
- Programmable Technologies and State-of-the-Art Devices and
Programmable Elements
- Adaptive Computing Systems
- Evolvable Hardware
- Radiation Effects, Device Reliability and Element Characteristics
- Device Architecture, Performance, and Capabilities
- Applications and Novel Techniques for Military and Spaceflight
Circuits.
- Use of COTS Devices in the Military and Spaceflight Environment
- Testing and Analysis Techniques
- Software Tools for Design/Analysis - HDLs, Synthesis, and
Intellectual Property
- Advanced Packaging including Known-Good-Die, MCMs, and chip-scale
packaging.
The conference is sponsored by:
- NASA/GSFC
- JHU/Applied Physics Laboratory
- NSA
- NASA Radiation Effects Program
- Military & Aerospace Programmable Logic Users Group
- American Institute of Aeronautics and Astronautics
For more information see http://rk.gsfc.nasa.gov or contact:
Richard Katz
NASA
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Alan W. Hunsberger
NSA
awhunsb@afterlife.ncsc.mil
Tel: (301) 688-0245
Ann Garrison Darrin
JHU/APL
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Abstracts should be approximately 2 pages long and are due June 11,
1999. Please send abstracts to maplug@pop700.gsfc.nasa.gov.
Include first author information (name, affiliation, phone number,
and email address) and whether an open or classified presentation
is desired. If you can not submit an unclassified abstract, please
contact Al Hunsberger.
Industrial exhibit reservations should be sent to
maplug@pop700.gsfc.nasa.gov and should include company name and
contact information (name, phone and email).
------------------------------------------------------------------
MAPLD 99 Program
Military and Aerospace Applications of Programmable Devices and
Technologies Conference
Welcome
Rich Katz - NASA Goddard Space Flight Center
Dr. Stamatios Krimigis - Head, Space Department
Johns Hopkins University/Applied Physics Lab
Technical Sessions:
I. Military & Aerospace Applications
Session Chair: Marty Fraeman - JHU/APL
Invited Speaker: Dr. Ralph McNutt - JHU/APL
"Space Exploration Beyond 2020"
II. Devices, Elements, and Technologies
Session Chair: Rich Katz - NASA Goddard Space Flight Center
Invited Speaker: John McCollum - Actel Corp.
"Programmable Elements and Their Impact on FPGA Architecture,
Performance and Radiation Hardness"
III. Radiation Environments and Effects
Session Chair: Ken LaBel - NASA Goddard Space Flight Center
Invited Speaker: Rich Katz - NASA GSFC
"FPGAs in Space Environment and Design Techniques"
IV. Adaptive Computing
Session Chair: John McHenry - National Security Agency
Invited Speaker: Brad Hutchings - Brigham Young University
"Configurable Computing: Past, Present and Future"
V. SoC, Synthesis, and IP
Session Chair: Hans Tiggeler - University of Surrey, UK
Invited Speaker: Sandi Habinc - ESA
"Designing Space Applications Using Synthesizable Cores"
VI. Classified Session
Session Chair: Al Hunsberger - National Security Agency
Invited Speaker: Mark Dunham and Michael Caffrey - DOE/Los
Alamos
National Labs
Gigasample SIGINT & IMINT Processing via Reconfigurable
Computing
VII. Poster Session
Session Chair: Christina Gorsky - SGT, Inc.
Dinner Speaker (Tuesday Evening)
Dr. Don DeVoe, University of Maryland at College Park
"Micro Electro Mechanical Systems (MEMS)"
Panel Session: (Wednesday Evening)
"Architecture, Technologies and Design Methodologies for 2005
and Beyond"
Panel Moderator: Ann Garrison Darrin - JHU/APL
---------------------------------------------------
Technical Committee
===================
Ray Andraka - The Andraka Group
Neil Bergmann - Queensland University of Tech, Australia
Ben Cohen - Hughes Aircraft/Raytheon
Lew Cohn - Defense Threat Reduction Agency
Marco Figueiredo - SGT, Inc.
Marty Fraeman - JHU/Applied Physics Lab
Ann Garrison Darrin - JHU/Applied Physics Lab
Creigh Gordon - Air Force Research Lab/VSSE
Christina Gorsky - SGT, Inc.
Al Hunsberger - National Security Agency
Brad Hutchings - Brigham Young University
Richard B. Katz - NASA GSFC
Ralph Kohler - Air Force Research Laboratory
Ken LaBel - NASA GSFC
John McHenry - National Security Agency
Robert Reed - NASA GSFC
Michael Regula - Dornier Satellitensysteme GmbH
Frank R. Stott - Jet Propulsion Laboratory
Hans Tiggeler - University of Surrey, UK
Tanya Vladimirova - University of Surrey, UK
Article: 16711
andi_carmon@my-deja.com wrote:
>
> Regarding this issue, I need an advice on the following :
> The 'accept' call of the server is blocking by default. It will not
> return until a connection is available. I know that it is possible to
> define the socket as non-blocking. Can you advise me how? Actually I
> want to achieve the effect of the server 'visiting' the socket and if
> there is no connection of the client to let it continue.
Andi,
You didn't mention what platform/OS you're running on, but in general
there are two ways to approach this:
(1) you can issue an fcntl() on the socket file descriptor (i.e. the
fd you
got from socket()). You'll probably want to do a F_SETFL with
O_NDELAY
or O_NONBLOCK. Check the docs for your platform.
or
(2) you can "poll" the fd using poll() or select() (which one depends
on your
platform). You'll want to check for read availability (i.e. if
the call says
the fd is ready for read operations, you can then do an accept
on it and it
won't block).
Hope this helps,
--Bob
--
Bob Beckwith
To reply, remove NOSPAM. from the email address above.
Article: 16713Well. frankly, I can't say enough bad things about Data I/O. I was using the 3000 series programmers for EPC1's and they were absolutely horrendous. They took about 8 minutes to read the source file and 5 minutes to program the device. They couldn't give you a checksum until after the successfully programmed a device (as opposed to giving you a checksum on the source file before programming). They would fail the devices about 20% of the time (and the devices were toast after that). These problems existed with our Engineering programmer and our Production programmer. We eventually switched to the Altera programmer to enhance yields and throughput. This was great. They gave checksums immediately (confirming the right source file). They read the source file and programmed the device in about 30 seconds. They never toasted a device. I'm now with a different company and using different chips. The story is still the same, Data I/O programmers are causing us no end of grief. They seemed to have let a market monopoly go to their heads. One good thing was that Altera gave me credit for the bad EPC1's. In my opinion all the problems were Data I/Os. Regards, Steve Nicolas Matringe wrote in message <37567CD3.CCDB6285@dot.com.fr>... >We have two lots of EPC1 PROMs, one we can program and one we cannot. >Would it be because of a change in the programmation algorithm made by >Altera without notice (I know the PROM makers often do that) ? Or maybe >the lot is defective? > >Maybe an older version of the ChipWriter would do with the old EPC1 ? > >Any help is welcome (we don't want to throw 30 EPC1 away like that) > >Nicolas MATRINGE DotCom S.A. >Conception electronique 16 rue du Moulin des Bruyeres >Tel 00 33 1 46 67 51 11 92400 COURBEVOIE >Fax 00 33 1 46 67 51 01 FRANCE >Mail reply : remove one dot from my addressArticle: 16714
Hi all, I'm running the Xilinx M1.5 tools under WinNT on a fast machine with loads of memory. Whenenever the compile gets to the "par" stage the machine response to anything else slows to an almost complete stop. It is possible to go into WinNT's Task Manager and lower the priority of the par task and everything works OK. It doesn't even noticably slow compile times. So, my question is, is there someway to lower the par task priority from the command line? Using the Task Manager every time I run par is a pain. Cheers, Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 16715
Hello. I prepare a communication chip design project. the communication chip functions SDLC, Bus interfacing, queuing. I anticipate it will need about 40,000 ~ 50,000 gate. FPGA design will be preceded. but final product should be low cost. I am thinking Custum IC is one of them What can I do in order to convert FPGA design to Custum IC design What do I need .. or is there another method to be low cost help me! email to hayy@naracontrols.co.krArticle: 16716
ds12 wrote: > Hello, > > I am trying implement a very low level design on Virtex. > I want to use the MULT_AND and LUT components in my design. > > At the moment I can do it in schematics but I can't do it in VHDL. > The LUT is removed and then the MULT_AND doesn't work. > > Can anyone help? > > Dimitris > -- > Dimitrios Siganos <d.siganos@ic.ac.uk> > Dept. of Computing, Imperial College, London SW7 2BZ > Work Tel: 0171 589 5111 ext 58439, Home Tel: 0181 446 8841 > Homepage: www.doc.ic.ac.uk/~ds12 Hello Which software do you use for the synthesis? What are the error message? Do you respect the name and the I/O name of the macro when you instantiate them? Good luck. Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16717
Erik de Castro Lopo wrote: > > Hi all, > > I'm running the Xilinx M1.5 tools under WinNT on a fast > machine with loads of memory. Whenenever the compile gets > to the "par" stage the machine response to anything else > slows to an almost complete stop. > > It is possible to go into WinNT's Task Manager and lower > the priority of the par task and everything works OK. It > doesn't even noticably slow compile times. > > So, my question is, is there someway to lower the par task > priority from the command line? Using the Task Manager every > time I run par is a pain. > I don't know if you can change priority from the command line, but you can start a task with priority like this: start /priority program.exe where priority is: low, high, idle etc. and program.exe what ever program you want to start --L2C --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be, june 30th 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 16718
Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote: > Do anyone know what kind of size you can get with the [Altera Apex] CAM? Each EAB can be 32 words of 32 bits each. There are many EABs per chip. Although this is still not well documented, here's my understanding of how it works: The CAM is an 32-word array of 32-bit product terms. It takes 2 cycles to write a 32-bit product term. It takes 1 (or 2?) extra cycles to write a mask. (Each bit can match a 0,1, or x. If you want the x, you have to write a mask term.) To read, you present a 32-bit query pattern which may match one or more of the product terms. There is a simple 32-to-5 encoder to tell you which term matched. The encoder doesn't work if more than 1 term matches. In this case, you can read out all 32 "match" flags and supply your own encoder. It takes 2 cycles to read all 32 match flags. It would be nice to be able to clear the memory in a single cycle, however it looks like you have to explicitly clear unused cells. It would be nice to be able to read the matching pattern. Typically with a CAM, you want some pattern bits and some corresponding data bits. For the Apex implementation, you will have to use the 5-bit address to look up the data field in a separate memory.Article: 16719
Ray, Thanks for the help. I was making an, uhhh, user error. All is well. Tom Ray Andraka wrote: > The initial values do indeed get passed through the edif file using the INIT > property. If the initial values are all zero for a particular LUT, then the > INIT property is not placed on that LUT. If it is missing, then the default > of all zeros is used. You can see the initial values if you generate a RAM > component using a COE initial values file. After generating it, go into the > edif file with a text editor and do a search on the string "INIT". You will > find lines similar to " (property INIT (string "0f03c0f0"))" which > correspond to the initial values in the COE file. >Article: 16720
Ray, Thanks for the help. I did find the INIT property in the edif file, but they were all set to zero! I have a .coe file with initial values and Coregen generated the .mif file for simulation with the correct initial values, but they are not in the edif file generated at the same time. Any suggestions??? By the way, I am generating a single port RAM for Virtex using Coregen v1.5.2. Any help would be appreciated. Regards, Tom Ray Andraka wrote: > The initial values do indeed get passed through the edif file using the INIT > property. If the initial values are all zero for a particular LUT, then the > INIT property is not placed on that LUT. If it is missing, then the default > of all zeros is used. You can see the initial values if you generate a RAM > component using a COE initial values file. After generating it, go into the > edif file with a text editor and do a search on the string "INIT". You will > find lines similar to " (property INIT (string "0f03c0f0"))" which > correspond to the initial values in the COE file. >Article: 16721
Jonathan Feifarek wrote: > > "news.pcnet.com" wrote: > > > > I was thinking about putting up a page devoted to new engineers entering the > > FPGA market. > > ...Other than the differences between CPLD/FPGA, the > > programming, vendors, languages (VHDL or simple ABEL), what other things > > would be appropriate for this type of page? > > It would useful to describe typical applications of FPGA (general > prototyping, high speed reconfiguration, custom computers, etc.), as > well the technology areas (networks, DSP, graphics, computation). Of > course, discussion of the tools is a must, along with related topics > like mapping, floorplanning, placement, and routing. > > Much knowledge is based on hands-on experience, so up-to-date > information written by FPGA users would be helpful (perhaps some of it > gleaned from newsgroups like this if there are no copyright issues). To > make it interesting, add stories about unusual or novel applications, > "gotchas" to watch out for, or trends in the industry (this will also > attract veterans). This area is more for early users rather than > complete novices, and may be outside your scope. > > Lastly, I would recommend lots of links. The http://www.optimagic.com > site does an excellent job of this. I agree with all of these recommendations. With respect to simpler issues like "the difference between a CPLD and an FPGA" and a brief overview of typical applications, take a look at this article from the latest issue of Embedded Systems Programming. http://www.netrino.com/Articles/ProgrammableLogic/ It's written primarily for the software engineer who's new to FPGAs in general. So it doesn't get into more detailed topics. But it might be worth a look and/or a link before you write your own stuff. Cheers, Michael BarrArticle: 16722
Hello, Where can I find a symbol (Xilinx FPGA XC4013E) in Viewlogic? I use Powerview 6.1 but we have also the workview office CD's (for windows NT) Many thanksArticle: 16723
Your question is not clear. If you looking for a symbol for a XC4013E for use in a higher level schematic such as a PCB design, you will have to create it your self, as it will be unique, with your signal names and pin assignments. If you are looking for the symbol library, for doing a design that will end up in a XC4013E, then the library (on a PC install) is located in the directory: x:\xilinx\viewlog\data\xc4000e Viewlogic also ships this library, but the install of Workview office does not install it. It is on the second CD, the libraries CD. It is to be found at: y:\vendor\xilinx\\unified\xc4000e Note that these libraries are not identical. The Xilinx one appears to be more recent (maybe some bug fixes?) Philip Freidin In article <37580781.BBA8CEF3@alcatel.be> Jan Vermaete <jan.vermaete@alcatel.be> writes: >Hello, > >Where can I find a symbol (Xilinx FPGA XC4013E) in Viewlogic? >I use Powerview 6.1 but we have also the workview office CD's (for >windows NT) > >Many thanks > > >Article: 16724
Since Philip obviously has other things on his mind, I thought I'd mention a fine product from a little company named Fliptronics that offers a VERY extensive set of Viewlogic schematic symbols for Xilinx parts. I believe this is the URL: http://www.fliptronics.com/cae_products.html I also hear it is VERY reasonably priced too! ;-) Philip Freidin <fliptron@netcom.com> wrote in article <fliptronFCtFKM.LM7@netcom.com>... > > Your question is not clear. If you looking for a symbol for a XC4013E > for use in a higher level schematic such as a PCB design, you will have > to create it your self, as it will be unique, with your signal names and > pin assignments. > > If you are looking for the symbol library, for doing a design that will > end up in a XC4013E, then the library (on a PC install) is located in > the directory: > x:\xilinx\viewlog\data\xc4000e > > Viewlogic also ships this library, but the install of Workview office > does not install it. It is on the second CD, the libraries CD. It is > to be found at: > y:\vendor\xilinx\\unified\xc4000e > > Note that these libraries are not identical. The Xilinx one appears to be > more recent (maybe some bug fixes?) > > Philip Freidin > > > In article <37580781.BBA8CEF3@alcatel.be> Jan Vermaete <jan.vermaete@alcatel.be> writes: > >Hello, > > > >Where can I find a symbol (Xilinx FPGA XC4013E) in Viewlogic? > >I use Powerview 6.1 but we have also the workview office CD's (for > >windows NT) > > > >Many thanks > > > > > > > > >
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