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Peter, (How long have you been there? I recall talking to you back in the 80's. Have always welcomed your comments!) The 24c04 is a serial eeprom with an I2C interface. There is no reset, but I realize now that the fact that both SCL and SDA are going to drift high during the power-up sequence, there is NO chance to give a start command to the eeprom. A start is the sequence SDA going from low to high with SCL high. Might have it reversed. Anyway, I think I am covered. Thanks. Jim . Peter Alfke wrote: > > New User wrote: > > > Any lessons learned on power up sequence with 24c04. > > This sounds like a familiar problem when the design blindly > relies on FPGA ( what's a 24c04?) and EPROM properly waking > up together. Murphy does not sleep!That's why I always > recommend keeping the SPROM reset as long as possible, e.g. > by driving its RESET from the INITbar output of the (Xilinx) > FPGA. That method is 100% safe. > > Peter Alfke, Xilinx ApplicationsArticle: 15151
Sounds like a fun project ... not familiar with the Instruction Set Architecture ... can it be pipelined ?Article: 15152
-------------------------------------------------------------------------
Second and Final Call for Participation
Ph.D Forum at DAC '99
Submission Deadline: March 15, 1999.
http://www.cs.washington.edu/homes/soha/forum
-------------------------------------------------------------------------
Goals:
The Ph. D. forum provides a structured way of increasing interaction
between academia and industry. The forum's immediate goals are to
provide graduate students with feedback on their thesis work from
other researchers, and to give CAD and system companies a chance to
preview academic work-in-progress.
Format:
** Submission: Students within one or two years of completing their Ph.D.
submit a one-page abstract of their thesis, along with a
university-approved thesis proposal or a published
paper. (Deadline March 15, 1999)
Electronic submission only. Visit the web site for details.
http://www.cs.washington.edu/homes/soha/forum
** Review: The submission will be reviewed to ensure that the abstract
is supported via the accompanying paper/proposal.
** Awards: Some travel grants and DAC registrations will be awarded to
participating students -- provided they do not receive any DAC
financial assistance. (Notification April 30, 1999)
** Poster Session: Students will present their work during a poster
session hosted by SIGDA during their member meeting --
Tuesday, June 22, 7:00 - 9:00 p.m.
Background:
The first Ph.D. forum in design automation was held during DAC 1998. Nine
students (7 from the U.S. and 2 from Europe) participated. The poster
session was a positive experience for all. The students' feedback included
the following comments:
"It was a truly positive experience. I got a lot of constructive
criticism and feedback".
In response if the participant would recommend it to a friend,
"Absolutely, especially if the friend had passed his or her
candidacy exam and was half-way through the work. I think this is the
time in a Ph.D. when attending the forum would be most useful."
"It [the forum] was extremely useful and I got some interesting
and encouraging feedback. I also had a great time being
there....It's a good place to get encouragement and direction for
future work."
More Information:
For more information, visit the web site:
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or send inquiries to:
Soha Hassoun, soha@eecs.tufts.edu, or to
Olivier Coudert, coudert@mondes.com
Article: 15153Fred, Here are some things you might try: Assuming that the current design was fairly successful as far as timing margin goes... 1) You could lock the current pinout in the ".ucf" file. 2) Use the floorplanner to observe where critical logic such as data path registers, counters, adders, ram etc were placed. 3) Use the floorplanner to fix the placement of all or some of these. 4) Rerun the mapper with the -fp option using the floorplan file that the floorplanner generates. 5) Run multi-pass place and route until you have a sample of PAR's. 6) Choose the one that has the best timing score for final delay and cleanup PAR using that cost table. This should work as long as the design and pinout that the previous designer settled on had some breathing room. I use Synplicity and it has been my experience that the many of the items in #2 above often don't change names unless they are part of the circuit that is undergoing "minor" logic changes. Even if they do, the placement of their structures is what is important. I have found that it is not necessary to fix the entire design but only small portions of it to produce nicely repeatable results for a specific pinout after minor logic changes. Admittedly, this technique may work better for some designs than others. I can think of a few. If the original design had very little margin with any cost table then your job is probably tougher. You could in this case lock the pinout in the ".ucf" file (I assume you are trying to avoid a re-spin of the board.). Then, using your knowledge of the design, try to floorplan the items I mention above in a way that attempts to capitalize on the current pinout. Follow that with multi-pass PAR's. Iteratively use trce and epic to find out where the timing is broke and make subtle (or drastic) changes until you get successful results from the multi-pass PAR. The key here is doing a little floorplanning. The floorplanning can be done using the Xilinx floorplanner or done manually in the ".ucf". The tools produce "fairly" repeatable results if you help them a little. Best of luck, Matt Bielstein Fred Ganong wrote in message <36E58918.C34D0BCD@erols.com>... >I have inherited a design for a xilinx chiip that uses VHDL and about a >one page schematic using Xilinx's foundation tool. I am looking for a >way to "lock" in the current design as far as place and route to keep >the timing constraints constant during a couple of minor logic changes. >Unfortuantely Foundations option to use a previous design as a "guide" >for the current design appears to re-place and re-route about half the >clb's. Does anyone know of a way to keep the place and route from a >previous design from changing short of using the EPIC design editor? > >Article: 15154
Please, can somebody tell me where to find any FAQ abot fpga's? Thanxs.Article: 15155
Dear everbody I would like to seek for a fast 16-bit random number generator using VHDL or verilog or just logic gate drawing. Do you have any idea? Thanks. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15156
I'm not good at this subject. Pleas describe me what it is Look Up Table. Thank you.Article: 15157
Has anyone had any experience using the Virtex development board from Nallatech? I have heard from several people that the boards are quite good, I was hoping for any further comments on pro's, con's nice features of the board before I start to consider buying them. Any advice would be much appreciated Cheers Daryl BradleyArticle: 15158
Attachment contains many random number generators.
Article about that VHDL source code you can find on http://www.zemris.fer.hr/~gsc/Publications.html
Regards, Goran.
--
gsc@ieee.org
http://www.zemris.fer.hr/~gsc/
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end
Article: 15159You can find a FAQ on programmable logic on The Programmable Logic Jump Station at http://www.optimagic.com/faq.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Eci User wrote in message <01be6ad2$c2f0f400$ef26ea93@pc-iosi.ecitele.com>... >Please, can somebody tell me where to find any FAQ abot fpga's? >Thanxs.Article: 15160
Hi, leslie.yip@asmpt.com wrote: > Dear everbody > > I would like to seek for a fast 16-bit random number generator using VHDL or > verilog or just logic gate drawing. Do you have any idea? You may use LFSRs (linear feedback shift-register) to generate a pseudo random sequence. The Xilinx application note XAPP 052 contains some information on how to build an appropriate LFSR. Further, if memory serves me right then the "Vector Pipeline Library" written by John McCluskey includes some VHDL source for LFSRs (http://www.lucent.ca/fpga/). If the random number generator does not have to be synthezisable then check out Part 1, Section 4.9 of the FAQ (http://www.vhdl.org/comp.lang.vhdl/). -- EdwinArticle: 15161
Thanks, I'll keep you posted. Fred Ganong wrote: > I have inherited a design for a xilinx chiip that uses VHDL and about a > one page schematic using Xilinx's foundation tool. I am looking for a > way to "lock" in the current design as far as place and route to keep > the timing constraints constant during a couple of minor logic changes. > Unfortuantely Foundations option to use a previous design as a "guide" > for the current design appears to re-place and re-route about half the > clb's. Does anyone know of a way to keep the place and route from a > previous design from changing short of using the EPIC design editor?Article: 15162
EXTENDED DEADLINE: March 15, 1999 ======================================================================== Call for Papers: ---------------- Technical Session: Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) ------------------------------------------------------------------ http://www.cs.rdg.ac.uk/cs/research/pedal/events/pdpta.html of The 1999 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'99): http://www.cps.udayton.edu/~pan/pdpta/. June 28 -- July 1, 1999 Monte Carlo Resort, Las Vegas, Nevada, USA There has been a growing interest in using reconfigurable computing platform (FPGAs) for the design of application-specific computer systems (e.g. for multimedia application) as well as particular dedicated systems (e.g. for specific tasks in computer vision and signal processing). An important issue is the development of hardware/software codesign methodology that provides the designer with flexible tools for mapping different algorithms into FPGAs. The mapping methodology must take into account different parameters: * problem parameters (size of problem) * real-time parameters (latency, throughput rate) * hardware parameters (structural properties, scalability) and provide reconfigurable and parametrizable objects. There are different approaches for describing and representing algorithms and for mapping them onto reconfigurable hardware environment, for example: * logical specification and refinement * polytope model and systolic arrays * dataflow models This technical session focuses on the methods to provide reconfigurable objects for reconfigurable computing, i.e. finding hardware parameters that meet the real-time and problem parameters. We are also interested in applications and implementations, that demonstrate the systematic way to develop hardware/software objects with the emphasis on parametrizability end reconfigurability. Possible applications of interest include, but are not limited to: * signal and image processing * multimedia * long arithmetic * image databases * object recognition * navigation of robots Important dates: ---------------- March 15, 1999: Draft papers (about 4 pages) April 5, 1999: Notification of acceptance May 1, 1999: Camera-Ready papers June 28 - July 1, 1999: Conference and Technical Session Prospective authors are invited to submit three copies of their draft paper to Toomas P. Plaks by the due date. E-mail submissions in Postscript format viewable and printable with ghostview are also acceptable. Session Chairs: --------------- Dr. Toomas P Plaks Department of Computer Science The University of Reading P.O. Box 225 Reading RG6 6AY Engalnd, UK email: T.Plaks@reading.ac.uk Tel.: +44 (0) 118 987 5123 ext 7633 Fax:: +44 (0) 118 975 1994 Prof. Graham. M. Megson Department of Computer Science The University of Reading P.O. Box 225 Reading RG6 6AY Engalnd, UK email: G.M.Megson@reading.ac.uk Tel.: +44 (0) 118 931 8600 Fax:: +44 (0) 118 975 1994Article: 15163
Hi!
--
New User <defaultuser@domain.com> ...
> Any lessons learned on power up sequence with 24c04.
> Initially there might be some activity on the SCL SDA lines as master
> and eeprom power up. I suppose one might accidently give a start to
> the eeprom.
> But, the eeprom has warm up time, so maybe it would ignore anyway.
> If the master did give a bogus start... some time later the master
> would give a real start. Hmm. Would the eeprom be responsive?
> I guess the eeprom would be hanging looking for address?
> (the state machine internal to the eeprom.)
> Any hints?
> Thanks.
> Jim
See on the Microchip (www.microchip.com) - Serial EEPROM Application Notes.
AN572: Questions and Answers Concerning Serial EEPROMs.
And also on the Atmel (www.atmel.com)
Quoting from datasheet of AT24CS128/256
==\
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by following
these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
==/
Bye!
Kuznetsov Dmitry, Moscow, http://www.orc.ru/~dkuzn/index.htm
Alias http://attend.to/dkuzn
Article: 15164Rafal Kielbik wrote: > I'm not good at this subject. > Pleas describe me what it is Look Up Table. > Look-up table (LUT) is another word for a ROM ( read-only memory) with n address lines and a single output. n is usually 4, sometimes 3 or 2.,. It is also called a function generator because it can generate any function of the n inputs. Peter Alfke, Xilinx.Article: 15165
This is a multi-part message in MIME format. --------------E840CA14F9640D17B088418C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit FYI Virtual Computer Corp. along with Xilinx distributor Insight Electronics announce 'The Virtual Workbench'.... a Virtex based stand alone development board. The Virtual Workbench is designed to provide a working platform for testing and evaluating the Virtex Fanmily of FPGAs.... to see more details go to http://www.vcc.com/VW.html -- Best Regards, John Schewel, VP Marketing & Sales Virtual Computer Corp. http://www.vcc.com --------------E840CA14F9640D17B088418C Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John Schewel Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John Schewel n: Schewel;John org: Virtual Computer Corporation adr: 6925 Canby Ave. #103;;;Reseda;CA;91335;USA email;internet: jas@vcc.com title: VP Marketing & Sales tel;work: +1 (818) 342-8294 tel;fax: +1 (818) 342-0240 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------E840CA14F9640D17B088418C--Article: 15166
Peter Alfke ha scritto nel messaggio <36E58A10.8F4821C9@xilinx.com>... > [..] >The LUT is built pretty much like a conventional ROM, with >16 latches, read out by a tree-structure reducing the 16 >inputs to one output. The decoding is done with pass >transistors. Therefore we can claim that there never is a >glitch when you change only one address input. And there >also is no glitch when you change two address lines more or >less simultaneously if - and only if - all four address >combinations generate the same output. >I get that question quite often > >Peter Alfke, Xilinx Applications > Dear Peter, That "only if" is a surprise for me. For example, we have this function out = (a XOR b XOR c) AND d When d=0, I tought the out is ALWAYS 0, wathever occours to the inputs a b c. You say instead that in these conditions the out might have glitches ? LuigiArticle: 15167
I'm looking at using some Actel FPGA's . . . you know the anti-fuse variety. It seems the ..SX16 family is quick and definitely inexpensive on a gate per gate basis vs. other vendors. My question is, has anybody used these yet, and what general pros and cons do you see. I'd still consider using an SRAM based part from say Altera (FLEX10K series) if needed. Are there any penalties (besides OTP) that this architecture has? Any help would be great gene ggli@dictaphone.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15168
--------------4E9E9685C4422D63DEAB471D Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Infidels Invited, Heathens Highly Welcome ! This March and April, Xilinx will conduct a world-wide series of Applications Symposia, describing new CPLD and FPGA solutions and Cores. I was responsible for coordinating and partly creating the content, so believe me, the emphasis is on application solutions and system design, not on marketing. The presentations will be given by experienced Field Applications Engineers. I will assist in Germany and Sweden, my old stomping grounds. We will describe parts and solutions that you can buy and use today, no vaporware here. We invite all Altera and Actel advocates, Lucent and Lattice lovers, Vantis fans, and especially ASIC aficionados, as well as frustrated fence-sitters. As a minimum, you will learn what you are missing. For a list of times and locations, click on http://www.xilinx.com/company/seminar99.htm I hope this commercial message has not offended any sensitive souls. We are on a teaching crusade, almost in line with comp.arch.fpga Peter Alfke, Xilinx Applications --------------4E9E9685C4422D63DEAB471D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> <H2> Infidels Invited, Heathens Highly Welcome !</H2> <P>This March and April, Xilinx will conduct a world-wide series of Applications Symposia, describing new CPLD and FPGA solutions and Cores. I was responsible for coordinating and partly creating the content, so believe me, the emphasis is on application solutions and system design, not on marketing. <P>The presentations will be given by experienced Field Applications Engineers. I will assist in Germany and Sweden, my old stomping grounds. We will describe parts and solutions that you can buy and use today, no vaporware here. <P>We invite all Altera and Actel advocates, Lucent and Lattice lovers, Vantis fans, and especially ASIC aficionados, as well as frustrated fence-sitters. As a minimum, you will learn what you are missing. For a list of times and locations, click on <P><U><A HREF="http://www.xilinx.com/company/seminar99.htm">http://www.xilinx.com/company/seminar99.htm</A></U> <BR> <P>I hope this commercial message has not offended any sensitive souls. <BR>We are on a teaching crusade, almost in line with comp.arch.fpga <P>Peter Alfke, Xilinx Applications </BODY> </HTML> --------------4E9E9685C4422D63DEAB471D--Article: 15169
Wiggo, Aren't the Lucent devices with hardcoded PCI interface logic fairly pricey? I do like the idea of a hardcoded PCI logic and programmable logic in one device. Regards, Bob Wiggo Olufsen wrote in message <36E1AC76.3043025F@online.no>... >Bob, > >Lucent has released FPGA's with embedded hard-coded PCI-cores in addition to the >programmable array. You find them on http://www.lucent.com/micro/fpga/ . > >Wiggo. >Article: 15170
Austin, Thanks for the info. Similar to what you have stated, I have heard that the 4000 series Xilinx parts are easier to use than the Spartan series for a PCI implementation because of their more robust routing resources. And, the 4000 parts are more costly. Regards, Bob Austin Franklin wrote in message <01be69bc$e48879b0$207079c0@drt1>... ><snip> >> : Generally, are how much tweaking with placement and timing constraints >is >> : required for the current crop of cores? > >My experience has only been with Xilinx. > >Things are certainly better than they were in the past. Basically, parts >are now much faster, by at least 2x, over a few years ago, so implementing >any PCI design (target/master/burst), and making timing isn't as big a feat >as it was a few years ago....BUT... > >If you want to run in as inexpensive a part as you can, then you will have >to do more placement and logic mapping than you would if you ran in a >faster/more expensive part, and did less work on the placement/logic >mapping. In either case, you need to make a good set of timing constraints >for the placer/router to use...and you will probably make timing with >minimal floor planning in the faster parts. > >In any PCI design, the PCI design is usually only half the job. The other >half is the back end interface, so don't underestimate that amount of >work... I feel $5k is a bargain for the PCI core...given how much work it >is to do it in the first place. That's really only 2 weeks of engineering >$$ at best. > >You can probably even get away with using some HDL to do this design, if >you use a fast enough part ;-) I always found using schematics for PCI >interfaces has been a much better design methodology because I have much >better control over the placement and logic mapping than an HDL. I would >like to believe that will change in a year or so....but if you want to run >in the cheapest part you can, then I would strongly suggest the design be >done in schematics. If cost is not a primary concern, than an HDL may >suffice. > >Austin Franklin >austin@darkroom.com >Article: 15171
Our client is a world leader in communication. They are looking for a > ASIC Verification Contractor to work a 3-6 month contract in the Silicon > Valley. They are working on an ASIC for a new router product. They will > pay $90 / hr. This position will start as soon as possible. So respond > now!! > > The ideal candidate will have: > - ASIC Verification experience > - Verilog experience > - PCI interface related knowledge > > Helpful but not necessary are: > - Good Networking environment experience > - VERA > - Good C knowledge] 408, IC OK, $80-$90/hr, ASIC Verification Engineer, > Verilog, PCI > > Patrick > ======================== > The Trattner Network > A Norrell Information Services Company > ======================== > > Patrick Lowney > plowney@tratnet.com > Phone: 925-280-2122 > > http://www.tratnet.com > 500 Ygnacio Valley Road, Suite 225 > Walnut Creek, CA 94596 > Resume Fax: 650-949-1026 > Business Fax: 925-280-2100 > >Article: 15172
Check out QuickLogic. They have devices with built-in PCI interfaces + memory + field-programmable gates. I don't know the particulars on the amount of RAM or gates. They also provide templates for NT/95 drivers. I've been using QuickLogic parts for several years - they have superior tools and support. Their parts' only drawbacks are one-time programmability. Nick Steffen Bob Bauman <bbauman@lynxstudio.com> wrote in article <7bppqe$qlv$1@birch.prod.itd.earthlink.net>... > Hi all, > > About a year and a half ago I was considering implementing a PCI interface > in an FPGA. At that time I decided that the design was going to be very time > consuming and posed compatibility risks. Altera's and Xilinx's cores seemed > to require quite a bit of tweaking and they were expensive.Article: 15173
Dear Kuznetsov Dmitry, Yes, the part can get reset in this manner. Since I am designing an ASIC I have no specification to cause a situation of 'interuption in protocol.' All of the operations the ASIC performs are graceful. Power up is no-man's land in terms of gates and/or firmware. But, givne that the start condition seems to be defined with some thought of power up in mind, I think that power up will not cause a problem with eeprom. I may add suspenders if I have silicon and time. You just never know. Jim Kuznetsov Dmitry wrote: > > Hi! > -- > New User <defaultuser@domain.com> ... > > Any lessons learned on power up sequence with 24c04. > > Initially there might be some activity on the SCL SDA lines as master > > and eeprom power up. I suppose one might accidently give a start to > > the eeprom. > > But, the eeprom has warm up time, so maybe it would ignore anyway. > > If the master did give a bogus start... some time later the master > > would give a real start. Hmm. Would the eeprom be responsive? > > I guess the eeprom would be hanging looking for address? > > (the state machine internal to the eeprom.) > > Any hints? > > Thanks. > > Jim > > See on the Microchip (www.microchip.com) - Serial EEPROM Application Notes. > AN572: Questions and Answers Concerning Serial EEPROMs. > > And also on the Atmel (www.atmel.com) > Quoting from datasheet of AT24CS128/256 > ==\ > MEMORY RESET: After an interruption in protocol, power > loss or system reset, any 2-wire part can be reset by following > these steps: (a) Clock up to 9 cycles, (b) look for SDA > high in each cycle while SCL is high and then (c) create a > start condition as SDA is high. > ==/ > > Bye! > Kuznetsov Dmitry, Moscow, http://www.orc.ru/~dkuzn/index.htm > Alias http://attend.to/dkuznArticle: 15174
Depends on which 4000 series family. The Spartan's routing resource is like the 4000E. the EX, XL, XLA, XV have more routing resources than the 4000E and the Spartan. So yes, if you are talking about one of the newer 4000 families (one with an X in the suffix) that is true. If you are talking about an early 4000 family such as the original 4000, 4000A, 4000H or 4000E then the spartan has equivalent or better routing. Bob Bauman wrote: > Austin, > > Thanks for the info. Similar to what you have stated, I have heard that the > 4000 series Xilinx parts are easier to use than the Spartan series for a PCI > implementation because of their more robust routing resources. And, the 4000 > parts are more costly. > > R-- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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