Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Patrick Hibbs <phibbs@ti.com> wrote: > What's wrong with a robust asynchronous fifo??? Possible.. at 350 MHz though? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36076
MOst of the FIR filters I have dealt with have been more than 14 taps
(these are FPGA applications). You might look at the papers available on
my website, particularly at "FPGAs Make a Radar Signal Processor on a Chip
a Reality" which uses a 256 tap complex coefficient FIR for a matched
filter and a 64 tap FIR in the demodulator.
finish wrote:
> hello,
>
> I am looking for a real-application FIR of more than 14 taps,
> symmetric or no it does not matter. This is typically for comparaison
> purposes .
>
> The target is FPGA
>
> thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36077
Peter,
A synchronous counter can get pretty wide if you are using a master clock of
100+ MHx. The complaint that precipitated this discussion was that the poor
guy had a counter with 20+ bits that wasn't synthesizing well (a different
problem) and was not meeting speeed. I pointed out that an LFSR makes an
excellent prescaler that only takes a very small number of CLBs and whose
performance is limited by the SRL16 minimum pulse width rather than the prop
delay through the carry chain. I was not advocating a preload value (this
adds more complexity than I intended), rather I suggested accepting the
native modulus of the LFSR (2^(n-1)) and then using that as a tick pulse for
a much lower rate and smaller counter. I tried to illustrate that such a
prescaler was extremely compact and as fast as the FPGA could reasonably
perform even for a preposterous count length of 2^64 clocks. Personally, I
wouldn't bother presetting one, rather I'd take a native length that was
short enough to meet my needs. I've used this in things like a watchdog
tmer where the time interval was measured in seconds and the FPGA clock was
>100 MHx. Just another tool in the toolbox, not a cure for cancer.
Peter Alfke wrote:
> I think this discussion has gone too abstract.
> What is a reasonable max counter length?
> 64 bits, 80 bits, 100 bits, 140 bits?
>
> Who wants to count 100 MHz until the universe has frozen over a thousand
> times?
> There has to be some reason for all this. LFSRs are great as random
> number generators. Detecting zero is reasonably easy, but adds junk. So
> does arbitrary presetting...
> The conventional binary ripple-carry structure supported in good FPGAs
> is sufficiently compact and fast for all but the most exotic purposes.
>
> Peter Alfke
>
> glen herrmannsfeldt wrote:
>
> > Ray Andraka <ray@andraka.com> writes:
> >
> > >How long is *really long* ? As I pointed out, 1 CLB worth of LFSRs
> > >gets you a period of over 2000 years with a 100 MHz clock.
> > >The single LFSR actually gets more efficient as you increase its
> > >length, since the termnal count only grows at log2(N) and the LFSR
> > >grows at a little less than 1/17 that rate. Cascading 2 identical
> > >LFSRs gets you the same effect as doubling the length of a single
> > >LFSR, so it is more expensive. Cascading different lenght LFSRs,
> > >however may give you better granularity in your selection of period.
> >
> > Well, I said really really long.
> >
> > I don't know Virtex so well, so I don't know which mode you use
> > to do this. Does it include the feedback taps in that one CLB?
> > Can you select any feedback taps that you want?
> >
> > So you have a 64 bit LFSR to count your 2000 years, and need
> > a 6 bit counter to count the 64 successive zeroes. The suggestion
> > was to use a LFSR counter to count those zeroes, though, yes,
> > there might be better ways to count to 64.
> >
> > As you mention, two LFSR's with different periods could be run
> > in parallel and then detect the simultaneous zero of the two.
> > With only one more CLB you could get a 128 bit counter, and count
> > for 3e22 years.
> >
> > How many CLB's does it take to make a complete LFSR counter?
> > (Inlcuding the preset ROM and load logic for arbitrary counts?)
> >
> > -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36078Try http://www.nallatech.com/products/dime.htm They might have something in line with what you are seeking. There are others. They just come to mind. Good luck! Matt "#BASUKI ENDAH PRIYANTO#" <PH892987@ntu.edu.sg> wrote in message news:8D5C8824989A21458FFF1C3CE9902036058AF144@mail12.main.ntu.edu.sg... > Hi, > > Currently, I am looking for Xilinx Virtex 2 or Virtex E evaluation > board. Basically, ,my requirement is the FPGA which has at least 3 > Million System gate. > > Anybody can help me ? > > Thanks ! > > Basuki >Article: 36079
Good Morning, I've designed a QPSK modulator with variable rates so I've three set of 42 coefficients for the SRRC filter, one set for each rate, my question is what is the best way to implement it in VHDL for a virtex XCV1000 in particular I need a block where I give the 2 bit signal named rate_sel and obtain at the output an array named SRRC_coeffs of 42 coefficients each one with 12 bits. My problem is that I now how to declare this type inside an architecture with TYPE but I need to have this type available also at the output of the block 'cause I've to send it to the SRRC block. I hope to have explain well, thanks for your interest. AntonioArticle: 36080
"AME" <AME3141592@yahoo.com> ha scritto nel messaggio news:9r5jh401vui@enews1.newsguy.com... > > In retrospect, the reason I wasn't able to learn HDL two years ago was > > not only because the books I read weren't that interesting > > A list of good (practical, real-world) books that might be recommended for a > HDL newbie with extensive "real" digital circuit design? > About learning VHDL... I'd like to share my experience, and suggest a title or two. I'm a newbie too, in HDL and FPGA design, too (but with a solid backgorund in digital design and a good working knowledge of many comp. languages). I used Xilinx Foundation 3.1i for a simple video project, now I moved to ISE. I wanted to "play" with a new design, learning VHDL during that. I followed this "track", and I'm really satisfied, now. In fact, I enjoyed a lot, learning VHDL. I read a bit around, and choose a text, to begin with: "Essential VHDL, RTL Synthesis Done Right", di S. Rajan, ISBN 0-9669590-0-0 I found it very very readable. Almost "enjoyable" :-) It explain in a very clear way what does the compiler infers when you use a particular language construct. Yes, you can find this information on the compiler's vendor manual. But I like the way this book handles the subject, without a particular compiler in mind (I'm still jumping back and forth from FPGA Express to XST, for various reasons). The Ashenden book... many suggests it's the ultimate Bible. I didn't buy it by now; too deep for a newbie, I think. Too big the risk to get lost. Maybe the student version ? I downloaded the online version from his site, but it's a bit old. I'll buy Ashenden too, but not now. I'm not ready :-) Then I played with the compiler, investigating a lot of variants of my new design. Doing this, I "grasped" a bit of experience about compiler nuances, messages, and so on. I quickly discovered how fast I could switch from an architecture to another completely different. Just some pages of code to write. Doing that on schematics would have required half a day. Now, a week later, I have an almost working "proof of concept" prototype, and learned quite a bit during the time. I could have done it in schematics: perhaps now I could have done a bit more... but right now I have a VHDL design that I can customize with very little effort to different bus widths, memory space and so on. I'll go on studying VHDL reading also the compiler's manuals. Now I want to learn the language's features that help in testing. I took "Writing Testbenches - Functional verification of HDL models" - Janick Bergeron. Still flipping through pages, though. I have not an opinion, now. To summarize.... I was skeptical to use VHDL in this new design: too much hassle, too little time, no clear reward... But, frankly speaking... I'm happy I did! So... stop whining :-), take your next idea, take a book, a compiler and start playing around. It's really worthwile!Article: 36081
i am getting this error once i tried to lauch the foundation automation caused exception, exit code 80080005 server execution failed XIE uinternal error 01 xilinx claims that i have to install NT SP3, i have windows 95, i tried, but i have even succeded to install it any help pleaseArticle: 36082
Hi Have a look at http://www.8052.com or http://www.8052.com/search.phtml?MSGFORUM=TRUE&FULLSEARCH=TRUE&TYPE=ALLTERMS&TERMS=timing Maybe You have luck trying the above pages, but what exactly are You looking for ? The 8051 timing depends on the instruction, the clock-frequency and the type of controller You are using. The instructions use one, two or four clock-cycles. Now regarding the clock-frequency. For most of the 8051's the clock is divided by 12 to get one cycle, i.e. if You have a "one cycle instruction" it will take 12 clock-cycles to complete the instruction. When using a Dallas ds87c820 the cycle-time may be set to 4 clock-cycles and when using the latest ds89c420, the fastest until now, the clock-cycle is one. So You see that the timing may be quite difficult to state as there are so many different types. best regards Ivar NordingArticle: 36083
Kevin Brace wrote: > Thanks to everyone who replied to the posting I made. > Here are more details I will like to throw in. > Looking at Xilinx IP Evaluation license, does this evaluation license > stop someone from cloning Xilinx's IP cores? > > http://www.xilinx.com/ipcenter/ipevaluation/ipevaluation_license.htm > > ************************* (C) Xilinx ******************************* > Xilinx IP Evaluation License Agreement > > Xilinx Evaluation IP is owned and controlled by Xilinx and > must be used solely for design, simulation, implementation and > creation of design files limited to Xilinx devices or technologies. > Use with non-Xilinx devices or technologies is expressly prohibited > and immediately terminates your license. This violates the "principle of first sale" in the US and the "Erschöpfungsgrundsatz" in germany. When I buy a product the vendor looses all control over how I use the product. > Xilinx products are not intended for use in life support appliances, > devices, or systems. > Use in such applications are expressly prohibited > ******************************************************************** > > Let's say that someone sign up for their IP evaluation, and use > Xilinx's technical documents like user's guide, design guide, and > reference design contained inside the evaluation zip file from Xilinx > to derive that person's original, but compatible implementation. > After someone is done cloning the IP core, release it to the public > (of course, without the files that came with the IP evaluation, > because I don't have the right to redistribute it) as a synthesizable > vendor neutral HDL implementation with constraint files for multiple > vendors' devices. > Since that work was derived from the original evaluation version of > the IP core, will that person have the right to implement it with any > vendor's device? It is derived from the documentation, not from the IP core. Usually IP cores are not shipped with source code and as long as you do not do any reverse engineering on the netlist you can hardly violate any copyright on the IP core implementation. On the other hand the new (not cloned!) IP core does usually not contain anything from the documentation so you also do not violate any copyright on the documentation. You might however violate patents. Even if your core is not compatible and not derived from the original one. This does not apply to PCI and many other open standards. Complication comes with open source software. If essentially the whole community knows the original source code then the original vendor will allways claim that you derive your core from theire work. Even if you didn't. > Again, the method used here design that person's original > implementation compatible with the original will be: > > 1) Studying the bus protocol listed in the user guide, design guide, > or reference design > > 2) Entering waveform stimulus into the evaluation IP core, and analyze > how it behaves > > 3) Attach a user module that tests the evaluation IP core, and analyze > how it behaves > > 4) Study third party literature (IEEE, trade groups, or books related > that can be purchased at a book store) > > 5) Will not reverse engineer the netlist or any encrypted design > information (i.e., convert the netlist to gate-level symbols. Sort of > like disassembler software VCommunications used to have (maybe they > still have) that spit out .ASM file from .EXE file which can be > assembled again). > > The thing I guess I am trying to describe here is that is it possible > to clone Xilinx's IP core or any other IP core in a way Cyrix cloned > Intel's x86 implementation? > I guess the main point is, that building something that does the same as someone elses product is not cloning. You have a patent violation if you implement it the same way as it is stated in the patent, idependently of whether you did reverse engineering or whatever. You have a copyright violation if you use part of the original source code, netlist or bitstream in you own implementation. The license agreements are legaly worthless to a large extend. Especially if all information you need can be obtained without licensing the original core. (E.g. I do not need any Xilinx documentation to build a PCI to CoreConnect interface.) IANAL, Kolja SulimmaArticle: 36084
> 2. Some texts explain clock recovery for NRZ data, How should I > process IQ data to put in a suitable form? The following book is excellent in all the synchronization (phase, timing, frequency) issues: Meyr, Moenaclaey, Fechtel, "Digital Communication Receivers: Synchronization, Channel Estimation and Signal Processing", WileyArticle: 36085
Hi! I am a student at the Vienna University of Technology (Austria) studying electrical engineering. I want to build a small Digital Sampling Oscilloscope, connected via USB (Cypress EZ-USB chip) to the PC. Therefore I have a few little basic questions, because I am not familiar with FPGA, CPLDs, VHDL, Verilog, ... My design consists of 3 major parts: CPU, Memory and Inputs. These have to be connected. As I found some very amazing fast memories with e.g. 256kx36 I want to use all of that width. 3 AD-Convertes with 10 bits each (MAX4148) at 80MHz. The 6 bits left will be digital inputs. So, I thought of a big part in the middle (perhaps FPGA or CPLD or PAL or GAL) which: - routes the 36 bit data from the inputs to the memory during sampling - has the clock divider (80MHz crystal) must be divided downto 40kHz (or 4kHz, not yet fixed) - does the triggering (because it already has the digitized input data in real time) - calculates addresses for the RAM. I want cyclic adressing the whole RAM to be able to look at the signal before the trigger occoured. As soon as the trigger happens, the current memory address has to be stored.. When a certian (by the CPU specified) amount of samples is written in the RAM, sampling has to stop and an interrupt for the CPU has to be generated. - the CPU wants to see the big "logic part" as a FIFO and simply applies the "FRD" (fast read) strobes, and gets 8 bit one after another. 5 cycles per sample (5x8=40, so 4 bits extra). In this stage the "logic part" has to route the memory to the CPU (mulitplexed) - as soon as the CPU starts to read out the data after the interrupt, the stored address has to be used and an offset (positive or negative) added to it. This is the start address for the read out. - all these functions have to be adjustable by the CPU. I'd like an I2C like interface for that, but anything else which doesn't use too much wires is ok too. Could you please tell me, if a CPLD or an FPGA is a good choice for the job of that "big central logic part"? What is the difference between a CPLD and an FPGA? Is VHDL and Verilog a propper design language to implement such a problem for such a logic device? Which one is more suitable? Which logic device would you recommend? Producer/Type Where can I find software to design this device? I don't need a very comfortable software. I would prefere one for Linux. Is it possible to program the logic device without one of these very expensive commecial programmers? In system programming would be a nice thing. Could you please recommend a good book or better an URL in the internet where I can find basics of logic devices and VHDL and Verilog? Thanks for you help! Bye HansiArticle: 36086
Hi Kolja, I'm not a lawyer, so I can't say for sure... But I think the Xilinx IP Evaluation License Agreement means that Xilinx retains ownership of the IP and is licensing it, not selling it, to whoever happens to download the evaluation. I believe the same is true of the full-featured product. That's my personal opinion, Eric Crabill Kolja Sulimma wrote: > > ************************* (C) Xilinx ******************************* > > Xilinx IP Evaluation License Agreement > > > > Xilinx Evaluation IP is owned and controlled by Xilinx and > > must be used solely for design, simulation, implementation and > > creation of design files limited to Xilinx devices or technologies. > > Use with non-Xilinx devices or technologies is expressly prohibited > > and immediately terminates your license. > > This violates the "principle of first sale" in the US and the > "Erschöpfungsgrundsatz" in germany. When I buy a product the > vendor looses all control over how I use the product.Article: 36087
I'll try to be more precise, I need to implement a SRRC filter for
different rate, here there is the code to supply the right
coefficients
to the filter depending on which data rate is operating.
The problem is that for an XCV1000-4 BG560 the result of
the mapper is the following :
Xilinx Mapping Report File for Design 'coeffs_selector'
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Design Information
------------------
Command Line : map -p V1000-BG560-4 -cm area -gm exact -k 4 -c 100
-tx off
coeffs_selector.ngd
Target Device : xv1000
Target Package : bg560
Target Speed : -4
Mapper Version : virtex -- D.27
Mapped Date : Sun Oct 28 16:15:44 2001
Design Summary
--------------
Number of errors: 1
Number of warnings: 1
Number of Slices: 2 out of 12,288 1%
Number of Slices containing
unrelated logic: 0 out of 2 0%
Number of 4 input LUTs: 3 out of 24,576 1%
Number of bonded IOBs: 506 out of 404 125%
Total equivalent gate count for design: 18
Additional JTAG gate count for IOBs: 24,288
How I can arrange the things in a different way to use well the FPGA
???
Following there is the package SRRC_coeffs and the file
coeffs_selector.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
package SRRC_coeffs is
subtype coeff is std_logic_vector(11 downto 0);
type coeffs is array(1 to 42) of coeff;
end SRRC_coeffs ;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use work.SRRC_coeffs.all;
entity coeffs_selector is
port( coeffs_sel : in std_logic_vector( 1 downto 0);
coeffs_SRRC : out coeffs
);
end coeffs_selector;
architecture coeffs_selector_arch of coeffs_selector is
-- calcolati con rcosine di matlab e non scalati
Constant coeffs_SRRCx3 : coeffs := coeffs'(
coeff'("111111100010") , -- 1
coeff'("111111111100") , -- 2
coeff'("000001000001") , -- 3
coeff'("000001000100") , -- 4
coeff'("111110111001") , -- 5
coeff'("111100100110") , -- 6
coeff'("111110011100") , -- 7
coeff'("000110001100") , -- 8
coeff'("001111110110") , -- 9
coeff'("010100001111") , -- 10
coeff'("001111110110") , -- 11
coeff'("000110001100") , -- 12
coeff'("111110011100") , -- 13
coeff'("111100100110") , -- 14
coeff'("111110111001") , -- 15
coeff'("000001000100") , -- 16
coeff'("000001000001") , -- 17
coeff'("111111111100") , -- 18
coeff'("111111100010") , -- 19
coeff'("000000000000") , -- 20
coeff'("000000000000") , -- 21
coeff'("000000000000") , -- 22
coeff'("000000000000") , -- 23
coeff'("000000000000") , -- 24
coeff'("000000000000") , -- 25
coeff'("000000000000") , -- 26
coeff'("000000000000") , -- 27
coeff'("000000000000") , -- 28
coeff'("000000000000") , -- 29
coeff'("000000000000") , -- 30
coeff'("000000000000") , -- 31
coeff'("000000000000") , -- 32
coeff'("000000000000") , -- 33
coeff'("000000000000") , -- 34
coeff'("000000000000") , -- 35
coeff'("000000000000") , -- 36
coeff'("000000000000") , -- 37
coeff'("000000000000") , -- 38
coeff'("000000000000") , -- 39
coeff'("000000000000") , -- 40
coeff'("000000000000") , -- 41
coeff'("000000000000")); -- 42
-- calcolati con rcosine di matlab e non scalati
Constant coeffs_SRRCx4 : coeffs := coeffs'(
coeff'("111111100110") , -- 1
coeff'("111111110001") , -- 2
coeff'("000000011010") , -- 3
coeff'("000001000011") , -- 4
coeff'("000000111010") , -- 5
coeff'("111111101001") , -- 6
coeff'("111101110110") , -- 7
coeff'("111100111111") , -- 8
coeff'("111110101001") , -- 9
coeff'("000011010100") , -- 10
coeff'("001001101110") , -- 11
coeff'("001111010100") , -- 12
coeff'("010001100010") , -- 13
coeff'("001111010100") , -- 14
coeff'("001001101110") , -- 15
coeff'("000011010100") , -- 16
coeff'("111110101001") , -- 17
coeff'("111100111111") , -- 18
coeff'("111101110110") , -- 19
coeff'("111111101001") , -- 20
coeff'("000000111010") , -- 21
coeff'("000001000011") , -- 22
coeff'("000000011010") , -- 23
coeff'("111111110001") , -- 24
coeff'("111111100110") , -- 25
coeff'("000000000000") , -- 26
coeff'("000000000000") , -- 27
coeff'("000000000000") , -- 28
coeff'("000000000000") , -- 29
coeff'("000000000000") , -- 30
coeff'("000000000000") , -- 31
coeff'("000000000000") , -- 32
coeff'("000000000000") , -- 33
coeff'("000000000000") , -- 34
coeff'("000000000000") , -- 35
coeff'("000000000000") , -- 36
coeff'("000000000000") , -- 37
coeff'("000000000000") , -- 38
coeff'("000000000000") , -- 39
coeff'("000000000000") , -- 40
coeff'("000000000000") , -- 41
coeff'("000000000000")); -- 42
-- calcolati con systolix e scalati
Constant coeffs_SRRCx6 : coeffs := coeffs'(
coeff'("000000000110") , -- 1
coeff'("111111110011") , -- 2
coeff'("111111100010") , -- 3
coeff'("111111011110") , -- 4
coeff'("111111101100") , -- 5
coeff'("000000001101") , -- 6
coeff'("000000110111") , -- 7
coeff'("000001011000") , -- 8
coeff'("000001011011") , -- 9
coeff'("000000110011") , -- 10
coeff'("111111100010") , -- 11
coeff'("111101111100") , -- 12
coeff'("111100100011") , -- 13
coeff'("111100000011") , -- 14
coeff'("111101000011") , -- 15
coeff'("111111110111") , -- 16
coeff'("000100010101") , -- 17
coeff'("001001110111") , -- 18
coeff'("001111011101") , -- 19
coeff'("010100000010") , -- 20
coeff'("010110100110") , -- 21
coeff'("010110100110") , -- 22
coeff'("010100000010") , -- 23
coeff'("001111011101") , -- 24
coeff'("001001110111") , -- 25
coeff'("000100010101") , -- 26
coeff'("111111110111") , -- 27
coeff'("111101000011") , -- 28
coeff'("111100000011") , -- 29
coeff'("111100100011") , -- 30
coeff'("111101111100") , -- 31
coeff'("111111100010") , -- 32
coeff'("000000110011") , -- 33
coeff'("000001011011") , -- 34
coeff'("000001011000") , -- 35
coeff'("000000110111") , -- 36
coeff'("000000001101") , -- 37
coeff'("111111101100") , -- 38
coeff'("111111011110") , -- 39
coeff'("111111100010") , -- 40
coeff'("111111110011") , -- 41
coeff'("000000000110")); -- 42
begin
with coeffs_sel select
coeffs_SRRC <= coeffs_SRRCx3 when "00",
coeffs_SRRCx4 when "01",
coeffs_SRRCx6 when "10",
coeffs_SRRCx6 when others ;
end coeffs_selector_arch;
Thanks for your answer...
Antonio D'Ottavio
Article: 36088Ray Andraka <ray@andraka.com> writes: > DaveG wrote: > > > I would like to simulate digital video or image stills to an FPGA > > design using Altera MAX+plus II software. My plan is to convert a > > graphics file like a bitmap into a *.vec vector waveform file. > > Can anyone tell me if this has been done before? And does anyone > > know a simple graphics file format that will be easy to extract > > the image data? I need it in 8-bit RGB format. (24-bits total). > > Thanks. > I've used a program called Scion Image to convert various image > formats to ascii text files that can be easily read by VHDL > I wrote a PGM reading package, and used Paintshop Pro to convert my images to the ASCII format of PGM. I've also used that as the output of my testbench so i can see the image resulting in PSP. Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 36089
Hi, i have two divices in chain. First EPM7064SLC and than EPC2LC. With MAX+plus II i can program the JTAG Chain. It works fine. Then i create jam files (*.JAM or *.JBI) with MAX+plus II. With JAM.EXE (Version 2.2) or (JBI.EXE version 2.1) the "Exit code = 0... SUCCSESS", but the divices a NOT ok. What is wrong? regards Thomas BornhauptArticle: 36090
Just wanted to announce the release of two new tutorials: Introduction to WebPACK 4.1 for FPGAs: http://www.xess.com/appnotes/webpack-4_1-fpga.pdf Introduction to WebPACK 4.1 for CPLDs: http://www.xess.com/appnotes/webpack-4_1-cpld.pdf These tutorials introduce the use of WebPACK 4.1 and show: How to start an FPGA or CPLD project. How to target a design to a particular type of FPGA or CPLD. How to describe a logic circuit using VHDL and/or schematics. How to detect and fix VHDL syntactical errors. How to synthesize a netlist from a circuit description. How to fit the netlist into an FPGA or CPLD. How to check device utilization and timing for an FPGA or CPLD. How to generate a bitstream for an FPGA or CPLD. How to download a bitstream to program an FPGA or CPLD. How to test the programmed FPGA or CPLD. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 36091
Peter wrote: > > Hello, > > Xilinx took over this line from Philips and promptly discontinued it. > I am after a few hundred, PLCC, any speed. > > Or maybe pin for pin replacements. It does not have to be "zero > power". > > Peter. > -- > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary. Peter, AFAIK, Atmel has drop-in replacements (ATF22V10 I think). IwoArticle: 36092
Does anybody know of suppliers for altera parts in prototype quantities ( 1's and 2's ) as well as programing for the serial proms in Canada.I have briefly check the internet and could find nothing. I am looking for 10K10LC84 and EPC144LC20. FPGA and prom. Ben Franchuk. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 36093
Hi, i found it by my self. The devices are programed. But there is an wrong information in the dataport from the parallelport. If the byteblaster cabel is on, the devices are blockt. Take the cabel away or set Dateport with a little programm to 2 (port[$378]:=2;) fix the problem. regards Thomas "Thomas Bornhaupt" <Thomas.Bornhaupt@t-online.de> schrieb im Newsbeitrag news:9rj6j2$ec$00$1@news.t-online.com... > Hi, > > i have two divices in chain. First EPM7064SLC and than EPC2LC. > > With MAX+plus II i can program the JTAG Chain. It works fine. > Then i create jam files (*.JAM or *.JBI) with MAX+plus II. > With JAM.EXE (Version 2.2) or (JBI.EXE version 2.1) the "Exit code = 0... > SUCCSESS", but the divices a NOT ok. > > What is wrong? > > regards > Thomas Bornhaupt > > > > >Article: 36094
>Here is the answer from Xilinx in Albuquerque ( the former Philips CoolRunner >group) > >"We have misc. inventory on the Philips-marked product as follows: > >P5Z22V10IDA (10 ns industrial) - thousands >P5Z22V10-7A (7.5ns commercial) - hundreds > >We don't have any excess die on this one, so no Xilinx marked (XCR22V10) devices > >can be ordered. Anybody can purchase the Philips marked devices through any >Xilinx >franchised distributor on a NCNR basis. Order multiple is 26, a minimum order >will most probably apply, but if they're buying appx. 500 pieces they will meet >it." > >Hope that helps. Sounds like good news! > >Peter Alfke, Xilinx Applications Do you have any PLCC packaged parts (as per my subject header)? Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 36095
I answered this a while ago: Here is the answer from Xilinx in Albuquerque ( the former Philips CoolRunner group) "We have misc. inventory on the Philips-marked product as follows: P5Z22V10IDA (10 ns industrial) - thousands P5Z22V10-7A (7.5ns commercial) - hundreds We don't have any excess die on this one, so no Xilinx marked (XCR22V10) devices can be ordered. Anybody can purchase the Philips marked devices through any Xilinx franchised distributor on a NCNR basis. Order multiple is 26, a minimum order will most probably apply, but if they're buying appx. 500 pieces they will meet it." Hope that helps. Sounds like good news! Peter Alfke, Xilinx Applications ===========================================Article: 36096
> I am a student at the Vienna University of Technology (Austria) studying > electrical engineering. I want to build a small Digital Sampling > Oscilloscope, connected via USB (Cypress EZ-USB chip) to the PC. Look at the X2S_USB evaluation board from Cesys. You could connect your ADCs and your memory to the expansion connector. There is an VHDL example that shows how to transmit data using FRD / FWR and isochronous transfer. The board will be available at the end of November. www.cesys.com --ManfredArticle: 36097
Kevin Brace wrote: > Xilinx IP Evaluation License Agreement > > Xilinx Evaluation IP is owned and controlled by Xilinx and > must be used solely for design, simulation, implementation and > creation of design files limited to Xilinx devices or technologies. > Use with non-Xilinx devices or technologies is expressly prohibited > and immediately terminates your license. Kolja Sulimma <kolja@sulimma.de> writes: > This violates the "principle of first sale" in the US and the > "Erschöpfungsgrundsatz" in germany. When I buy a product the vendor > looses all control over how I use the product. Many things in the US violate the principle of first sale. In general, U.S. copyright law does. For instance, when you buy a VHS tape of a movie, you aren't allowed to use it for public exhibition. License agreements may well violate the principle of first sale. The question is whether the license is binding and enforceable.Article: 36098
"Antonio Pasini" <pasini.a@libero.it> wrote in message news:RUOC7.18406$Qj6.1344938@news.infostrada.it... > So... stop whining :-), take your next idea, take a book, a compiler and > start playing around. It's really worthwile! Just for the record. I have not been whining at all. It is a fact that the choices today are VHDL and Verilog (and Handel-C) and, after much reading and thinking about the comments on ths NG I decided to concentrate on VHDL, which is what I'm doing now. My comments about a "next generation" approach have nothing to do with complaining as much as just offering ideas for anyone who might be listening on what might help increase a designer's productivity. -MartinArticle: 36099
Hello. You might look at http://www-li5.ti.uni-mannheim.de/fpga/?race/ Takes a XC2V3000 or bigger, comes with 64bit PCI interface (PLX) It is still not a commercial product but if you are interested, let me know. Cheers, Andreas #BASUKI ENDAH PRIYANTO# wrote: >Hi, > >Currently, I am looking for Xilinx Virtex 2 or Virtex E evaluation >board. Basically, ,my requirement is the FPGA which has at least 3 >Million System gate. > >Anybody can help me ? > >Thanks ! > >Basuki >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z