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Hello folks, I am trying to get started in programmable logic, but so far having somewhat of a hard time. I have a simple project sitting in my digital circuit emulator program, and I would like to realize it using some kind of programmable logic device. Actually, I had been planning to realize the design in discrete 74xx TTL's (it's that simple--just a 10-bit counter, some AND gates, some flip flops, and some NAND gates), but I thought this might be a good time to get into the world of programmable logic devices. So far, however, I'm having a lot of trouble sorting through all the different kinds of devices that are available, and was wondering if anyone here could help me out. Specifically, perhaps someone could help me with the following questions: 1. What kind of programmable devices should I be looking into to implement the design mentioned above? I assume the presence of flip-flops and an n-bit counter is a little beyond the level of PALs and GALs, but perhaps I'm wrong? Is FPGA what I need/want, or something else entirely? 2. Moreover, can someone give a brief description of the differences between the major families of programmable devices? e.g., PAL vs. GAL vs FPGA etc. (if there's a FAQ or other reference that does this, please just point me to it.) 3. Which families of devices have TTL-level inputs/outputs? 4. What are some good introductory reference materials? Books, websites, etc. Thank you for your time and help in getting a beginner started! Rob VHDLArticle: 15001
Depending on the number of ff's, you might get it to fit in a PAL. A 22V10 variant sold by Atmel is the ATV750, which if I remember has 10 output flipflops plus another 10 'buried' flip-flops. The next step up is usually considered to be a CPLD, which has a PAL like structure (an array of programmable product terms, usually fairly wide, feeding one or more flip-flops). Each of the product term arrays has fixed, or relatively fixed connections to inputs and/or outputs of the array. The result is the routing delay is quite deterministic. If your design didn't fit some of the larger PALs, it would certainly fit just about any CPLD on the market. CPLDs include phillips coolrunner, Altera 7K, cypress, xilinx 9500, Vantis Mach parts, etc. FPGAs are a different structure, usually considered to consist of an array of logic cells (simpler than CPLD 'macrocells') in a sea of basically undedicated routing. The FPGA logic cells typically have a small number of inputs (4-9). The signal routing in an FPGA is more like a fabric of short wires and switches, so a route may require transiting several switches. Most of the devices have TTL compatible I/O. You do have to be careful with some of the low voltage devices, as the inputs are sometimes not "5 volt tolerant". If you use a 5 volt device, the I/O will be TTL compatible. For some basics, you might check out my website (lite on the really basic stuff) or http://www.optimagic.com Robert4422 wrote: > Hello folks, > > I am trying to get started in programmable logic, but so far having somewhat of > a hard time. I have a simple project sitting in my digital circuit emulator > program, and I would like to realize it using some kind of programmable logic > device. Actually, I had been planning to realize the design in discrete 74xx > TTL's (it's that simple--just a 10-bit counter, some AND gates, some flip > flops, and some NAND gates), but I thought this might be a good time to get > into the world of programmable logic devices. So far, however, I'm having a > lot of trouble sorting through all the different kinds of devices that are > available, and was wondering if anyone here could help me out. > > Specifically, perhaps someone could help me with the following questions: > > 1. What kind of programmable devices should I be looking into to implement the > design mentioned above? I assume the presence of flip-flops and an n-bit > counter is a little beyond the level of PALs and GALs, but perhaps I'm wrong? > Is FPGA what I need/want, or something else entirely? > > 2. Moreover, can someone give a brief description of the differences between > the major families of programmable devices? e.g., PAL vs. GAL vs FPGA etc. > (if there's a FAQ or other reference that does this, please just point me to > it.) > > 3. Which families of devices have TTL-level inputs/outputs? > > 4. What are some good introductory reference materials? Books, websites, etc. > > Thank you for your time and help in getting a beginner started! > > Rob > > VHDL -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15002
You university bookstore probably has it. AFAIK it runs just under $100 US. No such thing as free lunch! Ilia Oussorov wrote: > Hi all! > I'm student > Where I can get Student Editon of Foundation Ser. Is it free for me? > With best regards. > > Ilia Oussorov > TU Ilmenau > > Pl. answer on my email! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15003
Eduardo Augusto Bezerra wrote: > Hello > > I want to use VHDL in order to have a technology independent > implementation, but the problem is that VHDL is not synthesis > tool independent. Is it correct? Is it possible to have only > one VHDL description which can be used for several synthesis > tools to infer memory to different FPGAs? > Good luck! Since I generally use FPGAs for ASIC prototyping, I'm usually happy to accept what ever bizarre implementation the synthesis tool comes up with as long as it meets timing. However, that is not the case with RAMs. I always implement RAMs as structural blocks wrapped in VHDL. True, I do need two RAM blocks, one for the FPGA and one for the ASIC, but that has been much less annoying then trying to get the synthesis tools to do what I want. ToddArticle: 15004
I apologize for being slightly off subject, but have any of the members of this group worked with any "fast-turn" ASIC vendors? We are looking for fab times under a month. We have worked with Chipexpress in the past, but Chipexpress doesn't have any processor core licenses and the ASIC we are doing needs an embedded processor. Besides Chipexpress, I know of: Lightspeed, Toshiba, Am I missing anyone? (I hope!) Thanks, ToddArticle: 15005
Todd Kline wrote:
> I apologize for being slightly off subject, but have any of the members
> of this group worked with any "fast-turn" ASIC vendors? We are looking
> for fab times under a month. We have worked with Chipexpress in the
> past, but Chipexpress doesn't have any processor core licenses and the
> ASIC we are doing needs an embedded processor.
>
> Besides Chipexpress, I know of:
>
> Lightspeed,
> Toshiba,
>
> Am I missing anyone? (I hope!)
>
> Thanks,
> Todd
You might want to take a look at Atmel.
They have a pretty good selection of cores, decent process and their
fab times can be less than a month.
--
~~~ "It's not a BUG,
/o o\ / it's how I make my living"
( > )
\ ~ / Jerry English
_]*[_
Article: 15006Any easy way to put in place a VHDL model which does not need to be synthesizable (sp) that would allow entries like a memory? I realize the examples have ROM, but they all are in binary. What about different base? What about appending comments on an entry into a memory array to get a message.. i.e. address data comment 0x5 0x30 (r1) <- r1 + 1 0d55 0d2 NOP Is this possible with VHDL. Create a file where the VHDL spits out an entry from the file based on the addrss presented to it? Thanks. Jim .Article: 15007
Hi, just working with MAX+PLUSII and FLEX devices. Just got my design fitted every time now, having the FPGA filled up to 95%, so I just assign the signals to fit routability on the PCB and then doing a 'example' fit to see if it works. Especially when designing a new design the used device shouldn't be filled up to 95% preventing future upgrades. Don't know the situation with MAX Devices, with FPGA you mostly find devices with greater capability and same pinout (e.g. EPF6016 and EPF6024). Ciao, CSArticle: 15008
Hi Please what is the Self-Timed circuit design technique? Is it synchronous, asynchronous or something different? What its advantage over the traditional design techniques? Thanks in advanceArticle: 15009
Hi,
I am urgently looking for 1 to 30 Xilinx XC 4020 XLA 09 PQ 208 C
Acceptable variants are : XC 4020 XL 09 PQ 208 C
XC 4020 XLA 1 PQ 208 C
XC 4020 XL 1 PQ 208 C
Also acceptable: the last digit being an "I" instead of a "C".
Please send me price and possible delivery time.
Thanks in advance.
-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15010Yes, self-timed design is asynchronous (i.e. no global timing reference or clock.) For more info on self-timed design, check out http://www.cs.man.ac.uk/amulet/async/index.html Mike -- Mike Lewis, mailto:lewism@cs.man.ac.uk -------------------------------------- AMULET Group, University of Manchester http://www.cs.man.ac.uk/~lewism/Article: 15011
Hi, in self-timed logic there is no global clock existing, i.e. from this point of view it's an asynchronous design technique. But it's not at all based on race conditions and wiring delays as it is the case when you have asynchronous parts in a synchronous design. Usually a very strict 4-phase-full handshake protocoll is implemented, which is based on 'request' and 'acknowledge' signals (to be a bit faster you can also use a 2-phase handshake protocoll). This protocoll implies two things: - control overhead - special kind of logic gates (SSDL) To be able to generate an acknowledge signal as a result of the evaluation of the logic, special logic gates with differential outputs are needed like Sample Set Differential Logic (SSDL). In traditional (synchronous) design techniques you always have the problems of wiring delays. This becomes even more problematic when you are moving towards smaller gate length (Very Deep SubMicron). The transistor switching time becomes less important in comparison to the wire delay. Additionally the amount of gates per area becomes higher as well, which leads to longer clock nets as well. In a synchronous system you need to guarantee that there is not too much skew between the each clock input of the same clock net. The effort to achieve this becomes higher and higher. Exactly here is the advantage of self-timed logic. Because a proceeding action is triggered by the completion of the previous one, you do not have such distribution problems. You can have a look on articles of the following authors: Robert Broderson (Berkeley University, early 90s) Eric Brunvand (Carnegy Mellon University, early 90s) As far as I remember the approach of E. Brunvand is not delay insensitive, but he implemented it into FPGAs. The whole topic is not just a theoretic playing. Philips implemented an error correction algorithm using this technique. Have fun, Alex Schreiber In article <36DCDC1C.C1817CD7@ieee.org>, khatib@ieee.org wrote: > Hi > Please what is the Self-Timed circuit design technique? Is it > synchronous, asynchronous or something different? > > What its advantage over the traditional design techniques? > > Thanks in advance > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15012
I want to combine 3 xilinx designs (4005xl's) into a single 4013xl part. The 3 designs are all done in foundation schematic entry, and are "flat". Each design is about 5 pages of schematics. Can I do a hierarchial schematic for this large design by creating a macro for each of the 3 small designs and then connecting them all togeather on a top level schematic? This would require creating a macro for each of the small designs from its multi-page schematic. I have been able to create a macro from "the current schematic page", but have not been able to create a macro from a multi-page schematic (or add a schematic page to a macro). Can someone help? Thanks DanArticle: 15013
Hello all, here's my problem: I have a DSP design which fits nicely in a X4010E chip. The design was described in VHDL, and I used the Xilinx F1.5 tools to synthesize, map, and PAR. In order to meet stringent timing requirements, I also had to use Floorplanner to manually place components on the critical paths, and obtained results much improved from what PAR could do. Now, I want to reuse this design in a larger one by adding some front-end and back-end processing. The new design should go in a larger chip, and maybe a different family. Obviously, I would like to re-use my manual placement information instead of spending three or four days going through the process again. The Xilinx documentation says that guided mapping and incremental design with the Floorplanner constraints is not recommended for VHDL-based designs, because every new synthesis may generate different signal and instance names. I'm not the kind of guy who takes no for an answer, at least not initially. Therefore, I was hoping to be able to generate some kind of RPM from my first design and use it as a whole component in another design, much like using a Logiblox component. I haven`t been able to find a way to do this. Can anyone recommend a process that would allow me to solve this problem? Thanks in advance. =============================================== Pierre Langlois Département de mathématiques et informatique Collège militaire royal du Canada tél. (613)541-6000 x6860 B.P. 17000 Succ. "FORCES" fax. (613)541-6584 Kingston ON K7K 7B4 Canada langlois-p@rmc.ca ===============================================Article: 15014
Hello all, I would like to know of anyone's experience in pushing the I/O speeds of Xilinx 4K series to their limits. I find that the Xilinx documentation is vague on this subject. For example, for a certain design I have, the TRACE tool reports that all constraints are met for a clock frequency of 100 MHz in a X4000XL-09 chip. This includes 10ns constraints on "from pads to INFF" and "from OUTFF to pads". This is consistent with "IOB Input and Output Switching Characteristic Guidelines" for the family, which list propagation delays all well under 5ns for the XL-09 family. However, the generic Xilinx document "XC4000E and XC4000X Series FPGAs", dated Nov 10, 1997, says that the devices " ... can run at synchronous system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz." Is there some limitation that kicks in at 80 MHz for the I/Os? What is it? Any suggestions on how to get around it? Thanks in advance. =============================================== Pierre Langlois Département de mathématiques et informatique Collège militaire royal du Canada tél. (613)541-6000 x6860 B.P. 17000 Succ. "FORCES" fax. (613)541-6584 Kingston ON K7K 7B4 Canada langlois-p@rmc.ca ===============================================Article: 15015
I need for clocks out, one at 236,16Khz, a other at 245Khz, thirth 254,8Khz and the last 269,5kHz from reference crystal at 10Mhz i need a PLD or PFGA to make a counter with 4 output for each frequency !! My question what the best I can use for this ? Thank you !!Article: 15016
"saffary" <saffary@club-internet.fr> wrote: >Does anyone have a lcd cntrol core, and ,or info about this. >Thanks Please be more specific, which kind of LCD ? Static, multiplexed, or grafic? How many segments (/pixels) ?Article: 15017
Pierre, I've experimented with XC4005E-4. To my great surprise, it successfully takes 136 MHz frequency via I/O pin. But here is the trick - you should manually place high frequency CLB as close as possible to the 136 MHz pin. If there is a long way from the pin to the CLB clock input, oscillations are lost somewhere inside internal delays. Regards, Alex Sherstuk AMSD Company Pierre Langlois wrote in message <36DD48C3.B482C1F5@rmc.ca>... >Hello all, > >I would like to know of anyone's experience in pushing the I/O speeds of >Xilinx 4K series to their limits. > >I find that the Xilinx documentation is vague on this subject. For >example, for a certain design I have, the TRACE tool reports that all >constraints are met for a clock frequency of 100 MHz in a X4000XL-09 >chip. This includes 10ns constraints on "from pads to INFF" and "from >OUTFF to pads". This is consistent with "IOB Input and Output Switching >Characteristic Guidelines" for the family, which list propagation delays >all well under 5ns for the XL-09 family. > >However, the generic Xilinx document "XC4000E and XC4000X Series FPGAs", >dated Nov 10, 1997, says that the devices " ... can run at synchronous >system clock rates of up to 80 MHz, and internal performance can exceed >150 MHz." > >Is there some limitation that kicks in at 80 MHz for the I/Os? What is >it? Any suggestions on how to get around it? Thanks in advance. > > >=============================================== >Pierre Langlois >Département de mathématiques et informatique >Collège militaire royal du Canada tél. (613)541-6000 x6860 >B.P. 17000 Succ. "FORCES" fax. (613)541-6584 >Kingston ON K7K 7B4 Canada langlois-p@rmc.ca >=============================================== > > >Article: 15018
Dan- Unfortunately,there is no way to create a multi-page macro. The way I see it, you have a few different choices: - Break the "multi-page macros" into single page macros, then make a larger macro out of those. Basically, create another level of hierarchy. - Add all the schematics to the 4013xl design, and have a ton of top level schematics (not a good idea) - In each 4005xl project, get rid of the ipads and opads (and ibufs and obufs) and Export Netlist. Then, in the 4013xl project, you can create a macro from a netlist. This may be the best way to go without doing some major modifications. Hope this sets you on the right track. Mike Peattie Xilinx Applications Dan Kuechle wrote: > I want to combine 3 xilinx designs (4005xl's) into a single 4013xl part. > The 3 designs are all done in foundation schematic entry, and are "flat". > Each design is about 5 pages of schematics. > Can I do a hierarchial schematic for this large design by creating a macro > for each of the 3 small designs and then connecting them all togeather on > a top level schematic? This would require creating a macro for each > of the small designs from its multi-page schematic. I have been able to > create a macro from "the current schematic page", but have not been able > to create a macro from a multi-page schematic (or add a schematic page > to a macro). Can someone help? > > Thanks > DanArticle: 15019
Does anyone have a clever circuit that can divide an input clock by two and a half? We're looking to go from 100MHz down to 40MHz. I've thought of a couple of ways to do this, but they all had some asynchronous parts to them that required that I could guarantee minimum propagation delays. In a 100MHz part I didn't really want to have to guess at the minimum propagation delays (neither Xilinx nor Cypress nor Vantis -- vendors whose CPLDs we're thinking of implementing this in -- mention their minimum propagation delays in the data sheets that I looked at). Additionally I don't want to buy a faster speed grade device -- any change in speed grade would cost more than the ~$3 of an external PLL. (In which case I'd divide by 5 and multiply by 2.) Most CPLDs these days can clock on either edge of the incoming clock, and it initially seemed that a design that had two "divide by fives" and then combinatorially ORed the results together would work. Getting the two circuits synchronized is the problem. Either they have to rely on each other's output, which effectively means the design is running at 200MHz internally, or they have to rely on an external result pulse, and generating it at the exact time point required appeared difficult. ---Joel KolstadArticle: 15020
Assume you have a state machine that has some "interesting" state encoding... say the reset state encodes to 1010, and then the state machine always steps to a state encoded by 0101. This state machine has an asynchronous reset input, which comes from a pin on a CPLD or FPGA. The clock to this synchronous state machine also comes from a pin. Isn't a completely asynchronous reset input just asking for trouble? While reset is active, the state machine is sitting at 1010. If I now assume that reset goes inactive just a split (nano)-second before the active clock edge, I don't have any guarantees at all that some of the state encoding bits are going to transition to their expected new values, whereas some won't transition at all, correct? If this is really an issue, it would appear that the correct way to apply an asynchronous reset is to first run it through a synchronizer before applying it to the asynchronous reset input of the state machine. ---Joel KolstadArticle: 15021
> the TRACE tool reports that all > constraints are met for a clock frequency of 100 MHz in a X4000XL-09 > chip. This includes 10ns constraints on "from pads to INFF" and "from > OUTFF to pads". This is consistent with "IOB Input and Output Switching > Characteristic Guidelines" for the family, which list propagation delays > all well under 5ns for the XL-09 family. > > However, the generic Xilinx document "XC4000E and XC4000X Series FPGAs", > dated Nov 10, 1997, says that the devices " ... can run at synchronous > system clock rates of up to 80 MHz, and internal performance can exceed > 150 MHz." > > Is there some limitation that kicks in at 80 MHz for the I/Os? What is > it? Any suggestions on how to get around it? Thanks in advance. The 4kE series timing is completely different than the 4kXL series. I also don't understand what you mean by 80MHz for I/O. The 80MHz they refer to in your quote is overall chip frequency, as opposed to the 150MHz flop to flop with probably no logic between... I/O doesn't have a 'frequency', per say, it has a delay. You would have to add up the clock to out and delay from the source, clock skew between the source and the Xilinx flop, etc. So, given this, I don't really understand what your question is? Austin Franklin austin@darkroom.comArticle: 15022
It may be a bit theoretical, but the book title: Synchronization Design for Digital Systems author: Teresa H. Meng publ: Kluwer Academic Press ISBN: 0-7923-9128-4 is interesting and may answer some questions. /UA -- Ulf Andersson E-mail: Ulf.Andersson@Axis.com Axis Communications AB Tel: +46 46 270 17 34 S - 223 70 LUND Fax: +46 46 13 61 30 SWEDEN WWW: http://www.axis.comArticle: 15023
Create a divide_by_5 circuit, delay it by 2.5 cycles, then OR the original and delayed versions together. Any CPLD that can clock on both edges of the 100MHz clock should be able to do this. You may then want to register the ORed result again with 100MHz. Bob S. Joel Kolstad wrote: > > Does anyone have a clever circuit that can divide an input clock by two and > a half? We're looking to go from 100MHz down to 40MHz. I've thought of a > couple of ways to do this, but they all had some asynchronous parts to them > that required that I could guarantee minimum propagation delays. In a > 100MHz part I didn't really want to have to guess at the minimum propagation > delays (neither Xilinx nor Cypress nor Vantis -- vendors whose CPLDs we're > thinking of implementing this in -- mention their minimum propagation delays > in the data sheets that I looked at). > > Additionally I don't want to buy a faster speed grade device -- any change > in speed grade would cost more than the ~$3 of an external PLL. (In which > case I'd divide by 5 and multiply by 2.) > > Most CPLDs these days can clock on either edge of the incoming clock, and it > initially seemed that a design that had two "divide by fives" and then > combinatorially ORed the results together would work. Getting the two > circuits synchronized is the problem. Either they have to rely on each > other's output, which effectively means the design is running at 200MHz > internally, or they have to rely on an external result pulse, and generating > it at the exact time point required appeared difficult. > > ---Joel KolstadArticle: 15024
Pierre Langlois wrote: > Hello all, > > I would like to know of anyone's experience in pushing the > I/O speeds of > Xilinx 4K series to their limits. > > snip > However, the generic Xilinx document "XC4000E and XC4000X > Series FPGAs", > dated Nov 10, 1997, says that the devices " ... can run at > synchronous > system clock rates of up to 80 MHz, and internal > performance can exceed > 150 MHz." > > Is there some limitation that kicks in at 80 MHz for the > I/Os? What is > it? Any suggestions on how to get around it? Thanks in > advance. > The "ultimate authority" is the software using the worst-case numbers in the speed file. (Assuming you want a bullet-proof design. In the lab you can always rig up something that runs much faster at room temperature). The generic document quoted above is 16 months old, a long time in this industry. Whenever we ( at Xilinx ) make generic statements, we have to balance two aspects: We want to be conservative, honest, and not misleading, but we also want to promote the good features of our devices, and create excitement . At Xilinx, we often overdo the conservative aspects. And that must have been behind the 80 MHz number. I have designed and built a frequency counter ( in XC4002-09 ) that counts an input signal at over 420 MHz, and I have demonstrated this working design at various shows in 1998. So if you just want to go through the input buffer and toggle a flip-flop, you can do that - worst-case and using the speed-file values- at over 400 MHz. But I still won't claim that 420 MHz is the I/O frequency. For I/O-limited performance, we take the inverse of the sum of worst-case input set-up plus clock-to-output times. That value is above 100 MHz and can be pushed to 200 MHz, using the DLL in Virtex, essentially eliminating the on-chip clock delay. Peter Alfke, Xilinx Applications
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