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Messages from 49950

Article: 49950
Subject: Custom FPGA synthesis
From: "Andy Mitchell" <acm11@york.ac.uk>
Date: Tue, 26 Nov 2002 17:09:20 -0000
Links: << >>  << T >>  << A >>
Hi,

I`m wondering if anyone knows of a synthesis tool for FPGAs (i.e.
LeonardoSpectrum) where a custom Technology/architecture can be specified as
opposed to using the existing Technologies (i.e. Xilinx Virtex)...I`ve heard
that a plug-in/module exists for Leonardo which allows this but I cant seem
to find any information on it..

Many thanks for any help.

--



Article: 49951
Subject: Re: Fast Digital Synthesis Generator
From: "Mark McMahon" <point308@hotmail.com>
Date: Tue, 26 Nov 2002 17:44:05 GMT
Links: << >>  << T >>  << A >>
Alan said:
> Either you are using a very old and slow device, or there is something
> wrong with your design.

I say:
Either you are using a very old and slow device, or there is something
wrong with your design.

I am using a 33 bit accumulator (with a 31bit control word) in a Spartan II
xc2s50 -6, clocked at 64MHz with no problems.

Try this:

SIGNAL ACCUMULATOR   : unsigned (32 DOWNTO 0); -- THE ACCUMULATOR IS LARGER
THAN THE CONTROL WORD.
SIGNAL SIGN    : std_logic;
CONSTANT HIGH : std_logic := '1';
CONSTANT LOW : std_logic := '0';

BEGIN
clkout <= sign;  -- THE TOP BIT IS THE DDS GENERATED CLOCK

PROCESS(RESET, CLK) BEGIN
     IF (RESET = LOW) THEN
         ACCUMULATOR <= (OTHERS => '0');
     ELSIF CLK'EVENT AND CLK=HIGH THEN
     ACCUMULATOR <= ACCUMULATOR + unsigned(FREQ_CW);
      END IF;
END PROCESS ACC;
SIGN <= ACCUMULATOR(32);

Mark.

Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote in message
news:3de3611a.114493022@netnews.agilent.com...
> On 26 Nov 2002 03:23:52 -0800, edaudio2000@yahoo.co.uk (ted) wrote:
>
> >I need to implement a fastish DDS using a 32 bit accumulator (I need
> >the resolution).
> >
> >However, I am hitting the carry ripple problem, and the fastest clock
> >frequency I can manage at the moment is 20MHz
>
> Sure you didn't slip a decimal place?  A modern FPGA should be able to
> do a 32 bit accumulator using ripple carry comfortably at 200MHz, not
> 20MHz.
>
> Either you are using a very old and slow device, or there is something
> wrong with your design.
> ... but to help you, we will need to know which device and which
> design entry method you are using.  It would also be a help if you
> posted your code.
> --





Article: 49952
Subject: Re: count based Frequency generator
From: David Gamboa <dgamboa@ieee.org>
Date: Tue, 26 Nov 2002 11:51:19 -0600
Links: << >>  << T >>  << A >>

	With a basic counter, where you count from 0 to de number that is given 
in your 12bit input. The ways you can do that are too much.


Article: 49953
Subject: Re: Custom FPGA synthesis
From: Stephen Williams <icarus-hates-spam@icarus.com>
Date: 26 Nov 2002 18:30:53 GMT
Links: << >>  << T >>  << A >>
Andy Mitchell wrote:
> Hi,
> 
> I`m wondering if anyone knows of a synthesis tool for FPGAs (i.e.
> LeonardoSpectrum) where a custom Technology/architecture can be specified as
> opposed to using the existing Technologies (i.e. Xilinx Virtex)...I`ve heard
> that a plug-in/module exists for Leonardo which allows this but I cant seem
> to find any information on it..

Icarus Verilogs supports custom "code generators" but they are written
in C. Also, the synthesizer in Icarus Verilog is pretty fresh.

   <http://www.icarus.com/eda/verilog/>


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

abuse@xo.com
uce@ftc.gov


Article: 49954
Subject: question about programmable oscillator ?
From: anand287@lycos.com (Anand)
Date: 26 Nov 2002 11:43:37 -0800
Links: << >>  << T >>  << A >>
hi everybody,

 I am looking for a programmable oscillator for a XCV2000E board .
i.e the VIRTEX-E 2000 part. This FPGA has 3.3 volt I/O's.

(So I assume it needs 3.3 v oscillator ???)

I need it to be programmable between say, 1Mhz to 120 Mhz.
Moreover I need to be able to program it "after" it has been installed
on the board.

Also, the programming needs to be accomplished in a simple way ;

I am not knowledgeable enough to devise elaborate programming options
like something that XESS does using their XESS setclk program etc.

Please do reply with your suggestions and comments .

thanks very much

regards

Anand Kulkarni

Article: 49955
Subject: Re: problems programming/verifying fpga using ISE 5.1
From: Neil Glenn Jacobson <neil.jacobson@xilinx.com>
Date: Tue, 26 Nov 2002 11:51:33 -0800
Links: << >>  << T >>  << A >>
I believe this solution record may describe your situation:

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13461

Kyle Guichard wrote:

> Hi all,
>
> When I program my spartan 2 using the ISE software using JTAG, it
> tells me that "programming succeeded." However, when I verify the
> design, it comes up with thousands of discrepancies in the design
> actually on the fpga. When I implement very simple logic like an AND
> gate, it works sporadicaly and does not work at all after shutting
> down the fpga.
>
> Any help or direction would be great.
>
> thanks!
> kyle


Article: 49956
Subject: Re: Custom FPGA synthesis
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 26 Nov 2002 11:52:03 -0800
Links: << >>  << T >>  << A >>
Andy Mitchell wrote:

> Hi,
> 
> I`m wondering if anyone knows of a synthesis tool for FPGAs (i.e.
> LeonardoSpectrum) where a custom Technology/architecture can be specified as
> opposed to using the existing Technologies (i.e. Xilinx Virtex)...I`ve heard
> that a plug-in/module exists for Leonardo which allows this but I cant seem
> to find any information on it..



That's probably because only customers ic fabs would be
interested in porting to synthesis tools.

Do a google search on: leonardo lgen


Lgen costs extra and likely only works with the "level 3" product.

  -- Mike Treseler


Article: 49957
Subject: Re: Xilinx programming and PCI printer port
From: Neil Glenn Jacobson <neil.jacobson@xilinx.com>
Date: Tue, 26 Nov 2002 11:54:54 -0800
Links: << >>  << T >>  << A >>
Dziadek wrote:

> Well, it does not seem to work.
> The "Properties" dialog box for PCI printer does not report I/O range at all
> (because it is an emulation, not a physical port). Instead I have tried to
> use addresses of resources listed for the PCI card, but it does not work,
> too.
>
> Is your solution implemented in Impact 4.2?

You must use iMPACT 5.1i or better for the described solution to work,

>
>
> Today I expect to get another PCI I/O card. Then I will try to run Impact
> with this new one.
>
> Thanks for help, anyway.
>
> Dziadek
>


Article: 49958
Subject: Re: Fast Digital Synthesis Generator
From: Ray Andraka <ray@andraka.com>
Date: Tue, 26 Nov 2002 21:12:55 GMT
Links: << >>  << T >>  << A >>
You didn't mention the device.  I'll presume for the moment that you are
using a device with built in carry chains (Altera 10K or later, or any
Xilinx after 3K).  If that is the case, and assuming that the synthesizer
inferred the chain (it will unless you did something totally goofy), then
there are a few things that could be slowing it down.  Most likely, you
have a long delay path feeding into the carry chain.  Ideally, the inputs
to the adder should be registered and placed immediately adjacent to the
accumulator.  For the feedback, that is easy, since it is coming from the
accumulator output (this assumes that it didn't put logic between the
carry chain and the registers).  For the increment value, pipeline that so
that you get a register feeding directly into the accumulator with no
muxes or whatnot in between.

Also look to see if the synthesis inferred a mux or gate between the carry
chain and the register.  This separates the two, and the autoplacer is not
particularly good at putting the separated pieces near each other.  You
will often get a mux AFTER the carry chain if you put a synchronous reset
term or load term along with an async global reset.  Ideally, you need to
redefine the add slightly so that the reset modifies the inputs of the add
instead of affecting the register directly. The synthesizers don't seem to
be very good at recognizing the distinction.

Finally, if you ave taken car of the above, floorplanning will help.

If you are using the Xilinx tools, make sure you have a timing constraint
on the DDS consistent with your target speed.  Especially in the newer
versions of  the tools, the tools only work as hard as needed to meet your
timing constraint.  If there is no constraint, it doesn't try very hard at
all.  You should be able to get in the high hundreds of MHz with a 32 bit
add in most of the current devices.


ted wrote:

> I need to implement a fastish DDS using a 32 bit accumulator (I need
> the resolution).
>
> However, I am hitting the carry ripple problem, and the fastest clock
> frequency I can manage at the moment is 20MHz
>
> Notwhitstanding using faster FPGAs or optimising the compilation (both
> of which can only help so far), are there any other techniques and
> tricks worth looking at?
>
> The application requires a very narrow range of frequencies in the
> 22-22.1MHz range, spaced a few Hz apart (hence the 32 bit
> accumulator).
>
> I could consider adding analogue frequency mixers and bandpass
> filters, but I'd rather avoid analogue circuits.
>
> Thanks in advance
>
> Theo

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 49959
Subject: Re: Fast Digital Synthesis Generator
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Tue, 26 Nov 2002 23:05:11 +0100
Links: << >>  << T >>  << A >>
Mark McMahon wrote:
> Alan said:
> 
>>Either you are using a very old and slow device, or there is something
>>wrong with your design.
> 
> 
> I say:
> Either you are using a very old and slow device, or there is something
> wrong with your design.
> 
> I am using a 33 bit accumulator (with a 31bit control word) in a Spartan II
> xc2s50 -6, clocked at 64MHz with no problems.
> 
> Try this:
> 
> SIGNAL ACCUMULATOR   : unsigned (32 DOWNTO 0); -- THE ACCUMULATOR IS LARGER
> THAN THE CONTROL WORD.
> SIGNAL SIGN    : std_logic;
> CONSTANT HIGH : std_logic := '1';
> CONSTANT LOW : std_logic := '0';
> 
> BEGIN
> clkout <= sign;  -- THE TOP BIT IS THE DDS GENERATED CLOCK
> 
> PROCESS(RESET, CLK) BEGIN
>      IF (RESET = LOW) THEN
>          ACCUMULATOR <= (OTHERS => '0');
>      ELSIF CLK'EVENT AND CLK=HIGH THEN
>      ACCUMULATOR <= ACCUMULATOR + unsigned(FREQ_CW);
>       END IF;
> END PROCESS ACC;
> SIGN <= ACCUMULATOR(32);


Basically repeatedly adding a sufficiently large value in a big register
and the wrap-around makes the tick, I guess.

Rene


Article: 49960
Subject: Re: Anybody know of vendors of PCI boards with FPGAs?
From: Kolin Paul <kolin@cs.colostate.edu>
Date: Tue, 26 Nov 2002 15:21:03 -0700
Links: << >>  << T >>  << A >>
u can check www.alphadata.com

David wrote:
> You can check www.dalanco.com
> 
> David
> 
> Seth wrote in message ...
> 
>>I am looking for vendors of PCI FPGA boards for production, not just
>>prototyping.
>>
>>So far I know of Annapolis Microsystems which offers boards with
>>Virtex chips and RAM.
>>
>>Can anyone recommend any others?
> 
> 
> 



Article: 49961
Subject: Initialising Spartan's Block RAM
From: "pradeep" <uqpprabh@dingo.cc.uq.edu.au>
Date: Wed, 27 Nov 2002 09:12:22 +1000
Links: << >>  << T >>  << A >>
Hi,

Just wanted to know whether the user should initialise the Spartan-II block
ram using the INIT_XX attribute or is it automatically initialised on
powering the chip.

thanks,
pradeep



Article: 49962
Subject: Re: Initialising Spartan's Block RAM
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Tue, 26 Nov 2002 23:23:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <as0v4m$vcg$1@bunyip.cc.uq.edu.au>,
pradeep <uqpprabh@dingo.cc.uq.edu.au> wrote:
>Hi,
>
>Just wanted to know whether the user should initialise the Spartan-II block
>ram using the INIT_XX attribute or is it automatically initialised on
>powering the chip.

By default, they are initialized to all 0s, although a warning is
issued in the mapping stage.


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 49963
Subject: Re: Frequency multiplier with digital h/w
From: "Gary Desrosiers" <gtdesrosi@cox.net>
Date: Wed, 27 Nov 2002 00:04:51 GMT
Links: << >>  << T >>  << A >>
Xilinx's Virtex devices have DLL (Digital Delay-Locked Loop) frequency
multipliers onboard. See;
http://www.xilinx.com/products/virtex/techtopic/vtt003.pdf

"Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message
news:arv489$me3js$1@ID-159866.news.dfncis.de...
> HI all experts,
>   Can somebody say me , how to implement a frequency multipliers with
> digital hardware without using a any combinational logic
>
> Thanks & Regards,
> SKillie
>
>



Article: 49964
Subject: question about PCB traces for FPGA board... ?
From: anand287@lycos.com (Anand)
Date: 26 Nov 2002 17:43:47 -0800
Links: << >>  << T >>  << A >>
hi everybody,

I hope this is the right audience for this question.

I am designing a Printed Circuit Board which mainly consists of an
FPGA [XCV2000E, xilinx virtex-E 2000 part,package : FG1156 ,fine pitch
ball grid array]  , "16" SCSI connectors [68 pin female]
and oscillator,regulator and configuration PROM.

Now, I am using 544 I/O's of this FPGA.
As result, I have 136 I/O's  from each side of the FPGA (four sides in
all)
and leaving the FPGA on various layers.

Following the Xilinx Board Routability Guidelines I chose 5 mil trace
width for these I/O's traces.

I plan to use 33 ohm series [ source ] termination resistors for half
of these 544 lines (since I intend to use half of them for sending and
half of them for receiving data ; and apparently the receivers do not
need termination)

Any suggestions on what is done in such a situation wherein one needs
to put in "so many termination resistors " and  very  limited space
[BGA part] is available ?

How much leeway do I have in choosing these termination resistors ?
Is 33 ohm  acceptable as a series termination resistor for a wide
range of trace characteristic impedances ?

Further, I believe I need to use 5 mil trace width  as  they leave the
FPGA BGA because  the number of traces is huge considering the space
between succesive balls in this BGA [ball grid array package].

I am not clear about the width of these traces as they move away from
the FPGA.

Is the trace width changed along the length of the trace ,normally ?
Say, the traces are on an average of length , 4 inches long ?

Please reply with your suggestions/comments...
I'd really appreciate it.

thanks very much 
regards
Anand Kulkarni

Article: 49965
Subject: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
From: "Mike D" <mdelphia@snet.net>
Date: Wed, 27 Nov 2002 02:01:07 GMT
Links: << >>  << T >>  << A >>
Rule #1 - if you can't picture it in hardware, don't write it in VHDL!!!


"Justin A. Kolodziej" <jkolodzi@students.uiuc.edu> wrote in message
news:Pine.GSO.4.31.0211111730001.3254-100000@ux13.cso.uiuc.edu...
> Does anyone have a pointer to a canonical list of things to do and avoid
> doing when you want to write VHDL that has a good chance of actually
> synthesizing correctly in Leonardo?
>
> I only know that what I do tends to work better than what my students do
> (I have the unfortunate task of TAing a class in embedded systems and
> reprogrammable logic), but I admit that I don't have such a list of rules
> that will guarantee that VHDL works when it is synthesized, even if it
> works in simulation.
>
> Certainly someone out there must have a list... and I don't mean the
> "Synthesizable VHDL" subset, because even if the synthesis tools gives no
> warnings or anything, things can break horribly when additional processes
> are added, it seems.
>



Article: 49966
Subject: Has anyone implemented a IEEE1394 LLC?
From: "MM" <misoma@NOrogersSPAM.com>
Date: Wed, 27 Nov 2002 03:23:39 GMT
Links: << >>  << T >>  << A >>
Hi all,

I was wondering if anyone has successfully implemented a IEEE1394 LLC in a
FPGA? I would like to know how much work it is and how much resources does
it require from the FPGA?

Any free cores out there?


Thanks,
/Mikhail



---
Outgoing mail is certified Virus Free.
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Article: 49967
Subject: How to instantiate a Hard-Macro in a design?
From: muthu_nano@yahoo.co.in (Muthu)
Date: 26 Nov 2002 20:34:45 -0800
Links: << >>  << T >>  << A >>
Hi,

I have created a hard-macro from the FPGA editor. and i got the .nmc
file. How should i instantiate this macro in my design.

when i open the .nmc file, i couldn't see the interface signals. How
can we view that one?

Best regards,
Muthu

Article: 49968
Subject: Re: question about PCB traces for FPGA board... ?
From: "MM" <misoma@NOrogersSPAM.com>
Date: Wed, 27 Nov 2002 06:11:02 GMT
Links: << >>  << T >>  << A >>
"Anand" <anand287@lycos.com> wrote in message
news:a6908954.0211261743.1d96e642@posting.google.com...

Skip...

> I plan to use 33 ohm series [ source ] termination resistors for half
> of these 544 lines (since I intend to use half of them for sending and
> half of them for receiving data ; and apparently the receivers do not
> need termination)

First of all,  Virtex devices allow some slew rate control, so you might not
need any resistors at all. However, it might be safer to design them in....

> Any suggestions on what is done in such a situation wherein one needs
> to put in "so many termination resistors " and  very  limited space
> [BGA part] is available ?

It is usually OK to have this resistor at some small distance from the
source, so you are not really that much limited in space. Then consider
using 0402 resistors or really small resistor arrays.

>  How much leeway do I have in choosing these termination resistors ?
> Is 33 ohm  acceptable as a series termination resistor for a wide
> range of trace characteristic impedances ?

That depends a lot on how big the (signal integrity) problem is. In an ideal
world you need to simulate it. In practice for signals below 100 MHz and for
relatively short traces, any value in the range from 10 to 50 Ohm will
probably work for the most cases.

> Further, I believe I need to use 5 mil trace width  as  they leave the
> FPGA BGA because  the number of traces is huge considering the space
> between succesive balls in this BGA [ball grid array package].
>
> I am not clear about the width of these traces as they move away from
> the FPGA.

No need to change them. As soon as you used 5 mil anywhere on the board a
PCB house will charge you based on this size anyway.

> Is the trace width changed along the length of the trace ,normally ?
> Say, the traces are on an average of length , 4 inches long ?

Normally you want to keep trace impedance constant, so any width changes or
other disturbances are not welcome.

/Mikhail


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Article: 49969
Subject: Re: count based Frequency generator
From: "Skillwood" <skillwoodNOSPAM@hotmail.com>
Date: Wed, 27 Nov 2002 16:08:34 +0900
Links: << >>  << T >>  << A >>
But if the numebr of input lines increases ....

Say I have a 32 bit i/p bus. The total no of frequencies will be 2^32 , the
frequencies are multiples of the base frequency like f,2f,3f,4f,.......2^32f
(for  all 32 1's ). I wan t to implement this in an fpga using HDL.
How can i generate 2f,3f.. from the system clock f . If we use a highe
frequency (higher than 2^32 )as a reference frequency is this possble.
thanks for your help

"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message
news:3DE34CF9.20903@dplanet.ch...
> There are various approaches, the simplest being just
> a counter, others might use the internal PLL of an FPGA ...
> What frequency range did you have in mind ?
>
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net
>
> Skillwood wrote:
> > Hi all,
> >     Can somebody tell me how to generate a signal frequency based on a
count
> > input value.
> > say I have a 12 bit i/p which can be used to give binary inputs. I want
to
> > generate an o/p signal frequency corresponding to each different
i/p(2^12).
>



Article: 49970
Subject: Re: question about PCB traces for FPGA board... ?
From: backhus@isms.hs-bremen.de (E. Backhus)
Date: 26 Nov 2002 23:20:16 -0800
Links: << >>  << T >>  << A >>
Hi,

> I plan to use 33 ohm series [ source ] termination resistors for half
> of these 544 lines (since I intend to use half of them for sending and
> half of them for receiving data ; and apparently the receivers do not
> need termination)
> 
> Any suggestions on what is done in such a situation wherein one needs
> to put in "so many termination resistors " and  very  limited space
> [BGA part] is available ?

You should contact a high-end PCB manufacturer and ask for resistors
that can be integrated into the PCB tracks. These resistors are not
"long and thin copper wires", they are made from special resistor
material for PCBs. For 33 Ohms i expect those to consume not more
space than your copper tracks, but you have to produce an extra gerber
file that shows the geometry of these special tracks. On your PCB
layer The result will look like this for 2 parallel tracks:

C = Copper track
R = Resistor Track

                                 CCCCCC  
   CCCCCCCCCCRRRRRRRRRRRRCCCCCCCC
                                   CCCCCC
   CCCCCCCCCCRRRRRRRRRRRRCCCCCCCCCC


Have a nice routing
  Eilert

Article: 49971
Subject: Re: count based Frequency generator
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 27 Nov 2002 20:21:26 +1300
Links: << >>  << T >>  << A >>
> Skillwood wrote:
> > Hi all,
>  Can somebody tell me how to generate a signal frequency based on a count
> input value.
> say I have a 12 bit i/p which can be used to give binary inputs. I want
> to generate an o/p signal frequency corresponding to each different
> i/p(2^12).
and
> How can i generate 2f,3f.. from the system clock f .

You cannot generate arbitary multiples of a lower clock, without
something like a faster oscillator : be it VCO, DLL, etc.
 So 2fi, 3fi..4095fi is not practical.

 However, I think what you are after is Fo = Fi * (N/4096), where
N is 0..4095.  Fi can be in the 100's of MHz in modern silicon.
 
 For HW examples of this, look for Binary Rate Multipliers
CD4089 is one device number. There is some phase jitter on the
output.

 This same topology can make what we call a Picket Fence DAC.

 - jg

Article: 49972
Subject: Re: count based Frequency generator
From: "Skillwood" <skillwoodNOSPAM@hotmail.com>
Date: Wed, 27 Nov 2002 17:07:48 +0900
Links: << >>  << T >>  << A >>
ok,
 if i have f and 4095f , Can I generate 2f,3f,4f,.....


"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:3DE47276.41C9@designtools.co.nz...
> > Skillwood wrote:
> > > Hi all,
> >  Can somebody tell me how to generate a signal frequency based on a
count
> > input value.
> > say I have a 12 bit i/p which can be used to give binary inputs. I want
> > to generate an o/p signal frequency corresponding to each different
> > i/p(2^12).
> and
> > How can i generate 2f,3f.. from the system clock f .
>
> You cannot generate arbitary multiples of a lower clock, without
> something like a faster oscillator : be it VCO, DLL, etc.
>  So 2fi, 3fi..4095fi is not practical.
>
>  However, I think what you are after is Fo = Fi * (N/4096), where
> N is 0..4095.  Fi can be in the 100's of MHz in modern silicon.
>
>  For HW examples of this, look for Binary Rate Multipliers
> CD4089 is one device number. There is some phase jitter on the
> output.
>
>  This same topology can make what we call a Picket Fence DAC.
>
>  - jg



Article: 49973
Subject: Re: Fast Digital Synthesis Generator
From: edaudio2000@yahoo.co.uk (ted)
Date: 27 Nov 2002 00:12:39 -0800
Links: << >>  << T >>  << A >>
> 
> Either you are using a very old and slow device, or there is something
> wrong with your design.
> ... but to help you, we will need to know which device and which
> design entry method you are using.  It would also be a help if you
> posted your code.
> 
Very valid quesion to ask!
I forgot to mention the constrains. 

This "extra" circuit is to be retroffited onto a board 
already containing an Altera 10K. The boards in stock already have
parts with a -4 speed rating. So that is my target. We could
re-populate the boards with faster devices, but at least I would like
to know that is the only viable option!!

The other alternative is to re-lay the board, and add a new device.
Because the DDS is the only function needed, it would be too expensive
to use large FPGAs,
so the only cost-relevant option would be to use a CPLD.

So the question should be re-phrased: Any hints on how to get the best
carry performance out of an Altera 10k (-4).

I got the 20 MHz limit by using the standard AHDL: 
accum[].d = accum[q] +  add[]
(all registered)

Using the library lpm_addsub() incresed the speed to about 30MHz. I
really
need to go at least up to 50MHz.

I have also fiddled with the various global options optimise settings.

Any hints?

Thanks in advance!

Also thanks to those who have already responded!

Theo


PS I have also noticed the MAX-II simulator gives result nothing like
the ones I get on the oscilloscope.

Article: 49974
Subject: HardMacro (from FPGA Editor) Instantiation
From: muthu_nano@yahoo.co.in (Muthu)
Date: 27 Nov 2002 00:37:06 -0800
Links: << >>  << T >>  << A >>
Hi,

Here i generated a Hard-macro using FPGA editor. But in the creation
itself i am getting the warnings below.

////////////////////////////////////////
save -w macro D:\\bei_bfr_smc_64_6.nmc
WARNING:FPGAEditor:172 - Placing and routing an unbound system macro
may given unexpected

results.
Component "PWR_GND_0" assigned to be reference component.
WARNING:DesignRules:18 - Macrodefcheck: This macro has no external
pins defined.
////////////////////////////////////////

And i instantiated this module as a black box in the design and
synthesised.During Place and Rounte I am expecting that, the macro
will be expanded in the translation phase. but it is giving the below
errors.

///////////////////////////////////////
ERROR:NgdBuild:76 - File
   "D:/bei_bfr_smc_64_6.nmc" cannot be merged
   into block "bfr_ins1/bei_bfr_smc_ins1"
   (TYPE="bei_bfr_smc_64_6") because one or more pins on the block,
   including pin "sampled_out", were not found in the file.  Please
make
   sure that all pins on the instantiated component match pins in the
   lower-level design block (irrespective of case).  If there are
bussed pins on
   this block, make sure that the upper-level and lower-level netlists
use the
   same bus-naming convention.
///////////////////////////////////////

How should we view the file for checking hte singals.? is the way of
instantiating macros is correct?

Thanks in advance.

Best regards,
Muthu



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