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Workgroup MCU & UPL
Belgium
Hello guys,
We are doing some studywork and need titles about
recommended VHDL books.
So if you have read certain books and can recommend it give me a sign ...
regards,
Michel
WMU Belgium
Article: 20951
KJ <Kevin.Jennings@Unisys.com> wrote in message
news:89gjav$sek$1@mail.pl.unisys.com...
> No you're not paranoid, you can't be sure that cpua_data(7) is properly
> latched. Transparent latches always need the redundant cover term when
> implemented as combinatorial logic (i.e. without benefit of some
predefined
> latch in the hardware architecture). I've seen this failure with several
> programmable devices.
>
> When I used Warp I couldn't find a way to have it keep the necessary
> redundant terms so unless the part you are targetting can guarantee that a
> latch will be implemeted properly I wouldn't suggest trying it. If it
does,
> you might want to change the logic somewhat like...
>
> latch_enable <= not(cpua_wr_not) or not(cpub_wr_not); -- Or together
the
> writes to create a latch enable
>
> Make your process sensitive to latch_enable instead of cpua_wr_not and
> cpub_wr_not and then use one of the write signals to select the data.
>
> process (reset, latch_enable, cpua_data, cpub_data)
> begin
> if reset = '1' then
> outport <= "00000000";
> elsif latch_enable = '1' then
> if (cpua_wr_not = '0') then
> outport <= cpua_data;
> else
> outport <= cpub_data;
> end if;
> end if;
>
> [...]
>
> If that still gives a single combinatorial equation then either...
> - Pick another part that knows about latches.
> - Rethink the real reason for your async requirement.
> - Talk to the Cypress rep about how to keep redundant terms. Like I said
> when I played with it, the VHDL signal attributes that they defined didn't
> include any sort of "don't touch this
Hi Kevin,
My part (CY37064) does support latches, and Warp uses them when I rewrite it
like in your example. But won't the hold time be badly violated, since the
latch_enable signal is delayed by an extra pass through a macrocell? E.g.
at the end of a CPU A write cycle, the "if (cpua_wr_not = '0')" disappears
"immediately" since it is implemented directly in product terms in front of
the latch, but the latch_enable edge comes one pass later.
I would prefer an asynchronous solution since I have some sensitive analog
stuff nearby, and I am worried by the noise from 28 flipflops running at
14 MHz. (Should I be that?) But since it is so non-trivial to get an
async solution right, I will go for a synchronous circuit like this, which
should be safe. It delays the write strobes two clocks so that it can
latch the data at the clock edge that comes between one and two clock
periods after the falling edge of the real cpuX_wr_not.
Thanks a lot for your advice.
Regards,
Karl Olsen
library ieee;
use ieee.std_logic_1164.all;
entity sync is
port (
reset : in std_logic;
clock : in std_logic;
cpua_wr_not : in std_logic;
cpua_data : in std_logic_vector (7 downto 0);
cpub_wr_not : in std_logic;
cpub_data : in std_logic_vector (7 downto 0);
outport : out std_logic_vector (7 downto 0)
);
end sync;
architecture sync_arch of sync is
signal cpua_wr_not1 : std_logic;
signal cpua_wr_not2 : std_logic;
signal cpub_wr_not1 : std_logic;
signal cpub_wr_not2 : std_logic;
begin
process (reset, clock)
begin
if reset = '1' then
cpua_wr_not1 <= '1';
cpua_wr_not2 <= '1';
cpub_wr_not1 <= '1';
cpub_wr_not2 <= '1';
elsif rising_edge(clock) then
cpua_wr_not1 <= cpua_wr_not;
cpua_wr_not2 <= cpua_wr_not1;
cpub_wr_not1 <= cpub_wr_not;
cpub_wr_not2 <= cpub_wr_not1;
end if;
end process;
process (reset, clock)
begin
if reset = '1' then
outport <= "00000000";
elsif rising_edge(clock) then
if cpua_wr_not1 = '0' and cpua_wr_not2 = '1' then
outport <= cpua_data;
elsif cpub_wr_not1 = '0' and cpub_wr_not2 = '1' then
outport <= cpub_data;
end if;
end if;
end process;
end sync_arch;
Article: 20952On Tue, 29 Feb 2000 21:14:53 GMT, "Number Cruncher" <michel.heuts@pandora.be> wrote: > We are doing some studywork and need titles about >recommended VHDL books. >So if you have read certain books and can recommend it give me a sign ... I very much like "VHDL for Logic Synthesis" by Andrew RUSHTON (2nd ed) which is reasonably cheap (by the standards of VHDL books) and is not widely recommended. "A designer's guide to VHDL" by Peter ASHENDEN gets the thumbs-up from many people, but I haven't read it myself. Jonathan BromleyArticle: 20953
A few books: Transaction Processing: Concepts & Techniques By Gray & Reuter Morgan Kaufmann Publishing Reliable Computer Systems: Design and Evaluation, Third Edition By Siewiorek & Swarz Atomic Transactions: In Concurrent and Distributed Systems by Lynch, Merritt & Weihl Morgan Kaufmann Publishing Fault Tolerance in Distributed Systems By Pankaj Jalote Tandem have (or had?) a thing called Tandem Information Manager (TIM) where you could get the Tandem documentation on CD for around $150. That might also be useful. Jan Mikkelsen janm@transactionsite.comArticle: 20954
Jonathan Bromley wrote: > On Tue, 29 Feb 2000 21:14:53 GMT, "Number Cruncher" > <michel.heuts@pandora.be> wrote: > > > We are doing some studywork and need titles about > >recommended VHDL books. > >So if you have read certain books and can recommend it give me a sign ... > > I very much like "VHDL for Logic Synthesis" by Andrew RUSHTON (2nd ed) > which is reasonably cheap (by the standards of VHDL books) and is > not widely recommended. > > "A designer's guide to VHDL" by Peter ASHENDEN gets the thumbs-up > from many people, but I haven't read it myself. _HDL Chip Design_ by Smith gets two thumbs up. :-) rkArticle: 20955
How does Quartus for APEX compare with the Xilinx tools version for Virtex. Principally I am interested in post Synopsys features. 1. Timing analysis reports 2. Fitter/Router 3. any experience with compile time for 1mil gate designs 4. timing driven compilation 5. Incremental compile 6. Testability tools Thanks -Wamsi Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20956
Hello guys, I have a few questions to you. First, I use the following components: 1. Active-HDL from Aldec 2. Xilinx Foundation Series 1.5 3. Wild-one AMS board 4. Visual C++ and Borland C++ I have been trying to do a synthesis for one of the example project provided. BUT I got the following message: ELBREAD: Warning: Component /GEN_BOARDS/WF1BOARD/U_PE0/U_IF/U_PADIntAck : IPAD not bound. I have noticed that it is the only Component (IPAD) without any Architectural description on ams4ksim.vhd package file.What you should I do? (do a dataflow 'bypass', i.e., just assign the output equal to the input) My other doubt is: can I use the DPMCs ports as direct communication ports between PEs themselve and the host; given I don't have any mezzanne memory card; Or those ports are wasted? Thanks, Javier Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20957
henry wrote: > i was wondering if a delay line could be made easily in an fpga and if so > are there any > limitations ie. max delay, max frequency. The main limitation is accuracy. A range exceeding three to one should be expected over process, temperature and voltage. Example: if the longest delay is 30 ns, the shortest would be less than 10 ns. A better way to handle the same problem is a digital delay of some sort. Perhaps a high frequency clock runs a counter for the number of cycles that makes up the delay. -- Phil HaysArticle: 20958
Hi, Take a look at part 2 of the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). Section 2.6 lists some recommended books. -- EdwinArticle: 20959
I am studying VHDL with Maxplus2 student 9.24 of Altera. but I can't design
RAM and
ROM. Although I don't have drive F:, Maxplus2 occurs error that is "Error:
Line 5: File
f:\maxw\code\exew\vhdl87\std\textio.vhd: Unsupported feature error: access
type is not supported"
Why? I don't understand.
Please correct my error.
below is my source.
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity myROM is
port( ROM_ADDR : in ieee.std_logic_1164.std_logic_vector(4 downto 0);
ROM_EN : in ieee.std_logic_1164.std_logic;
ROM_DATA : out ieee.std_logic_1164.std_logic_vector(7 downto 0) );
end myROM;
architecture behavior of myROM is
COMPONENT asyn_rom_32x8
-- pragma translate_off
GENERIC (LPM_FILE : string);
-- pragma translate_on
PORT (Address : IN ieee.std_logic_1164.STD_LOGIC_VECTOR(4 DOWNTO 0);
MemEnab : IN ieee.std_logic_1164.STD_LOGIC;
Q : OUT ieee.std_logic_1164.STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
BEGIN
rom: asyn_rom_32x8
-- pragma translate_off
GENERIC MAP (LPM_FILE => "myrom.mif")
-- pragma translate_on
PORT MAP (Address => ROM_ADDR(4 downto 0), MemEnab => ROM_EN, Q =>
ROM_DATA(7 downto 0));
END behavior;
Article: 20960On Tue, 29 Feb 2000 23:37:43 GMT, wamsi@my-deja.com wrote: >How does Quartus for APEX compare with the Xilinx tools version for Virtex. >Principally I am interested in post Synopsys features. >1. Timing analysis reports >2. Fitter/Router >3. any experience with compile time for 1mil gate designs >4. timing driven compilation >5. Incremental compile >6. Testability tools > >Thanks >-Wamsi > > >Sent via Deja.com http://www.deja.com/ >Before you buy. The new version of of Quartus works OK now There are some bugs with runtime errors But there is a workarround >Principally I am interested in post Synopsys features. I am using Mentor Leonardo as front end. it works fine . There are however some I/F mismatches between Leonardo and Apex resulting in protection errors , which can be avoided by using some work arround The Xilinx 2.1i has a simple interface : 16-bit look alike but it is apparently working fine and it does the job. >1. Timing analysis reports Is fine in both Xilinx and Altera >2. Fitter/Router works Fine on both of them >3. any experience with compile time for 1mil gate designs I only managed to fill 50% of Apex 400 K gates Chip As far as know Altera and Xilinx gate counting method can not be directly compared. Roughly one must divide the Xilinx gate count by factor 2 to get the same gate count. >5. Incremental compile It will come in the future >6. Testability tools Altera has a IP for logic analyzer working via JTAG Georg BerlinerArticle: 20961
See my comments below Georg Berliner wrote in message ... >On Tue, 29 Feb 2000 23:37:43 GMT, wamsi@my-deja.com wrote: > >>How does Quartus for APEX compare with the Xilinx tools version for Virtex. >>Principally I am interested in post Synopsys features. >>1. Timing analysis reports >>2. Fitter/Router >>3. any experience with compile time for 1mil gate designs >>4. timing driven compilation >>5. Incremental compile >>6. Testability tools >> >>Thanks >>-Wamsi >> >> >>Sent via Deja.com http://www.deja.com/ >>Before you buy. > > >The new version of of Quartus works OK now >There are some bugs with runtime errors But there is a workarround > >>Principally I am interested in post Synopsys features. >I am using Mentor Leonardo as front end. it works fine . There are >however some I/F mismatches between Leonardo and Apex resulting in >protection errors , which can be avoided by using some work arround > > >The Xilinx 2.1i has a simple interface : 16-bit look alike but it is >apparently working fine and it does the job. > >>1. Timing analysis reports >Is fine in both Xilinx and Altera Xilinx offers very good timing driven compile syntax, and accepts timing information from all 3 main Synthesis Vendors, namely Synopsys, Leonardo and Synplify > >>2. Fitter/Router >works Fine on both of them > >>3. any experience with compile time for 1mil gate designs >I only managed to fill 50% of Apex 400 K gates Chip I have designs that are using upto 99% of V1000's and routing and running at over 100MHz > >As far as know Altera and Xilinx gate counting method can not be >directly compared. >Roughly one must divide the Xilinx gate count by factor 2 to get the >same gate count. > Not quite, an Apex 20K400E is equivalent to a V600(E). For rough guidlines use the Logic Cell count, but this still doesn't take into account things like the Mult-And, and SRL16's which are VERY useful, and are again automatically inferred by the systhesis tools. >>5. Incremental compile > >It will come in the future Xilinx 2.1i already has the cabability and has always had it. In fact Exemplar have an app note that details how you can use it with Leonardo. > >>6. Testability tools >Altera has a IP for logic analyzer working via JTAG Xilinx has the Probe functionality in FPGA Editor, and has JTAG test tools. Probe is far more usable, as it doesn't have to be inserted into the design, and therfore altering the desing timing, and can be manipulated and re-downloaded in seconds.... My 2 cents...Article: 20962
javidiaz@my-deja.com wrote in message <89hu2l$om6$1@nnrp1.deja.com>... > >I have been trying to do a synthesis for one of the example project >provided. BUT I got the following message: >ELBREAD: Warning: >Component /GEN_BOARDS/WF1BOARD/U_PE0/U_IF/U_PADIntAck : >IPAD not bound. > >I have noticed that it is the only Component (IPAD) without any >Architectural description on ams4ksim.vhd package file.What you should >I do? (do a dataflow 'bypass', i.e., just assign the output equal to >the input) Try defining IPAD for synthesis by adding this to your code: -- synthesis translate_off library unisim; use unisim.vcomponents.all; -- synthesis translate_onArticle: 20963
> >>2. Fitter/Router > >works Fine on both of them > > So you mean Quartus fixed the bugs which plagued MAXPLUS-2 for timing driven compilation? I could never get even a 10K40 design to route using timing driven compilation...it would just go on for hours at no end! > >>3. any experience with compile time for 1mil gate designs > >I only managed to fill 50% of Apex 400 K gates Chip > I have designs that are using upto 99% of V1000's and routing and running at > over 100MHz > > Any experiance with APEX at over 130MHz speeds? How well do the Altera -3 speed grade compare with the Xilinx -6? I am told the Xilinx -6 can do a 16x16 multiply at 175MHz ... any such benchmarks for altera? > >As far as know Altera and Xilinx gate counting method can not be > >directly compared. > >Roughly one must divide the Xilinx gate count by factor 2 to get the > >same gate count. > > > Not quite, an Apex 20K400E is equivalent to a V600(E). For rough guidlines > use the Logic Cell count, > but this still doesn't take into account things like the Mult-And, and > SRL16's which are VERY useful, and are > again automatically inferred by the systhesis tools. > But does the 20K not have the ESB feature in it which can be used either as RAM or as combinatorial logic? By using it as combinatorial logic you can get a lot more gates than the equivalent Xilinx part. > >>5. Incremental compile > > > >It will come in the future > > Xilinx 2.1i already has the cabability and has always had it. In fact > Exemplar have an app note that details > how you can use it with Leonardo. > > > Are there ways to use the incremental compile in the verilog->synopsys->fpga tools design flow? > >>6. Testability tools > >Altera has a IP for logic analyzer working via JTAG > Xilinx has the Probe functionality in FPGA Editor, and has JTAG test tools. > Probe is far more usable, as > it doesn't have to be inserted into the design, and therfore altering the > desing timing, and can be manipulated > and re-downloaded in seconds.... > Do you mean that Xilinx actually has the testability function embedded in the chip and it just needs to be configured? -Wamsi Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20964
The best book (as far as I know) is: PCI System Architecture (fourth edition !!) Mindshare Inc (Tom Shanley, Don Anderson) ISBN 0-201-30974-2 Available through Amazon (usually stock). Mark keshav wrote: > > Hi all, > I would like to know which book is the Best for PCI. > > Thanks in advance, > Ken > > * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * > The fastest and easiest way to search and participate in Usenet - Free!Article: 20965
javidiaz@my-deja.com wrote: > Hello guys, > > I have a few questions to you. > > First, I use the following components: > 1. Active-HDL from Aldec > 2. Xilinx Foundation Series 1.5 > 3. Wild-one AMS board > 4. Visual C++ and Borland C++ > I haven't used the wild-one, but I can make these observations based on the wildforce and wildstar boards: Simulation is a whole lot easier using Modelsim because all the AMS macros have been set up for modelsim. For use with Aldec, you pretty much have to re-write all the macros. After spending too much time trying to get the board level sim running on Aldec I gave up and went to modelsim, where it pretty much ran the first time. Annapolis obscures the VHDL code with all kinds of cute things. That makes the translation to aldec a pain. One area Aldec seemed to have particular problems was with the entity and architecture definitions being in separate files in separate directories (Annapolis does that too much). I suspect that is the root of the warning you are getting. On the wildstar board, the DPMCs ports can be used as connections between the PEs if the mezzanine memories are not installed (or installed but not needed). To do this you use the SHUNT definitions of the port. > > I have been trying to do a synthesis for one of the example project > provided. BUT I got the following message: > ELBREAD: Warning: > Component /GEN_BOARDS/WF1BOARD/U_PE0/U_IF/U_PADIntAck : > IPAD not bound. > > I have noticed that it is the only Component (IPAD) without any > Architectural description on ams4ksim.vhd package file.What you should > I do? (do a dataflow 'bypass', i.e., just assign the output equal to > the input) > > My other doubt is: can I use the DPMCs ports as direct communication > ports between PEs themselve and the host; given I don't have any > mezzanne memory card; Or those ports are wasted? > > Thanks, > Javier > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20966
The best book (as far as I know) is: PCI System Architecture (fourth edition !!) Mindshare Inc (Tom Shanley, Don Anderson) ISBN 0-201-30974-2 Available through Amazon (usually stock). Mark keshav wrote: > > Hi all, > I would like to know which book is the Best for PCI. > > Thanks in advance, > Ken > > * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * > The fastest and easiest way to search and participate in Usenet - Free!Article: 20967
Hi all, I'm using a FIFO design based on Xilinx's synchronous FIFO with independent clocks, described in XAPP131. In this, it states that in the worst-case scenario (due to the asynchronous nature of the READ and WRITE clocks), the FULL and EMPTY flags would simply stay active one cycle longer and that this would _not_ generate an error. I have a simulation in which EMPTY goes low, indicating that there is data to be read from the FIFO, and then, due to the clock edges from the two different domains coinciding, the signal is forced into an unknown state, which could be high or low. In the case where the signal is actually interpreted as low, the FIFO would indicate that it was not empty, when in fact it might be. This causes a problem when trying to read data from the FIFO using the EMPTY signal as the read enable: for each occurence, and additional word may be inserted into the data stream. Does anyone know of a solution to this problem (apart from avoiding the use of multiple clock domains!). Cheers, Steve _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ Heterogeneous, Parallel & Reconfigurable Architectures Group School of Electronic & Electrical Engineering University of Birmingham, Edgbaston, Birmingham, B15 2TT e-mail: s.m.charlwood@bham.ac.uk tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291 Signal Processing & Imagery Department Defence Evaluation & Research Agency (DERA) DERA Malvern, St. Andrews Road, Malvern, Worcs., WR14 3PS e-mail: charlwood@signal.dera.gov.uk tel: +44 (0)1684-895452 (shared)/fax: +44 (0)1684-894389 _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/Article: 20968
HI ! You can download this information direct from Xilinx Web Site. I do not know the exact name, but the document is >1MByte... I got it there ... Ken Schmidt <kenschmidtNOSPAM@earthlink.net> schrieb in im Newsbeitrag: BNmt4.2460$pP5.45867@newsread1.prod.itd.earthlink.net... > Do you mind my asking you a couple of questions? First, what is your cost > target for your PCI Xilinx? Second, > are you planning on turning the Xilinx into a hard ASIC? > > Thanks, > --Ken Schmidt > Peerless Systems Corp. > > "Nicolas Matringe" <nicolas@dotcom.fr> wrote in message > news:38B56158.3C805F18@dotcom.fr... > > Hi > > I plan to buy a Xilinx PCI Core for a SpartanII device but I can't find > > any information about the core pinout. I'd like to start working on the > > PCB layout as soon as possible. > > The planned device is an XC2S50-FG256. > > > > Any help, link... is greatly appreciated > > > > Thanks in advance, > > Nicolas MATRINGE DotCom S.A. > > Conception electronique 16 rue du Moulin des Bruyeres > > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > > Fax 00 33 1 46 67 51 01 FRANCE > >Article: 20969
Simon wrote in message
<951925119.333.0.nnrp-11.9e9832fa@news.demon.co.uk>...
>javidiaz@my-deja.com wrote in message <89hu2l$om6$1@nnrp1.deja.com>...
>>
>>I have been trying to do a synthesis for one of the example project
>>provided. BUT I got the following message:
>>ELBREAD: Warning:
>>Component /GEN_BOARDS/WF1BOARD/U_PE0/U_IF/U_PADIntAck :
>>IPAD not bound.
>>
>>I have noticed that it is the only Component (IPAD) without any
>>Architectural description on ams4ksim.vhd package file.What you should
>>I do? (do a dataflow 'bypass', i.e., just assign the output equal to
>>the input)
>
>Try defining IPAD for synthesis by adding this to your code:
>
>-- synthesis translate_off
>library unisim;
>use unisim.vcomponents.all;
>-- synthesis translate_on
Simon,
that would make the library visible for simulation. it would be ignored for
synthesis.
a
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20970Hi, Steve - I've looked at XAPP131, but not a closely as you have, so I can't comment on the problem you're seeing. However, I have taken a (fairly) close look at a design done at QuickLogic by John Birkner and his associates, and it looks solid to me. Take a look at: http://www.quicklogic.com/support/anqn/qan25.pdf There's also a set of design files at: http://www.quicklogic.com/support/anqn/async.exe As I recall, I had to download their design software so I could read some of the schematics. As always, my comments come with the famous 30-second Usenet warranty... Take care, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 20971
Peter Alfke wrote in message <38B361E8.7378AF8A@earthlink.net>...
>It, the heck, is when you perform arithmetic serially, one bit at a
>time, LSB first, instead of on parallel words.
Peter,
that made my day!
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20972Yep. Engage brain... I tripped over the combination of the ams4ksim (simulation?) support stuff and what appeared to be a message from the Aldec simulator. As you point out, this won't help synthesis! Andy Peters wrote in message <89jh86$2jm$1@noao.edu>... >Simon wrote in message ><951925119.333.0.nnrp-11.9e9832fa@news.demon.co.uk>... >>javidiaz@my-deja.com wrote in message <89hu2l$om6$1@nnrp1.deja.com>... >>> >>>I have been trying to do a synthesis for one of the example project >>>provided. BUT I got the following message: >>>ELBREAD: Warning: >>>Component /GEN_BOARDS/WF1BOARD/U_PE0/U_IF/U_PADIntAck : >>>IPAD not bound. >>> >>>I have noticed that it is the only Component (IPAD) without any >>>Architectural description on ams4ksim.vhd package file.What you should >>>I do? (do a dataflow 'bypass', i.e., just assign the output equal to >>>the input) >> >>Try defining IPAD for synthesis by adding this to your code: >> >>-- synthesis translate_off >>library unisim; >>use unisim.vcomponents.all; >>-- synthesis translate_on > >Simon, > >that would make the library visible for simulation. it would be ignored for >synthesis. >Article: 20973
Hi guys,
thanks a lot!
regards,
Michel
Article: 20974Glad this thread started. I too am looking at Altera/Xilinx for a large design, about half million ASIC gates. What that equates to in fpga gates is up for debate. What I want to know is what kind of time am I looking at as far as place and routes go,. When I make small changes in the design do I have to start from "bare die" or can the existing layout be modified? Since it appears that Synopsys's FPGA express is the front end tool for HDL what kind of times should one expect for compiling? If you do respond please indicate the platform. Thanks Jerry wamsi@my-deja.com wrote: > How does Quartus for APEX compare with the Xilinx tools version for Virtex. > Principally I am interested in post Synopsys features. > 1. Timing analysis reports > 2. Fitter/Router > 3. any experience with compile time for 1mil gate designs > 4. timing driven compilation > 5. Incremental compile > 6. Testability tools > > Thanks > -Wamsi > > Sent via Deja.com http://www.deja.com/ > Before you buy.
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