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Dear all, Thank you very much for your valuable response. For those who may want to know, my thing is one of the slaves, and it has to communicate with the master who has to talk to many other slaves (components that I don't know what they are). I have to build the interface such that my thing knows when and what to respond when the master talks. I hope I could come out with something that works. =)Article: 80051
B. Joshua Rosen wrote: > I've put together a webpage on the performance of NCSim and Xilinx > tools on various systems, specifically a dual PIII, dual Xeon, Athlon 64 > 3400+ and an Athlon 64 3800+. > > http://www.polybus.com/linux_hardware/index.htm > A nice testbench but... 1. What's the amount of memory used on each system? 2. I think you miss-used the term "cpu-bound." Rather, they are all memory-bound computations. Had they been purely cpu-bound, the xeon machines might have won. The point that you really want to make is that the AMD cpus have on-chip memory controller and thus much less memory latency, which makes memory-intensive applications run much faster than Intel cpus. 3. You are comparing state-of-the-art AMD workstations with mediocre Intel servers. It's like comparing oranges with apples. Lastly, might I ask, are you affliated with AMD? -jzArticle: 80052
On Tue, 01 Mar 2005 01:58:18 +0100, Laurent Pinchart <laurent.pinchart@skynet.be> wrote: >> The computer must give you some strobe that indicates valid data. >> Do a worst-case analysis whether your FPGA clock guarantees capture >> within that window. >> Otherwise implement dirct data capture in the IOB and postpone the >> synchronization to 24 MHz. >> Always assume worst-case timing and phasing... > >The microcontroller has read, write and address strobe signals. The problem >is that the bus is asynchronous, which means that the FPGA might sample the >signals when they are not in a defined logic state. This implies >meta-stability problems if I remember my classes properly. What are the >basic guidelines to handle such problems ? The FPGA will do many things in parallel. One of the things it will do is a latch that's clocked by the appropriate edge from the AVR that is independent of any logic that's changed by the FPGA's clock. After the data is latched, it will set a "new data available" flag that's handled by the FPGA's clocked logic. -- Rich Webb Norfolk, VAArticle: 80053
No problem. In Frequency Synthesis mode (Fx output), it is only the output frequency (not the input frequency) that must be above 24 MHz... Peter AlfkeArticle: 80054
There was a descent thread of a PC104 (ISA) bus a while back. Try googling "Async logic in FPGAs" BTW, sometimes MPU's give bus timing with respect to the chip's clock input. - NewmanArticle: 80055
Peter, Spartan II doesn't have frequency synthesis mode or an FX output. This makes it difficult to use in the mode you suggest. Cheers, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:1109641138.681743.237750@z14g2000cwz.googlegroups.com... > No problem. In Frequency Synthesis mode (Fx output), it is only the > output frequency (not the input frequency) that must be above 24 MHz... > Peter Alfke >Article: 80056
Thanks Newman, I couldnt find anything on BFMs, but, I figured out what the problem with my design was. I was not tri-stating the bus while mimicing the processor functionality in my sim -MorpheusArticle: 80057
Pete wrote: > Hello > > Is there a Virtex4 FX eval board available yet? > We want to begin working with the on-chip Gig Ethernet mac. Howdy Pete, I don't know how available it is, but if you scroll down a ways on the page below (or search for ML40x), you'll find that just today they released a new copy of the eval platform user guide that mentions the ML403 - and it appears to have an XC4VFX12 (with two MAC's, but no Rocket I/O's). http://support.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1210768 In fact, the updated document has a link to an ML403 page, which lists the FX12 eval board as costing $500: http://www.xilinx.com/ml403 I also notice they trickled a few more numbers out onto the main V4 datasheet. Have fun, MarcArticle: 80058
Those are the subjets of the next webseminar. Over 700 engineers have signed up already. You can still join us this Tuesday (11:00 Pacific Time) when Dr. Howard Johnson explains the effects of ground bounce and crosstalk caused by simultaneously switching outputs. This is a highly technical talk (you will love it) with many screen shots taken with an 8 GHz scope, and with detailed comparisons of good and bad BGA packages. I give the short introduction and conclusion, but it is Howard's show. You may know him as the author of "High-speed Digital Design", the standard reference book found on many of our bookshelves (and benches). Howard is not only a well-known and respected expert in this treacherous field, he is also a lively speaker and an excellent teacher. Enjoy ! You can register for this live webseminar, and also for the two archived predecessors: http://www.xilinx.com/events/webcasts/tol/01feb05.htm Peter Alfke, Xilinx ApplicationsArticle: 80059
Laurent Pinchart wrote:
> As the bus is asynchronous, I suppose I'll have to over-sample the
signals.
> Could anyone direct me to some documentation about asynchronous bus
> interfaces for FPGAs ? The FPGA main clock runs at 24MHz, and I'd
like to
> know if this will be enough (the clock can be doubled using a DLL if
> needed).
>
> Thanks in advance for your help.
>
> Laurent Pinchart
This is a latched interface example that worked for me using Xilinx
FPGAs (Spartan II). Your design must be *extremely* careful about the
ALE, nRD and nWR signals (both in your board and in the FPGA - perhaps
buffering them adequately). I also registered carefully the internal
outputs of my design that interacted with the interface.
---8<---
/*
AVR bus interface
This module adapts the external AVR interface to the internal bus.
It latches the incoming address and generates the write and reset
signals.
*/
/*
+----+
AH -->| |--> A
AD <->| |--> DI
ALE -->| |<-- DO
nRD -->| |--> WE
nWR -->| |--> RST
CLK -->|> |
+----+
A: {AH, AD_address}
DI[7:0]: AD_data input
DO[7:0]: output to AD data
WE: write strobe
RST: reset (both nRD and nWR asserted)
*/
module avr(
CLK,
AH, AD, ALE, nRD, nWR,
A, DI, DO, WE, RST
);
parameter AH_size = 0;
input CLK; // not used in this implementation
input ALE, nRD, nWR;
input [((AH_size>0) ? AH_size-1 : 0):0] AH; // if AH_size == 0, AH is
unused
inout [7:0] AD;
output WE, RST;
output [AH_size+7:0] A;
output reg [7:0] DI;
input [7:0] DO;
reg [7:0] AL; // Address-low latch
assign A = (AH_size>0) ? {AH, AL} : AL; // Full address
wire nALE = ~ALE; // needed for XST to synthesize a latch for AL
wire RD = !nRD && nWR;
wire WR = !nWR && nRD;
assign WE = !ALE && WR;
assign AD = (!ALE && RD) ? DO : 'hz; // Memory read output drive
control
assign RST = !nRD && !nWR; // Reset signal generated by asserting nRD
and nWR simultaneously
always @(AD, nALE) if (!nALE) AL <= AD; // Address-low latch from AD
bus
always @(AD, WE) if (WE) DI <= AD;
endmodule
--->8---
Although the Atmega128 datasheet states that the interface is
asynchronous since there may be a skew between the external and
internal clocks, I have used it successfully in a synchronous fashion
feeding XTAL2 to a buffer (CKOPT set accordingly) and then to a FPGA
clock pin. However, I did not test this setting extensively so I can't
recommend it (read the quote below).
Regards.
--
PabloBleyerKocik /
pbleyer /"Ignorance simplifies ANY problem."
@embedded.cl / - R. Lucke
Article: 80060I did not test this setting extensively so I can't > recommend it (read the quote below). > > Regards. > > -- > PabloBleyerKocik / > pbleyer /"Ignorance simplifies ANY problem." > @embedded.cl / - R. Lucke > I got a good chuckle from your quote -NewmanArticle: 80061
16 of them are the RAMs which use the same site as luts. I imagine the last one is controlling the write enable to the RAMs. Open the gate level schematic view (HDL Analyst) and you should be able to find them all. ra_arce@yahoo.com wrote: > Hello, > > I am trying to get acquainted with the amount of logic it takes to > implement common structures to an FPGA. I built a simple VHDL 2x16bit > memory like follows and targeted it to a xc4013 device (which includes > block RAMs) > ---- > entity mem is > port( Dr: in std_logic_vector(15 downto 0); > wr: in std_logic; > clock: in std_logic; > clear: in std_logic; > Rr: out std_logic_vector(15 downto 0); > Ad: in std_logic_vector(1 downto 0) > ); > end mem; > ------------------------------------------------------------------ > architecture behv of mem is > type ram_type is array (0 to 3) of > std_logic_vector(15 downto 0); > signal tmp_ram1_r: ram_type; > begin > process(clock, clear) > begin > if clear = '1' then > -- do nothing > elsif (clock='1' and clock'event) then > if (wr='1') then > tmp_ram1_r(conv_integer(Ad))<= Dr; > end if; > end if; > end process; > Rr <= tmp_ram1_r(conv_integer(Ad)); > end behv; > ---- > > I use Synplify 7.0.3 to synthesize the design and get the following > resource usage report: > > Resource Usage Report for fft_2mem > > Mapping to part: xc4013xlabg256-07 > Cell usage: > GND 1 use > VCC 1 use > > I/O primitives: > IBUF 20 uses > OBUF 16 uses > > BUFG 1 use > > I/O Register bits: 0 > Register bits not including I/Os: 0 > > RAM/ROM usage summary > Single Port Rams (RAM16X1S): 16 > > Logic Mapping Summary: > FMAPs: 17 of 1152 (2%) > HMAPs: 0 of 576 (0%) > Total packed CLBs: 9 of 576 (2%) > (Packed CLBs is determined by the larger of three quantities: > Registers / 2, HMAPs, or FMAPs / 2.) > > What are the 17 FMAPs used for in this design? I though that Single > Port RAMs took care of everything that I am asking the entity to do > (write the 16-bit data to a specified address) . When I look into the > technology mapping view provided by Symplify and there is no evidence > of those 17 FMAPs. > > I will appreciate your help in this matter. > > Rafael Arce > Student, University of Puerto Rico >Article: 80062
It appears to me that you are trying to implement a wide, but shallow RAM, like 16 bits wide (in parallel) and 2 addresses deep. That's not the way the LUT-RAMs are organized. Each LUT is 1 bit wide and 16 addresses deep. So you can read or write one bit, but you can sequentially and randomly address 16 locations. Does that make things clarer ? Peter Alfke, Xilinx ApplicationsArticle: 80063
In article <bauUd.3513$Mw3.322@amstwist00>, "Dr Justice" <sorry@no.spam.wanted> wrote: > Jeremy and nospam, > > Thank you for the hints! > > This (non-FPGA legacy) clock is not high speed wrt propagation delays > (<20MHz), and the GATE is always of long duration, as in a few tens of > CLK_IN periods. > > I will test it just to observe and learn, but I shall also follow your > advice and investigate other ways to do things. > > DJ > > P.S. Apologies to Rob Barris for the hijack - I'm done now :) none needed. All the more useful stuff to learn from. It's not like I have to read all the replies in strict order :) RobArticle: 80064
Jason Zheng wrote: > 3. You are comparing state-of-the-art AMD workstations with mediocre > Intel servers. It's like comparing oranges with apples. I have some measurements with more current Xeon processors. Unfortunately I had only one not so state of the art Opteron to measure. These results were published by me in one local Mentor Graphics conference (these are only small part of the numbers). The simulations are done with Modelsim for a ~8Mgate chip (+all memories). The numbers are simulation time in seconds. RTL One CPU active Sun V880 UIII/900 3531 P4 Xeon 2.2/512k 2224 P4 Xeon 2.4/512k 2087 P4 Xeon 2.8/512k 1928 P4 Xeon 3.06/512k 1634 P4 Xeon 3.4EMT (32b) 1239 AMD Opteron 848(32b) 1584 RTL Both CPUs active Sun V880 UIII/900 3520 P4 Xeon 2.2 2540 P4 Xeon 2.4 2680 P4 Xeon 2.8 2650 P4 Xeon 3.06 2120 P4 Xeon 3.4EMT (32bit) 1450 AMD Opteron 848(32b) 1587 One thing that amazes me is that in Xeons even with RTL simulation the performance degrades very guickly. I guess with 4 processors Xeons degrade very badly. In Opterons there was no degradation to be seen. For the gate level simulations the results are almost identical, altough the dataset is 15-20x larger and simulation times for the same case are longer. Also if 64b mode was used Opteron became faster and Xeon EMT was little slower (very small differences compared to 32b mode tough). --KimArticle: 80065
"Pete" <padudle@sandia.gov> wrote in message news:4223bc0f$1_2@news3.es.net... > Hello > > Is there a Virtex4 FX eval board available yet? > > We want to begin working with the on-chip Gig Ethernet mac. > > Pete > > Looks like Memec will be releasing something at the 2005 Embedded Systems Conference later this month. __________________________________________________ * Memec Virtex-4 FX12 Development Kit The new FX12 kit provides embedded designers with a low cost development platform to explore the advanced features of the Virtex-4 FX family. Application development for the PowerPC and 10/100/1000 Ethernet MAC is made easy with the library of reference designs included in the kit. __________________________________________________ LinasArticle: 80066
Hallo to All i use Virtex2pro and edk 6.3i,ise 6.3i I have a problem with the read fifo. I created the fifo with edk wizard and its a part of IPIF. When you see the vhdl code belove i write in the FIFO(4 Register depth and 32 Bit wide) 4 datas 1,3,5,7. But when i read the registers with the software, i get only datas 1 and 7. The Datas between get not the fifo. Perhaphs had any the same problem? entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 1; C_IP_INTR_NUM : integer := 1; C_RDFIFO_DWIDTH : integer := 32; C_RDFIFO_DEPTH : integer := 4 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here switch1 : in std_logic; switch2 : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1); Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic; IP2RFIFO_WrReq : out std_logic; IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1); IP2RFIFO_WrMark : out std_logic; IP2RFIFO_WrRelease : out std_logic; IP2RFIFO_WrRestore : out std_logic; RFIFO2IP_WrAck : in std_logic; RFIFO2IP_AlmostFull : in std_logic; RFIFO2IP_Full : in std_logic; RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH)) -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end entity user_logic; -------------------------------------------------------------------------------- -- Architecture section -------------------------------------------------------------------------------- architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ---------------------------------------- -- Signals for read/write fifo example ---------------------------------------- type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE; signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; signal ip2wfifo_rdreq_cmb : std_logic; signal ip2rfifo_wrreq_cmb : std_logic; signal IP2RFIFO_Data_sig : std_logic_vector(0 to C_RDFIFO_DWIDTH-1):= (others => '0'); begin --USER logic implementation added here ---------------------------------------- -- Example code to read/write fifo -- -- Note: -- The example code presented here is to show you one way of operating on -- the read/write FIFOs provided by IPIF for you. There's a set of IPIC -- ports dedicated to FIFOs, beginning with RFIFO2IP_* or IP2RFIFO_* or -- WFIFO2IP_* or IP2WFIFO_*. Some FIFO ports are only available when -- certain FIFO services are present, s.t. vacancy calculation, etc. -- Typically you will need to have a state machine to read data from the -- write FIFO (in IPIF) or write data to the read FIFO (in IPIF). This code -- snippet simply transfer the data from the write FIFO to the read FIFO. ---------------------------------------- IP2RFIFO_WrMark <= '0'; IP2RFIFO_WrRelease <= '0'; IP2RFIFO_WrRestore <= '0'; --switch : process(switch1) --begin --if ( switch1 = '0' and switch1'event) then --go <= '1'; --end if; --if(nogo = '1') then -- go <= '0'; -- end if; --end process switch; FIFO_CNTL_SM_COMB : process( RFIFO2IP_full, RFIFO2IP_WrAck, fifo_cntl_cs, switch1) is variable counter : std_logic_vector(0 to 3):= "0000"; constant counter_stop : std_logic_vector(0 to 3):= "1111"; begin -- set defaults ip2rfifo_wrreq_cmb <= '0'; fifo_cntl_ns <= fifo_cntl_cs; case fifo_cntl_cs is when IDLE => if (switch1 = '0') then counter := (others => '0'); fifo_cntl_ns <= RD_REQ; end if; when RD_REQ => if ( RFIFO2IP_full = '0') then counter := counter + 1; IP2RFIFO_Data_sig(0 to 3) <= counter; ip2rfifo_wrreq_cmb <= '1'; fifo_cntl_ns <= WR_REQ; else ip2rfifo_wrreq_cmb <= '0'; fifo_cntl_ns <= IDLE; IP2RFIFO_Data_sig <= (others => '0'); end if; when WR_REQ => if ( RFIFO2IP_WrAck = '1' ) then fifo_cntl_ns <= RD_REQ; end if; when others => fifo_cntl_ns <= IDLE; end case; end process FIFO_CNTL_SM_COMB; FIFO_CNTL_SM_SEQ : process( Bus2IP_Clk ) is begin if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then if ( Bus2IP_Reset = '1' ) then IP2RFIFO_WrReq <= '0'; fifo_cntl_cs <= IDLE; else IP2RFIFO_WrReq <= ip2rfifo_wrreq_cmb; fifo_cntl_cs <= fifo_cntl_ns; end if; end if; end process FIFO_CNTL_SM_SEQ; IP2RFIFO_Data <= IP2RFIFO_Data_sig; ---------------------------------------- -- Example code to drive IP to Bus signals ---------------------------------------- IP2Bus_Data <= (others => '0'); IP2Bus_Ack <= Bus2IP_WrCE(0) or Bus2IP_RdCE(0); IP2Bus_Error <= '0'; IP2Bus_Retry <= '0'; IP2Bus_ToutSup <= '0'; end IMP;Article: 80067
Hi, I am Ranbir from eQURA Consulting. Guys, my client, which is a San Diego based wireless telecom giant. They were the original inventors of CDMA technology. They have recently set up a next gen design centre here in Bangalore, India. We are looking at various profiles, starting from frontend, backend to verification managers. If interested do contact me on +91 09845365740 ranbir@equra.comArticle: 80068
> Hi everybody, > > I have to interface a 8-bit microcontroller (ATMega128, running at 16MHz) to > a Xilinx Spartan-II FPGA. > > The FPGA will have several roles. It should be an address latch (the bus has > address/data multiplexed), an address decoder (to generate chip selects) > and a peripheral accessible through memory-mapped registers. > > As the bus is asynchronous, I suppose I'll have to over-sample the signals. > Could anyone direct me to some documentation about asynchronous bus > interfaces for FPGAs ? The FPGA main clock runs at 24MHz, and I'd like to > know if this will be enough (the clock can be doubled using a DLL if > needed). > > Thanks in advance for your help. > > Laurent Pinchart ALE is guaranteed to be valid during the AVR positive edge. I did an interface once for the mega103 which is harder, and that latched the data on the write strobe (open when low). Sample the write strobe with the FPGA clock. If it goes from low to high you have the valid data in the latch, and can copy this to a register clocked with your 24 Mhz Maybe it is easier if you could run your FPGA at 32 MHz and generate the AVR 16 MHz from an FPGA output An FPSLIC design would make life easier, but maybe it is too msall in FPGA and memory size. The new ones run at 40 Mhz. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic AB "Laurent Pinchart" <laurent.pinchart@skynet.be> skrev i meddelandet news:4223a767$0$30170$ba620e4c@news.skynet.be...Article: 80069
I am looking for an inexpensive logic analyzer and was considering the Ant16 but need more channels. I came across the LogicPort (34 channels, 500MHz timing, 200MHz state, USB powered, $379.00) but haven't found any reviews yet. It sounds like a great deal, but I don't want to buy without talking to someone who's tried it. Anyone heard of this product?Article: 80070
PS: Website is http://www.pctestinstruments.comArticle: 80071
On Tue, 01 Mar 2005 01:58:18 +0100, Laurent Pinchart <laurent.pinchart@skynet.be> wrote: >> The computer must give you some strobe that indicates valid data. >> Do a worst-case analysis whether your FPGA clock guarantees capture >> within that window. >> Otherwise implement dirct data capture in the IOB and postpone the >> synchronization to 24 MHz. >> Always assume worst-case timing and phasing... > >The microcontroller has read, write and address strobe signals. The problem >is that the bus is asynchronous, which means that the FPGA might sample the >signals when they are not in a defined logic state. This implies >meta-stability problems if I remember my classes properly. What are the >basic guidelines to handle such problems ? > >Laurent Pinchart Can't you run the MCU form a clock drived from the FPGA one - that way they won't be asynchronous.Article: 80072
"greenplanet" <greenplanet@hotmail.com> wrote in message news:<1109640048.457686.136820@f14g2000cwb.googlegroups.com>... > Dear all, > > Thank you very much for your valuable response. For those who may want > to know, my thing is one of the slaves, and it has to communicate with > the master who has to talk to many other slaves (components that I > don't know what they are). I have to build the interface such that my > thing knows when and what to respond when the master talks. I hope I > could come out with something that works. =) In this case: Some time ago I read somewhere on a phillips website that only one license is required per system. So if you have purchased a uC with I2C you can add an FPGA with an I2C slave to it without acquiring a new license. Try to find this with google. Kolja SulimmaArticle: 80073
Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>... > Since both processors starts at address 0, they will start to execute the same > initialization code. > You need to use a FSL port with different constant signals for each MicroBlaze. > The boot code would then read the FSL port to know which MicroBlaze it's. > Using this it would jump to the right code section. Dear Goran, sorry for the disturb, another question: how can you read and differentiate the constant signals if when executing a reading with mb_interface.h primitives on fsl the value on the FSL will be put in a variable that is shader if you are working with a shared data memory? The first processor that read will put its number in it and so you can't jump to the proper code... Any suggestion? Thank you very much!Article: 80074
"Benjamin Menküc" <benjamin@menkuec.de> writes: > If I was a fpga manufacturer I would put 1 or 2 people in this newsgroup > just for answering questions. That would be the most effective publicity > possible, I guess. Well, it seems better to have episodic contributions from enthusiastic engineers than the full-time presence of a marketing guy :-) MB -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)
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