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Messages from 75975

Article: 75975
Subject: Re: Custom Megafunctions in Quartus II
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 21 Nov 2004 10:23:30 +0100
Links: << >>  << T >>  << A >>

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:0NidnSxmY5AIMQLcRVn-3w@comcast.com...
> vadim wrote:
> > Is it possible to create a parametarizable Megafunction of my own
> > designs
> > in Quartus ? I would like to be able to add my own designs into
> > MegWizard Manager that can be instatiated within *.BDF files as
> > graphic entities with
> > configurable properties (similar to the LPM_XXX functions).
>
> Step one is to learn vhdl or verilog.
> Once you have working synthesis code it is
> easy to make a quartus graphic symbol for it.
> It is also easy to add generic options in the code.
> However, if the top ports change, you have to
> remake the symbol.
>
>
>         -- Mike Treseler

Hi Mike

your answer is not direct to the original posters question, agreed it may
actually be what he wanted to know, but - THERE IS NO WAY to make your own
MEGAWIZARD plugins that would show up in MegaWizard manager (not using only
Quartus) and that was the initial question.

I think that creating new megawizard functions is only possible with some
extra info/tools available only to AMPP members, not with using normal
Quartus.

Making a vhdl/verilog module and symbol for it is sure trivial, as you said
already

Antti













Article: 75976
Subject: Re: 18x18 Multipliers - Spartan III
From: Elder Costa <elder.costa@terra.com.br>
Date: Sun, 21 Nov 2004 07:54:16 -0200
Links: << >>  << T >>  << A >>
cristian wrote:
> I am doing some test with the Spartan III multipliers. I have tried
> the following simple code:
> 
> entity mac_ex is
>         generic (width: integer := 18) ;
>         port ( 	a,b	: in std_logic_vector (width-1 downto 0);
>                 final_res: out std_logic_vector((width*2)-1 downto
> 0));
> 
> end mac_ex;
> 
> architecture behave of mac_ex is
> begin 
> 
> final_res <= a * b;
> 		
> end;
> 
> The map report states that the above code will be implemented in 3
> (three) 18x18 multipliers when 'width' is equal to 18. Does any of you
> have an explanation for needing 3 18x18 multipliers?.
> 
> Note: when 'width' is equal to 17, just one 18x18 multiplier is
> needed. I am using the WebPack 6.2.03 version
> 
> thanks, 
> 
> cris

Just guessing here: have you included numeric_unsigned, right? Try 
numeric_signed. The Virtex/Spartan multipliers are signed ones.

Regards.

Article: 75977
Subject: Re: Altera chip identification
From: Carsten <xnews1@luna.kyed.com>
Date: Sun, 21 Nov 2004 11:35:38 +0100
Links: << >>  << T >>  << A >>
On Sun, 21 Nov 2004 01:47:59 +0100, "Fab" <moi@chezmoi.fr> wrote:

>hello all,
>
>it is not a question concerning FPGA but I could get the answer here:
>
>from old devices that went to trash I get two EPM7032VLC44-15 and I would 
>like to reuse them to build my own very low cost first protoboard for 
>developping wih VHDL.
>

I have tried the same with some old 7032's but the ones i have cant be
programmed by JTAG , and a programmer costs $300.
That was the end of my project with the 7032's 
 (@ltera does make som S versions that be programmed  with jtag , but
im not sure any of the 44 pins can)

Bottom line make sure that you can program them with the cheap jtag
cable before going further.

I ended up buying a xilinx cpld kit.

Carsten


Article: 75978
Subject: Re: Altera chip identification
From: "Fab" <moi@chezmoi.fr>
Date: Sun, 21 Nov 2004 13:52:14 +0100
Links: << >>  << T >>  << A >>
thank you for your answers I'll try with new components.

"Carsten" <xnews1@luna.kyed.com> a crit dans le message de news: 
ekr0q01pljt17cqn5b6s1ifjc004rj2dgg@4ax.com...
> On Sun, 21 Nov 2004 01:47:59 +0100, "Fab" <moi@chezmoi.fr> wrote:
>
>>hello all,
>>
>>it is not a question concerning FPGA but I could get the answer here:
>>
>>from old devices that went to trash I get two EPM7032VLC44-15 and I would
>>like to reuse them to build my own very low cost first protoboard for
>>developping wih VHDL.
>>
>
> I have tried the same with some old 7032's but the ones i have cant be
> programmed by JTAG , and a programmer costs $300.
> That was the end of my project with the 7032's
> (@ltera does make som S versions that be programmed  with jtag , but
> im not sure any of the 44 pins can)
>
> Bottom line make sure that you can program them with the cheap jtag
> cable before going further.
>
> I ended up buying a xilinx cpld kit.
>
> Carsten
> 



Article: 75979
Subject: Re: 18x18 Multipliers - Spartan III
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 21 Nov 2004 06:06:31 -0800
Links: << >>  << T >>  << A >>
Elder Costa wrote:

> Just guessing here: have you included numeric_unsigned, right? Try 
> numeric_signed. The Virtex/Spartan multipliers are signed ones.

Or better yet, numeric_std and
use the unsigned type explicitly.

             -- Mike Treseler

Article: 75980
Subject: Re: Custom Megafunctions in Quartus II
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 21 Nov 2004 06:26:38 -0800
Links: << >>  << T >>  << A >>
Antti Lukats wrote:


> I think that creating new megawizard functions is only possible with some
> extra info/tools available only to AMPP members, not with using normal
> Quartus.

True, but if I became a AMPP member, step one would be
to write some lpm style hdl code like this:

http://www.edif.org/lpmweb/more/vhdl.htm

An lpm module uses hdl strings to collect the GUI settings.

> Making a vhdl/verilog module and symbol for it is sure trivial, as you said
> already

Yes. And probably the best solution for the OP.

          -- Mike Treseler

Article: 75981
Subject: Re: Xilinx EDK - Unable to initialize BRAM in Simulation
From: swamydp@yahoo.com (swamy)
Date: 21 Nov 2004 09:44:30 -0800
Links: << >>  << T >>  << A >>
Hello Alan and Shalin

Thank you very much for your suggestions. PPC's reset vector
0xFFFFFFFC was not part of my plb_bram controller's address space.
Once I changed the address space the simulation files were generated
successfully. But I ran into another problem while simulating my
design. The following error messages were generated by Modelsim 5.7G
SE PLUS. Any pointers would be helpful.

# ** Error: (vsim-3043) system_init.v(9): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_00.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(10): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_01.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(11): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_02.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(12): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_03.

sytem_conf module has the defparams to initialise BRAM. I have tried
instantiating the top level system module in a testbench as mentioned
in one xilinx's support page :
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18769

But I did not have any success.

Thanks
Swamy





alann@accom.com (Alan Nishioka) wrote in message news:<a2db9b48.0411202011.69ff4570@posting.google.com>...
> Only block ram can be initialized during an fpga download.  If you are
> trying to run from external ram or cache, you have to download
> manually with a debugger or boot loader (and uncheck Mark BRAM for
> initialization, to continue implementation).
> 
> If you think you are running entirely from block ram, this probably
> means your linker script is bad (and is linking your program into
> memory that is not block ram).
> 
> Alan Nishioka
> alann@accom.com
> 
> 
> swamydp@yahoo.com (swamy) wrote in message news:<f43b3388.0411191512.70f321d9@posting.google.com>...
> > I am getting the following error message while building a simple
> > system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb
> > bridge. I am trying to use hardware simulation to verify my design.
> > Any help or pointers is greatly appreciated.
> > 
> > thanks
> > swamy
> > 
> > Initializing Memory...
> > Checking ELFs associated with PPC405 instance ppc405_0 for overlap...
> > 
> > 
> > Analyzing file hello/executable.elf...
> > ERROR:MDT - Elf file hello/executable.elf does not reside completely
> > within BRAM
> > 
> >    memory of processor ppc405_0.
> > ERROR:MDT - Uncheck the `Mark for BRAM Initialization` setting on the
> > software
> >    application generating this ELF.
> > INFO:MDT - This ELF file should be downloaded using a debugger, a
> > bootloader or
> >    an ACE file.
> > make: *** [implementation/download.bit] Error 1
> > Done.

Article: 75982
Subject: Xilinx EDK Simulation - Unresolved references
From: swamydp@yahoo.com (swamy)
Date: 21 Nov 2004 09:56:28 -0800
Links: << >>  << T >>  << A >>
Hello

I am trying to simulate verilog behavioural model of my PPC based
design using Xilinx EDK and Modelsim 5.7G SE PLUS simulator. I get the
following errors from defparams which are used to initialise the BRAM
blocks. Any help is greatly appreciated.

Thanks
swamy


# ** Error: (vsim-3043) system_init.v(9): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_00.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(10): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_01.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(11): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_02.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(12): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_03.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(13): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_04.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(14): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_05.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(15): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_06.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(16): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_07.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(17): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_08.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(18): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_09.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(19): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0A.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(20): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0B.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(21): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0C.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(22): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0D.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(23): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0E.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(24): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_0F.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(25): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_10.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(26): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_11.
#         Region: /system_conf
# ** Error: (vsim-3043) system_init.v(27): Unresolved reference to
'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_12.
#         Region: /system_conf

Article: 75983
Subject: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
From: austin <austin@xilinx.com>
Date: Sun, 21 Nov 2004 10:50:17 -0800
Links: << >>  << T >>  << A >>
Ian,

OK.  Time is on your side if you can wait.

Austin

Ian & Hilda Dedic wrote:
> Hi Austin
> 
> Obviously there is more margin if you're not pushing the transceiver so 
> hard, and being in the IC business I always take "real-soon-now" with a 
> large pinch of salt.
> 
> But in the timescales we're looking at it seems that there will be 
> solutions from both the biggest FPGA vendors, which always helps when 
> talking to customers who might exclusively use one or the other...:-)
> 
> Cheers
> 
> Ian
> 
> Austin Lesea wrote:
> 
>> Ian,
>>
>> There is a definite advantage to using a transceiver designed to work 
>> at 10 Gbs at 6.25 Gbs -- there is a lot of margin!
>>
>> Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them 
>> has to be just perfect, and pass the production BER test.  We are in 
>> production.  At 10 Gbs.
>>
>> And, you can see (and get delivery of) the Pro-X transceivers (today 
>> at the many RocketLab(tm) demo sites we have around the world).
>>
>> No "will", "more details under NDA", or any of that.  Just product, 
>> working, on the shelf, shipping NOW.
>>
>> Austin
>>
>> Ian Dedic wrote:
>>
>>> Thanks Dave -- it sounds like all our views agree here (see other
>>> mails in thread) that 5-6Gb/s as a next step avoids the issues which
>>> become difficult at 10-12Gb/s. Also given the number of channels
>>> available (from Altera and Xilinx) this will meet our requirement (up
>>> to about 100Gb/s total throughput).
>>>
>>> Ian

Article: 75984
Subject: Re: 18x18 Multipliers - Spartan III
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 21 Nov 2004 19:03:50 GMT
Links: << >>  << T >>  << A >>
On Sat, 20 Nov 2004 18:35:44 -0800, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote:
>What's the deal with 18 by 18 multipliers? Sheesh, is there anything more 
>useful they could have dropped into those silicon ares?

What's the deal with context free pointless posts? Sheesh, is there anything more
useful they could have done with internet bandwidth? (and spell checked "area")



Article: 75985
Subject: Re: Suggestion for Xilinx parallel port cable replacement.
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 22 Nov 2004 00:08:46 +0100
Links: << >>  << T >>  << A >>
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes:

> Petter Gustad <newsmailcomp6@gustad.com> wrote:
> : tony.p.lee@gmail.com (T Lee) writes:
> 
> : > How about creating a ethernet to jtag cable replacement?
> 
> : I've made my own Ethernet based programmer. Works on virtually any OS
> : and does not require a device driver. Also works with Xilinx Impact
> : and Altera Quartus.
> 
> Any chance to see the design or maybe buy units?

Unfortunately not yet. I'm currently making this programmer and system
into a product. I'm doing this on my spare time so I move slower than
anticipated, but I'm interested in getting in touch with beta testers
and other interested parties. My e-mail address can be found at 
http://www.gustad.com/pics/email.gif

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 75986
Subject: Spartan 3 output voltage level
From: "Lawrence Kiss" <lkiss80@hotmail.com>
Date: Sun, 21 Nov 2004 19:36:47 -0700
Links: << >>  << T >>  << A >>
I would like to integrate an 8051 microcontroller to a spartan 3 development 
board.  For input port I know I need to add a series resistor.  However for 
the output ports, I have read posts and app notes about using the 
quickswitch product.  The only problem is the package that they come in.  I 
have been wire wrapping most of my pins thus far and have not found any 
level shifting solutions that comes in a DIP package (that can be wire 
wrapped).  So here is my question:  instead of using the level shifter, can 
I just directly connect my Spartan 3 output port to an input port on my 8051 
and have a pull-up resistor to 5V on the same net?  My idea is that for low 
outputs I would just output a low logic level, but for a high output, I 
would create the VHDL code to output a high impedance (Z)...  Does anyone 
think this will work, or am I just crazy?

Thanks for any suggestions!

Larry 



 Posted Via Usenet.com Premium Usenet Newsgroup Services
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Article: 75987
Subject: Re: Spartan 3 output voltage level
From: "Bob" <nimby1_notspamm_@earthlink.net>
Date: Mon, 22 Nov 2004 02:53:26 GMT
Links: << >>  << T >>  << A >>
Just use the series resistor to limit the 8051->S3 high-level current.

In the S3->8051 direction, you don't need anything since LVTTL (3.3V supply)
has exactly the same logic thresholds as TTL (5V supply).

If you do need any pullups then connect them to 3.3V -- not 5V.

Bob


"Lawrence Kiss" <lkiss80@hotmail.com> wrote in message
news:41a15113$1_1@127.0.0.1...
> I would like to integrate an 8051 microcontroller to a spartan 3
development
> board.  For input port I know I need to add a series resistor.  However
for
> the output ports, I have read posts and app notes about using the
> quickswitch product.  The only problem is the package that they come in.
I
> have been wire wrapping most of my pins thus far and have not found any
> level shifting solutions that comes in a DIP package (that can be wire
> wrapped).  So here is my question:  instead of using the level shifter,
can
> I just directly connect my Spartan 3 output port to an input port on my
8051
> and have a pull-up resistor to 5V on the same net?  My idea is that for
low
> outputs I would just output a low logic level, but for a high output, I
> would create the VHDL code to output a high impedance (Z)...  Does anyone
> think this will work, or am I just crazy?
>
> Thanks for any suggestions!
>
> Larry
>
>
>
>  Posted Via Usenet.com Premium Usenet Newsgroup Services
> ----------------------------------------------------------
>     ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY **
> ----------------------------------------------------------
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Article: 75988
Subject: Re: microblaze: execute program from external memory
From: Shalin Sheth <Shalin.Sheth@xilinx.com>
Date: Sun, 21 Nov 2004 19:09:05 -0800
Links: << >>  << T >>  << A >>
Yongjie,

If this is for development purposes and everything will be run out of 
external memory then you have two options.

The first and easiest option is to simply change the Program Start 
Address that is passed to the compiler.  You can do this in EDK using 
the following steps:
1. In EDK click on the Applications/Software Projects tab.
2. Right click on the software project you are using and choose 'Set 
Compiler Options'
3. In the Program Start Address put the start address of your external 
memory in your MHS file.
4. Click 'OK' and recompile.
5. You can download the new elf file to the memory using XMD and execute 
or debug the code as you wish.

The second way and they most embedded developers do this is using a 
linker script, as it has already been suggested.  I would refer you to 
the Xilinx and GNU docs on writing linker scripts.

Cheers,
Shalin-

Yongjie Liu wrote:
> Hi,
> 
> I would like to run my program (too big) from external memory. I don't
> know how to configure my project in Xilinx Platform Studio to complie it
> correctly. What parameter should I modify or is there any configureation
> file I should creat?
> 
> Any suggestion or help is greatly appreiciated!
> 
> Thanks
> Yongjie

Article: 75989
Subject: Re: FPGA development board
From: nospam4ujack@yahoo.com (Jack)
Date: 21 Nov 2004 20:49:06 -0800
Links: << >>  << T >>  << A >>
Philip Freidin <philip@fliptronics.com> wrote in message news:<ru1vp05sqfsojarqd0b66b9e07hjerqrc7@4ax.com>...
> On 20 Nov 2004 05:51:34 -0800, nospam4u_jack@yahoo.com (Jack// ani) wrote:
> 
> >Hi all,
> >
> >I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to
> >implement my design on real Xilinx FPGA. Buying a professional
> >development board is really a costly affair, so I'm interested to
> >build my own FPGA board for learning purpose!
> >
> >Can anybody provide please provide me some help, where should I start
> >or suggest some pointer?
> 
> Here's a pointer:  http://www.fpga-faq.com/FPGA_Boards.shtml
> 
> Given that you are just getting started, I think you would be best
> off buying your first board, rather than getting distracted on
> building a board (which given your cost sensitivity, is going to be
> more expensive that buying one of the low cost boards).
> 
> Most of the cheap boards use chips that are supported by the free
> software from the FPGA vendors.
> 
> I would recommend you look at something with a Xilinx Spartan-2 or
> Spartan-3 chip.
> 
> Philip
> 
> 
> 
> 
> ===================
> Philip Freidin
> philip.freidin@fpga-faq.com
> Host for WWW.FPGA-FAQ.COM

Thanks everyone.

Article: 75990
Subject: VLSI professional at NASA
From: muthusnv@yahoo.co.in (Muthu)
Date: 21 Nov 2004 22:52:58 -0800
Links: << >>  << T >>  << A >>
Hi,
How to be part of NASA as a VLSI Design engineer?

Regards,
Muthu

Article: 75991
Subject: Re: FPGA development board
From: nospam4u_jack@yahoo.com (Jack// ani)
Date: 22 Nov 2004 00:39:38 -0800
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<419f7a75$0$2292$cc9e4d1f@news-text.dial.pipex.com>...
Hi Leon,

I saw this page http://www.geocities.com/leon_heller/pld_starter.html,
quite interesting. Now I think getting started with CPLD is not a bad
idea. As you said there, FPGA is probably not ideal for learning PLD,
so your CPLD proto board is pulling my attention!

I have few questions regarding your XC9536 proto board,

1.Is XC9536 still available, I mean to say(in case) they are obsolete
by now?

2.How may time can I reprogram it, since it is flash memory based? Is
there any equivalent SRAM based device, so that I can program it again
and again?

3.I need a Xilinx parallel download cable to program it, right?

4.What is frequency of crystal oscillator? Which sort to crystal
oscillator is this one, having six pins(as shown in the layout)? Till
now I dealt only two pin crystals!

5.Sorry to say, your PCB layout is missing some tracks of PLCC socket.
Can you please upload it again.

Thanks a lot.

Article: 75992
Subject: Re: Spartan 3 output voltage level
From: "Peter Seng" <NOSPAM@seng.de>
Date: Mon, 22 Nov 2004 09:56:45 +0100
Links: << >>  << T >>  << A >>

"Lawrence Kiss" <lkiss80@hotmail.com> schrieb im Newsbeitrag
news:41a15113$1_1@127.0.0.1...
> I would like to integrate an 8051 microcontroller to a spartan 3
development
> board.  For input port I know I need to add a series resistor.  However
for
> the output ports, I have read posts and app notes about using the
> quickswitch product.  The only problem is the package that they come in.
I
> have been wire wrapping most of my pins thus far and have not found any
> level shifting solutions that comes in a DIP package (that can be wire
> wrapped).  So here is my question:  instead of using the level shifter,
can
> I just directly connect my Spartan 3 output port to an input port on my
8051
> and have a pull-up resistor to 5V on the same net?  My idea is that for
low
> outputs I would just output a low logic level, but for a high output, I
> would create the VHDL code to output a high impedance (Z)...  Does anyone
> think this will work, or am I just crazy?
>
> Thanks for any suggestions!
>
> Larry
>
>
>
>  Posted Via Usenet.com Premium Usenet Newsgroup Services
> ----------------------------------------------------------
>     ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY **
> ---------------------------------------------------------- 
>                 http://www.usenet.com



Why not running the 8051 at 3V3 ???
There are lot of 3V3 compatible 8051 MCUs / CPUs ....


with best regards,

Peter Seng


#############################
SENG digitale Systeme GmbH
Im Bruckwasen 35
D 73037 Goeppingen
Germany
tel  +7161-75245
fax  +7161-72965
eMail  p.seng@seng.de
net  http://www.seng.de
#############################



Article: 75993
Subject: Re: Spartan 3 output voltage level
From: "Lawrence Kiss" <lkiss80@127.0.0.1:7501>
Date: 22 Nov 2004 02:59:10 -0600
Links: << >>  << T >>  << A >>

I am taking an embedded systems course.  We had to buy a parts kit that was
available only from the prof.  The semester is coming to a close within 2
weeks, and everyone is trying to finish their final (open ended) projects.
 No time to convert everything that I have been doing all semester to 3.3.
 Thanks for the suggestion though.

"Peter Seng" <NOSPAM@seng.de> wrote:
>
>"Lawrence Kiss" <lkiss80@hotmail.com> schrieb im Newsbeitrag
>news:41a15113$1_1@127.0.0.1...
>> I would like to integrate an 8051 microcontroller to a spartan 3
>development
>> board.  For input port I know I need to add a series resistor.  However
>for
>> the output ports, I have read posts and app notes about using the
>> quickswitch product.  The only problem is the package that they come in.
>I
>> have been wire wrapping most of my pins thus far and have not found any
>> level shifting solutions that comes in a DIP package (that can be wire
>> wrapped).  So here is my question:  instead of using the level shifter,
>can
>> I just directly connect my Spartan 3 output port to an input port on my
>8051
>> and have a pull-up resistor to 5V on the same net?  My idea is that for
>low
>> outputs I would just output a low logic level, but for a high output,
I
>> would create the VHDL code to output a high impedance (Z)...  Does anyone
>> think this will work, or am I just crazy?
>>
>> Thanks for any suggestions!
>>
>> Larry
>>
>>
>>
>>  Posted Via Usenet.com Premium Usenet Newsgroup Services
>> ----------------------------------------------------------
>>     ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY **
>> ---------------------------------------------------------- 
>>                 http://www.usenet.com
>
>
>
>Why not running the 8051 at 3V3 ???
>There are lot of 3V3 compatible 8051 MCUs / CPUs ....
>
>
>with best regards,
>
>Peter Seng
>
>
>#############################
>SENG digitale Systeme GmbH
>Im Bruckwasen 35
>D 73037 Goeppingen
>Germany
>tel  +7161-75245
>fax  +7161-72965
>eMail  p.seng@seng.de
>net  http://www.seng.de
>#############################
>
>



----== Posted via Newsfeed.Com - Unlimited-Uncensored-Secure Usenet News==----
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Article: 75994
Subject: Modelsim library problem
From: dgleeson-2@utvinternet.com (Denis Gleeson)
Date: 22 Nov 2004 02:51:37 -0800
Links: << >>  << T >>  << A >>
Hello

Im using Modelsim XE 5.5e for simulation.
All was going well until I attempted to include delay information in
my simulation by bringing the .sdf from my synthesis tool.

Now I just get # ** Fatal: ERROR: SDF files require Xilinx primitive
library

Now in the Load Design dialog box of Modelsim in the Libraries tab I
have added all 4 libraries supplied with the modelsim package
simprims_ver, unisims_ver, aim_ver and uni9000. Still no luck. Just
get the same message.

The error message is very limited and suggests to me that the package
is not seeing any library files even though I am including them.

Can anyone give me pointers on where I could start to find the problem
with this.


Many thanks for any suggestions

Denis

Article: 75995
Subject: Re: RocketIO success?
From: "Adarsh Kumar Jain" <adarsh.jain@cern.ch>
Date: Mon, 22 Nov 2004 12:39:22 +0100
Links: << >>  << T >>  << A >>
Hi Paul,
I am at CERN, Geneva. We recently successfully tested a VME 9U Board which
has 9 V2Pros and 3 Alteras.
We are using all 8 Rocket IOs present on the V2P7s in each of them except
for the last one in which we only use 6 of them (big deal ;) )
We are running the Xilinxs at about 80-85% of resource utilization(logic)
and use about 60-70% of Block RAMs. This will go further up as we proceed
with the production of the Board and we are confident that our board will
eventually do what it is supposed to !
Of course there were problems, some on the Xilinxs, some on the board. But
most of the problems (or rather our problems) we traced to the Refernce
Clock (mostly jitter). I was myself new to the Rocket IOs when i started
this project and so
there was a lot of trial and error. But eventually we did make the board
work.
We have an article in the current Xcell issue:
http://www.xilinx.com/publications/xcellonline/xcell_51/xc_particle51.htm

If there are specific questions, then maybe we can try to answer them
Good luck,
Adarsh

"Paul Smith" <ptsmith@nospam.indiana.edu> wrote in message
news:cnl7em$9q3$1@hood.uits.indiana.edu...
>
> I'm considering the V2pro series for several projects.
>
> I've heard from someone with experience that there are problems with the
> RocketIO when a lot of other things are happening on the chip.  This is
> thought to be a problem with the V2pro package.  The evaluation boards
> only implement the RocketIO without a lot of other things going on in
> the part.
>
> Can anyone provide an example of a successful RocketIO implementation on
> a real board that also has a lot of parallel IO and heavy use of
> internal block RAM, etc?
>
> Paul Smith
> Indian University Physics
>



Article: 75996
Subject: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
From: "Elmo" <ikeepthespiritalive@freenet.de>
Date: Mon, 22 Nov 2004 13:08:51 +0100
Links: << >>  << T >>  << A >>
Hello,

last week I started the development and design of a PCB with an FPGA (Xilinx
Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in
mind the most obvious design rules, i.e. combining the adress lines and
separating the data and strobe (DQS) lines. But now I came across the many
other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE,
etc. My first idea was to also combine them for both modules. Lately I
wondered if I am right with that assumption?

Regards, Elmo



Article: 75997
Subject: Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Mon, 22 Nov 2004 23:38:42 +1100
Links: << >>  << T >>  << A >>
On Mon, 22 Nov 2004 13:08:51 +0100, "Elmo"
<ikeepthespiritalive@freenet.de> wrote:

>Hello,
>
>last week I started the development and design of a PCB with an FPGA (Xilinx
>Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in
>mind the most obvious design rules, i.e. combining the adress lines and
>separating the data and strobe (DQS) lines. But now I came across the many
>other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE,
>etc. My first idea was to also combine them for both modules. Lately I
>wondered if I am right with that assumption?

From the P.O.V. of functionality, that depends on what you want to do.
Will you need to write to individual bytes?  Will you want to be able
to precharge (or whatever) one of the chips while you are performing a
different operation on the other chip?


Signal integrity implications of pairs of SDRAMs (DIMMs, actually) are
discussed in this recent c.a.f thread:
http://groups.google.com/groups?threadm=cm7ebv%243e3%241%40news.cs.tu-berlin.de

Regards,
Allan

Article: 75998
Subject: Re: Xilinx S3 IO during programming latches Cypress FX2 Reset
From: langwadt@ieee.org (Lasse Langwadt Christensen)
Date: 22 Nov 2004 04:40:00 -0800
Links: << >>  << T >>  << A >>
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10pvvkff7o3g16b@corp.supernews.com>...
> Got a strange problem here.  When I power up, the platform PROM starts up 
> the Spartan 3 OK and a Cypress FX2 (USB2).  However when I shoot another 
> program down through the JTAG cable, there is a slight dip in the FX2 reset 
> pin, which I connected to a Spartan IO, from about 3.3V to 2.2V.  This 
> slight dip in voltage seems to hose the FX2 chip and its oscillator will not 
> come back on.  I thought that the IOs during the programming cycle of the 
> Spartan 3s were high impedance and I shouldn't see such a dip.
> 

AFAIK, IOs are pull-down/pull-down/None during configuration based on
configuration options, Mode pins and maybe hotswap-enable, default
is pull-down. 

pull-down in FPGA and pull-up in FX2 could explain 2.2V ....

-Lasse

Article: 75999
Subject: Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
From: "Elmo" <ikeepthespiritalive@freenet.de>
Date: Mon, 22 Nov 2004 13:48:53 +0100
Links: << >>  << T >>  << A >>
Hello and thanks Allan!

I just browsed through the recent thread. But let me pick up your question,
anyhow: Yes, I want to be able to write to individual bytes and precharge
one of the chips while I am performing a different operation on the other
chip, i.e. I want one DIMM to load some data into memory and the other one
to read data from the memory to any sort of interface. What are the aspects
I must consider in connecting the DIMMs???

Regards,     Elmo






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