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If you need operation to -25C, do note that a "commercial" 0 to +85C part will certainly function down to -25C (the silicon is usually exactly the same these days) and at -25C it will go like a bat out of hell. >Does anyone know of a manufacturer of a 22V10 with guaranteed >combinational propagation delay 5ns or better for the full INDUSTRIAL >temperature range? > >All the devices I've looked at so far are limited to COMMERCIAL >temperature range. The fastest industrial grade devices appear to be >7.5ns (several sources). -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13676
Peter wrote: > If you need operation to -25C, do note that a "commercial" 0 to +85C > part will certainly function down to -25C (the silicon is usually > exactly the same these days) and at -25C it will go like a bat out of > hell. > As was mentioned before: Low temperature is not an issue. The problem is the extra 5% of lower Vcc ( 4.5 instead of 4.75) which costs about 5% in speed, plus the extra 15 degrees C, which cost about another 5% in speed. Plus the fact that the parts are not tested at the elevated temperature. Perhaps it may be worth mentioning: Responsible IC manufacturer production-test ALL their devices at the guaranteed highest temperature. That is 100% production testing. Not sampling. Xilinx heats all parts to 85 degrees C for commercial, 100 degrees C for industrial, and then ac tests them at a voltage that is a tad below the guaranteed min Vcc. I will spare you a long soapbox about the impossibility of guaranteeing the performance parameters of any programmable part at any specified AMBIENT temperature. That's why we call out the junction temperature only. Peter Alfke, Xilinx ApplicationsArticle: 13677
Peter Alfke <peter@xilinx.com> wrote: >Peter wrote: > >> If you need operation to -25C, do note that a "commercial" 0 to +85C >> part will certainly function down to -25C (the silicon is usually >> exactly the same these days) and at -25C it will go like a bat out of >> hell. >> > >As was mentioned before: >Low temperature is not an issue. So why don't you spec 'commercial' parts at -10 or -20? Cheers Terry...Article: 13678
Terry Harris wrote: > Are there any 95xx industrial parts which will run a state machine at > 80MHz? (without restricting he fit to local feedback?). > > Cheers Terry... I checked with CPLD Applications. The XC9536XL-5 ( not the future fastest -4) can implement a state machine at 135 MHz. If you have to "borrow" terms, that costs another 0.4 ns. The data sheet is on our web site http://www.xilinx.com/partinfo/9536xl.pdf Looks like a good fit. Peter Alfke, Xilinx ApplicationsArticle: 13679
I know you can do it, I did it in the past....but I don't remember the steps...any ideas? Thanks, Austin Franklin darkroom@ix.netcom.comArticle: 13680
This may not help you, but I did this several years ago using the XABEL compiler in the old Xilinx tools. That spit out an xnf file which I converted to a wir file using xnf2wir. If you don't have the netlist translator you need it might be easier to just write a model for the PAL in VHDL (assuming Viewsim reads VHDL). Bob S. Austin Franklin wrote: > > I know you can do it, I did it in the past....but I don't remember the > steps...any ideas? > > Thanks, > > Austin Franklin > darkroom@ix.netcom.comArticle: 13681
Peter Alfke <peter@xilinx.com> wrote: >Terry Harris wrote: > >> Are there any 95xx industrial parts which will run a state machine at >> 80MHz? (without restricting he fit to local feedback?). >> >> Cheers Terry... > > I checked with CPLD Applications. >The XC9536XL-5 ( not the future fastest -4) can implement a state >machine at 135 MHz. >If you have to "borrow" terms, that costs another 0.4 ns. > >The data sheet is on our web site > >http://www.xilinx.com/partinfo/9536xl.pdf > >Looks like a good fit. But only the -10 is available in industrial according to the data sheets. The data sheet specs the -5 at 178MHz fSYSTEM so where does the 135 above come from? The -10 looks like it would do 100MHz but maybe I am missing something. Cheers Terry...Article: 13682
Bob, Thanks, that is one way. I finally found the program, it is called 'pla2view'. It will output schematic, VHDL, wir...pretty much anything. My only problem now, is getting the simulator to agree the flops are reset on powerup (according to the 22V10 spec...), and there is no GR or GSR line in a Xilinx... Regards, Austin Bob Sefton <rsefton@nextstate.com> wrote in article <3679C47F.430F8332@nextstate.com>... > This may not help you, but I did this several years ago using the > XABEL compiler in the old Xilinx tools. That spit out an xnf file > which I converted to a wir file using xnf2wir. If you don't have > the netlist translator you need it might be easier to just write a > model for the PAL in VHDL (assuming Viewsim reads VHDL). > > Bob S. > > Austin Franklin wrote: > > > > I know you can do it, I did it in the past....but I don't remember the > > steps...any ideas? > > > > Thanks, > > > > Austin Franklin > > darkroom@ix.netcom.com >Article: 13683
--------------2DB688CB12272829F720BC9F Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit FPGA Downloader for Altera FPGA/EPLD - ONLY $75.00 Works with any voltage from target board 1.8 V - 5.5 V Replaces Altera ByteBlaster and ByteBlaster MV downloader You will never need another downloader Please visit us at: http://welcome.to/nefdesign.com Sincerely, NEF Design, Inc. --------------2DB688CB12272829F720BC9F Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <b>FPGA Downloader for Altera FPGA/EPLD - <u>ONLY $75.00</u></b> <p>Works with any voltage from target board <b>1.8 V - 5.5 V</b> <br>Replaces Altera ByteBlaster and ByteBlaster MV downloader <br>You will never need another downloader <p>Please visit us at: <b><A HREF="http://welcome.to/nefdesign.com">http://welcome.to/nefdesign.com</A></b> <p>Sincerely, <p>NEF Design, Inc. <br> <br> </html> --------------2DB688CB12272829F720BC9F--Article: 13684
Steven Derrien wrote:
> I'm having serious trouble with a constrained clock IOB placement on a
> XC4010e device.
> NET clock1 LOC=p4;
> NET clock1 LOC=p162;
^ typo? clock2?
First, what package? Different packages have the clock driver pins in
different places. P4 is a primary clock pin for the hq208 and pq208,
but is not a clock pin for other packages.
Second, have you tried not constraining the pins and let map find pins
for your clocks? While it might not pick the pins you want, perhaps the
pins it picks might help you understand the problem?
> ERROR:x4kma:81 - Primary clock buffer BUFGS symbol "U160" (output
I think a BUFGS maps to a SGCK buffer (like P204 in an hq208). A BUFG
or a BUFGP or a BUFGLS all should map to a PGCK. I don't know why
Synopsys FPGA compiler is picking a BUFGS rather than a BUFG.
Good luck.
--
Phil Hays
"Irritatingly, science claims to set limits on what
we can do, even in principle." Carl Sagan
Article: 13685Mikeandmax wrote: > >Tim wrote >> >>Does anyone know of a manufacturer of a 22V10 with guaranteed >>combinational propagation delay 5ns or better for the full INDUSTRIAL >>temperature range? > >Lattice makes GAL22V10s with 4ns speed in commercial grade, >but we don't offer industrial grade at that speed. Yup. Found that's true of all -5 and -4 products in my searches. >Why? Industrial ratings require both thermal and operating >voltage ranges that make it difficult to guarantee the speed. Understood. Incidentally, apologies for omitting the requirement that the device be 5V type. >I would suggest talking to the local Lattice guys about >possibly getting the factory to work on an 'ASPEC' device >for you, if you're willing to work with tighter voltage >swings they may be able to help. I'll certainly look into this. >... To satisfy the interest of various others (and thanks for all the suggestions - much appreciated), the application is a simple (simplistic, even) requirement to soak up a total of 5 SSI packages plus one multiple latch IC. If it wasn't for needing to invert the clock for negative edge clocking it would fit into a 16V8 (or one of a number of other 20 pin packages). As is not at all uncommon, I don't *NEED* FPGA or CPLD complexity this time. The design is not amenable to targetting one such and mopping up lots of other functionality, and other issues mean this isn't a good idea anyway. The design doesn't use even 10% of 22V10 resources. Most of the timing is relatively relaxed, but there are two combinational outputs which absolutely must respond within 5ns of relevant input changes. Discrete SSI gates can give me that, with FULL INDUSTRIAL temperature range. So far, I can't find a 22V10 that can. From experience, I'm sure that I could use a commercial 4ns IC and it would work fine (probably turning in typical measured times well below 4ns) - until the five thousandth unit happened to find itself in an extreme environment, at which point the unmentionable hits the fan in a BIG way. One approach under consideration is a couple of those individual-gate SOT packages for the fast-response signals, then an industrial 7.5ns PLD for the rest. Broadening the issue a bit, most of my design work is on relatively small-scale designs. In these applications I find it extremely frustrating that, except for Phillips XPLA, there's been nothing really new in not-many-pins devices for a very long time. What I'd love to see is a 16 pin IC, with at least two pins carrying clocking signals, and ALL pins having versatile I/O macrocells. Sort of 14V14. Or maybe 28V14 if every macrocell included a buried register. A 20-pin version would be 18V18/36V18. But all developments these days are in Mega this that and the other. Certainly useful in a very wide range of applications, but is the small-footprint IC really a dead market for new programmable logic devices? -- Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK The University is not responsible for my opinionsArticle: 13686
Ken, I don't agree with your statement on Altera silicon being better for filters and other pipelined functions. Altera uses 'non segmented' routing in its architectures, whereas Xilinx is segmented. In Altera it is very difficult to lock down a function to a particular area of the die. In Xilinx you can RPM (Relationally Placed Macro) elements of your design - and this is automatic if you use CoreGen or Logiblox. I taken a large amount of Altera filter designs and converted them into Xilinx and proved that in Altera (more obvious in the larger devices) the non segmented routing causes a very obvious performance tradeoff. All Xilinx cores are produced to ensure best overall system speed as opposed to a 'prep benchmark'. As for Altera's Place and Route advantage. Well that is water under the bridge. M1.5i is much faster than MPII, for all timing driven runs, and it does pretty well without 'timing driven'. As for Virtex. Well even I am staggered. 31 Tap 10 Bit Symmetrical Fir - Full precision ie no truncation or rounding. 130MHz sample rate in 10 Mins compile time on a 166MHz Pentium Laptop!!! I hope this helps... Dave Hawke, Xilinx Applications. Ken Coffman wrote in message <759dqv$utd$1@brokaw.wa.com>... >I don't consider Foundation tools to be usable. What is your desired design >entry method? Foundation might be okay for schematics, I wouldn't know >because I've never used a schematic to design an FPGA. The combination of >Synplicity Synplify or Exemplar Leonardo for Verilog or VHDL design with the >Xilinx Design Manager for place and route works very well. Altera has simple >silicon, so their software is correspondingly simple and easy, and works >very well. If you're looking for all-in-one vendor software that works well, >MAXPLUS2 is great. For silicon I'd say Altera works well for datapath type >functions (filters and other pipelined functions) and Xilinx works well for >more random and mixed logic. If you need to lock down your pins and create a >circuit board before the FPGA design is done, then you don't want to use >Altera. >glenn kubota wrote in message <364E13BF.5C4EB701@earthlink.net>... >>i've got a project where i'm looking at using CPLDs from either Altera >>or Xilinx. it looks like they both have chips that will fit the bill. >>my question, however, is what're the relative pros and cons of Xilinx >>Foundation vs. Altera Max Plus? what's easier to learn? what will serve >>me better in the future? >> >>thanks, >>glenn k. >> >> > >Article: 13687
You may instead look at the atmel serial PROM for configuring FPGA's.
They are ISP, and they have some application notes on this,
http://www.atmel.com
I am looking into using an XC9572 and a standard data flash prom. I let
the CPLD handle the program, done, init, din and cclk. The dataflash can
be programmed in circuit, as it has a simple 2 or 4 wire interface. -and
is inexpensive....
BBj//
--
+-------------------------------------------------+
| Bjerre Technology / Bo Bjerre |
| Instruments for Applied Geophysics |
| Phone (+45) 7669 5555 Fax (+45) 7669 5556 |
| E-mail "Bo@Bjerre-Technology.dk" |
+-------------------------------------------------+
Article: 13688Ken Coffman wrote: > I don't consider Foundation tools to be usable. What is your desired design > entry method? Foundation might be okay for schematics, I wouldn't know > because I've never used a schematic to design an FPGA. The combination of > Synplicity Synplify or Exemplar Leonardo for Verilog or VHDL design with the > Xilinx Design Manager for place and route works very well. Altera has simple > silicon, so their software is correspondingly simple and easy, and works > very well. If you're looking for all-in-one vendor software that works well, > MAXPLUS2 is great. While I wouldn't go as far as saying foundation is unusable, there are many people using it quite successfully. It is not, however, what I would consider a professional design package compared to the more expensive alternatives. It is also very awkward for controlling the design to obtain higher performance and/or density. For the occasional user who has not been 'spoiled' by using better, it is OK. I find Altera's tools are OK as long as you are doing a 'push the button to crank out a design' design. The Altera tools are not very friendly if you want to carefully control implementation and placement. > For silicon I'd say Altera works well for datapath type functions (filters and > other pipelined functions) and Xilinx works well for more random and mixed > logic. If you need to lock down your pins and create a circuit board before > the FPGA design is done, then you don't want to use Altera. I heartily disagree with this statement. In fact, my findings are almost exactly the opposite. Xilinx is a clearly superior choice for data-path and DSP applications. There are several reasons for this: First, the Altera carry chain structure costs inputs. When you invoke the carry chain in an Altera device, the 4LUTs are reduced to a pair of 3LUTs, with one input (and one output) dedicated to the carry chain. That limits you to a 2 input arithmetic function unless you go to multiple levels. This of course means that if you need an adder-subtractor, an accumulator with a synchronous clear, or any of a myriad of othr functions you are stuck with considerably reduced performance, density and routability. The carry chain is set up such that there is no advantage (actually a considerable disadvantage in most cases) to putting that second level in the same LAB as the first level, since the carry chain would have to be connected through that second level LE even though it is not used. The connections between the first and second levels in your arithmetic function are therefore forced onto the global routing.That brings me to the second disadvantage of Altera for data path designs. Data path designs typically require mostly local connections, usually going to only one or two destinations. Those connections are also typically busses, ranging from 8 to 32 bits wide. Altera's 10K architecture forces all connections between LE's to go onto the global routing. The Altera Global routing is a limited resource, in fact there are only 6 channels per lab in a row. This is not enough connection for anywhere near full logic utilization in a data path design. Global routing is also slower than local routing in the same device due to the capacitive effects, so there is a speed handicap incurred as well. Now the one thing the global routing does buy is predictable routing, which is a boon to synthesized design. That is why, for random synthesized logic, I feel the Altera has an edge over Xilinx 4K. When everything is routed on global routing, the ability to have pre-designed macros with known timing is compromised. The third handicap Altera suffers with for DSP designs is the inability to compactly create delay queues and many small memories. Delay queues occur very often in pipelined DSP designs. They are needed to match the pipeline delays on multiple signal paths. The xilinx architecture lets you implement a 16 clock delay in half a CLB (plus 2 clbs of control logic which can be shared among many delay queue bits). Altera, on the otherhand eats up 16 LE's to implement the same delay. This is a substantial handicap, especially in digital filters. The one place Altera does well is for synthesizing statemachines and random logic. This is because the global route takes the place and route out of the synthesis equation. The altera tools have less controls to worry about than the xilinx tools, which for the casual user or newbie may be a good thing. For the expert, it is a frustrating lack of control. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13689
Can anyone give suggestions for books on synthesizable VHDL. I've been working with PLD designs with VHDL for a while so what I'm really looking for is something that _doesn't_ start out with the basics i.e., more advanced topics and techniques but still within the bounds of pratical, synthesizable code. If it's written from a communication systems (or signal processing) perspective I'd probably weep from joy. Thanks, Tim O'ConnellArticle: 13690
Great post, Ray. But why stop here? I'd like to see you do a complete Xilinx vs. Altera comparison, both tools and FPGA silicon. And maybe toss Orca 2 & 3 series in there if you've used them. I've hung with Xilinx FPGAs and tools for over eight years now and have had no reason to even look at Altera's FPGAs. As an experiment I tried to build a fast 32-bit barrel shifter in an Altera 8k part about 5 years ago and had a very bad experience. I was appalled by the lack of control in MaxPlusII (not timing driven at all back then) and by the 8k architecture. Switched the design to a Xilinx 4k part with great results and have never looked at Altera again. I know MaxPlusII has gotten better and the Altera 10k family corrected some 8k problems, but it still amazes me that Altera gets any FPGA business at all considering the alternatives available (Xilinx and Lucent). I still love the Altera PLDs, though. Anyway, any more personal experiences along these lines you have time to post would be interesting reading. Bob S. Ray Andraka wrote: > > Ken Coffman wrote: > > > I don't consider Foundation tools to be usable. What is your desired design > > entry method? Foundation might be okay for schematics, I wouldn't know > > because I've never used a schematic to design an FPGA. The combination of > > Synplicity Synplify or Exemplar Leonardo for Verilog or VHDL design with the > > Xilinx Design Manager for place and route works very well. Altera has simple > > silicon, so their software is correspondingly simple and easy, and works > > very well. If you're looking for all-in-one vendor software that works well, > > MAXPLUS2 is great. > > While I wouldn't go as far as saying foundation is unusable, there are many > people using it quite successfully. It is not, however, what I would consider a > professional design package compared to the more expensive alternatives. It is > also very awkward for controlling the design to obtain higher performance and/or > density. For the occasional user who has not been 'spoiled' by using better, it > is OK. I find Altera's tools are OK as long as you are doing a 'push the button > to crank out a design' design. The Altera tools are not very friendly if you > want to carefully control implementation and placement. > > > For silicon I'd say Altera works well for datapath type functions (filters and > > other pipelined functions) and Xilinx works well for more random and mixed > > logic. If you need to lock down your pins and create a circuit board before > > the FPGA design is done, then you don't want to use Altera. > > I heartily disagree with this statement. In fact, my findings are almost > exactly the opposite. Xilinx is a clearly superior choice for data-path and DSP > applications. There are several reasons for this: First, the Altera carry > chain structure costs inputs. When you invoke the carry chain in an Altera > device, the 4LUTs are reduced to a pair of 3LUTs, with one input (and one > output) dedicated to the carry chain. That limits you to a 2 input arithmetic > function unless you go to multiple levels. This of course means that if you > need an adder-subtractor, an accumulator with a synchronous clear, or any of a > myriad of othr functions you are stuck with considerably reduced performance, > density and routability. The carry chain is set up such that there is no > advantage (actually a considerable disadvantage in most cases) to putting that > second level in the same LAB as the first level, since the carry chain would > have to be connected through that second level LE even though it is not used. > The connections between the first and second levels in your arithmetic function > are therefore forced onto the global routing.That brings me to the second > disadvantage of Altera for data path designs. Data path designs typically > require mostly local connections, usually going to only one or two > destinations. Those connections are also typically busses, ranging from 8 to 32 > bits wide. Altera's 10K architecture forces all connections between LE's to go > onto the global routing. The Altera Global routing is a limited resource, in > fact there are only 6 channels per lab in a row. This is not enough connection > for anywhere near full logic utilization in a data path design. Global routing > is also slower than local routing in the same device due to the capacitive > effects, so there is a speed handicap incurred as well. Now the one thing the > global routing does buy is predictable routing, which is a boon to synthesized > design. That is why, for random synthesized logic, I feel the Altera has an > edge over Xilinx 4K. When everything is routed on global routing, the ability > to have pre-designed macros with known timing is compromised. > The third handicap Altera suffers with for DSP designs is the inability to > compactly create delay queues and many small memories. Delay queues occur very > often in pipelined DSP designs. They are needed to match the pipeline delays on > multiple signal paths. The xilinx architecture lets you implement a 16 clock > delay in half a CLB (plus 2 clbs of control logic which can be shared among many > delay queue bits). Altera, on the otherhand eats up 16 LE's to implement the > same delay. This is a substantial handicap, especially in digital filters. > The one place Altera does well is for synthesizing statemachines and random > logic. This is because the global route takes the place and route out of the > synthesis equation. The altera tools have less controls to worry about than the > xilinx tools, which for the casual user or newbie may be a good thing. For the > expert, it is a frustrating lack of control. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 13691
Tim Forcer wrote: > Broadening the issue a bit, most of my design work is on relatively > small-scale designs. In these applications I find it extremely > frustrating that, except for Phillips XPLA, there's been nothing really > new in not-many-pins devices for a very long time. What I'd love to see > is a 16 pin IC, with at least two pins carrying clocking signals, and > ALL pins having versatile I/O macrocells. Sort of 14V14. Or maybe > 28V14 if every macrocell included a buried register. A 20-pin version > would be 18V18/36V18. But all developments these days are in Mega this > that and the other. Certainly useful in a very wide range of > applications, but is the small-footprint IC really a dead market for new > programmable logic devices? > > -- > Tim Forcer tmf@ecs.soton.ac.uk Tim, I remembered using a 22V10 type device with buried registers. I found it at http://www.atmel.com The ATV750B has a 22V10 structure along with an additional 10 buried registers. Comes in a 7.5 nS comm, 10 nS indust speed grade and 24 pin SOIC packages. I haven't used it in years (like maybe 10?) but they still seem to make it. It is not ISP, but rather UV eraseable. I remember that they made a 24V12 as well, in fact I still have a sample around here somewhere. But I guess that one hasn't survived the test of time. :( But your point is valid. Other than the zero power stuff, I haven't seen much improvement in the state of PLD in the last 5 or more years as well. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13692
We maintain links to various VHDL books on The Programmable Logic Jump Station at http://www.optimagic.com/books.html#VHDL. However, I don't know of one written from a communication perspective (so please, no weeping :) ). ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Tim O wrote in message <367a71d1.6056222@news.oar.net>... >Can anyone give suggestions for books on synthesizable VHDL. I've >been working with PLD designs with VHDL for a while so what I'm really >looking for is something that _doesn't_ start out with the basics >i.e., more advanced topics and techniques but still within the bounds >of pratical, synthesizable code. If it's written from a communication >systems (or signal processing) perspective I'd probably weep from joy. > > > Thanks, > > Tim O'ConnellArticle: 13693
Tim Forcer wrote in message <367A2F1B.1669@ecs.soton.ac.uk.nojunk>... >Broadening the issue a bit, most of my design work is on relatively >small-scale designs. In these applications I find it extremely >frustrating that, except for Phillips XPLA, there's been nothing really >new in not-many-pins devices for a very long time. Probably so in not many pin devices, but if you're worried about board space, several vendors (Lattice, Xilinx, and Vantis come to mind) offer 32 and 64 macrocell CPLDs in PQFP 44 packages. These take up a little less board space than a 22V10. I know Vantis, and probably the others, offers these same chips in TQFP 48 packages, which are even smaller than the PQFP 44's. All of them offer ISP, which other than the Lattice offerings, isn't found in 22V10's. They're really nice chips. Pretty cheap, too. The 32 macro Vantis CPLDs (Mach111SP or M4-32/32) goes down to 5ns in commercial versions as well. ---Joel KolstadArticle: 13694
FPGA'99 Advance Program
1999 ACM/SIGDA Seventh International Symposium on
Field Programmable Gate Arrays
Sponsored by ACM/SIGDA
with support from Xilinx, Altera, Actel, Vantis and Lucent Technologies
Doubletree Hotel, Monterey, California
February 21-23, 1999
http://www.ece.nwu.edu/~hauck/fpga99/index.html
Join us for the seventh ACM/SIGDA International Symposium on Field
Programmable Gate Arrays (FPGA'99), the premier forum for novel work in all
areas related to FPGA technology. This year's FPGA Symposium features
twenty-four papers describing cutting-edge FPGA work. Authors present novel
work on FPGA architecture from commercial vendors, research labs and
universities. Innovative software research highlights high-speed and
high-quality FPGA design. Papers also describe novel devices and software
for reconfigurable computing. Finally, FPGA'99 showcases some very impressive
applications of FPGAs.
This year's panel session deals with a timely issue: what will FPGAs look like
in the era of systems-on-a-chip? More and more of the same? Integrated
microprocessors? Reconfigurable computing? FPGAs as cores in cell-based
devices? How will they be designed? FPGA vendors disagree on the future and
they are staking the lives of their companies on their vision. The evening
panel session is certain to be both enlightening and entertaining.
FPGA'99 provides a relaxed environment for informal information exchange,
networking and stimulating discussions with the leaders in FPGA research and
development from academia and industry. Paper sessions are separated by ample
time to peruse the poster presentations and discuss the latest-breaking
FPGA news.
If you are at all interested in FPGA technology and developments, you won't
want to miss this event.
Organizing Committee:
General Chair: Sinan Kaptanoglu, Actel
Program Chair: Steve Trimberger, Xilinx
Publicity Chair: Scott Hauck, Northwestern University
Finance Chair: Jason Cong, UCLA
Program Committee:
Om Agrawal, Vantis Wayne Luk, Imperial College
Ray Andraka, Andraka Consulting Margaret Marek-Sadowska, UCSB
Michael Butts, Synopsys Peter Moceyunas, Synopsys
Jason Cong, UCLA Jonathan Rose, U. of Toronto
Eugene Ding, Lucent Gabriele Saucier, INPG
Carl Ebeling, U. of Washington Martine Schlag, UCSC
Scott Hauck, Northwestern U. Herman Schmit, CMU
Brad Hutchings, BYU Tim Southgate, Altera
Sinan Kaptanoglu, Actel Steve Trimberger, Xilinx
David Lewis, U. of Toronto John Wawrzynek, UCB
Fabrizio Lombardi, Northeastern U. Martin Wong, UT at Austin
PROGRAM
Sunday, February 21, 1999
6:00PM Registration
7:00PM Welcoming Reception
Monday, February 22, 1999
7:30AM Continental Breakfast and Registration
8:20AM Opening remarks, Sinan Kaptanoglu, Steve Trimberger
Session 1. Commercial FPGA Architectures
Chair: Jonathan Rose, University of Toronto
8:30AM A new high density and very low cost reprogrammable FPGA
architecture, Sinan Kaptanoglu, Greg Bakker, Arun Kundu,
Ivan Corneillet, Actel Corporation; Ben Ting, BTR Inc.
8:50AM Hybrid Product Term and LUT Based Architectures Using Embedded
Memory Blocks, Frank Heile, Andrew Leaver, Altera Corporation
9:10AM An Innovative, Segmented High Performance FPGA Family with
Variable-Grain-Architecture and Wide-gating Functions, Om Agrawal,
Herman Chang, Brad Sharpe-Geisler, Nick Schmitz, Bai Nguyen,
Jack Wong, Giap Tran, Fabiano Fontana,Bill Harding, Vantis Corporation
9:30AM Coffee Break and Poster Presentations
Session 2. Mapping, Packing and Floorplanning
Chair: Margaret Marek-Sadowska, University of California, Santa Barbara
10:30AM Cut Ranking and Pruning: Enabling a General and Efficient FPGA
Mapping Solution, Jason Cong, Chang Wu, University of California,
Los Angeles, Yuzheng Ding, Lucent Technologies
10:50AM Using Cluster-Based Logic Blocks and Timing-Driven Packing to
Improve FPGA Speed and Density, Alexander Marquardt, Vaughn Betz,
Jonathan Rose, University of Toronto
11:10AM A Methodology for Fast FPGA Floorplanning, John Emmert, Dinesh Bhatia,
University of Cincinatti
11:30AM Poster Presentations
12:00 noon Lunch
Session 3. FPGA Architecture Studies
Chair: Tim Southgate, Altera
1:30PM FPGA Routing Architecture: Segmentation and Buffering to Optimize
Speed and Density, Vaughn Betz, Jonathan Rose, University of Toronto
1:50PM Balancing Interconnect and Computation in a Reconfigurable Computing
Array (or, why you don't really want 100% LUT utilization),
Andre' DeHon, University of California, Berkeley
2:10PM Poster Presentations
Session 4. Rapid Reconfiguration
Chair: Mike Butts, Synopsys
2:40PM Configuration Cloning: Exploiting Regularity in Dynamic DSP
Architectures, S.R. Park, W. Burleson, University of Massachusetts
3:00PM Don't-Care Discovery for FPGA Configuration Compression, Zhiyuan Li,
Scott Hauck, Northwestern University
3:20PM Coffee Break and Poster Presentations
Session 5. Computational Applications
Chair: Brad Hutchings, Brigham Young University
4:20PM A FPGA-Based Hardware Implementation of Generalized Profile Search
Using Online Arithmetic, Emeka Mosanya, Eduardo Sanchez, Swiss Federal
Institute of Technology
4:40PM Procedural Texture Mapping on FPGAs, Andy G. Ye, David M. Lewis,
University of Toronto
6:00PM Dinner
7:30PM Panel: FPGAs in the Era of Systems-on-a-Chip
Moderator: Scott Hauck, Northwestern University
With ever increasing chip densities, more and more logic can be integrated
into a single reconfigurable substrate. At the same time, ASIC designs are
becoming complete Systems-on-a-Chip, integrating together the entire system's
functionality. These new opportunities for system designers raise complex
challenges to the FPGA market. These include:
* Will future FPGA devices contain only reconfigurable logic, or will DSPs,
CPUs, or other complex IP be integrated into these devices?
* How can such hardware resources be integrated with reconfigurable logic
efficiently?
* Should FPGAs be used as IP cores in System-on-a-Chip designs to add
reconfigurability to ASICs?
* How can CAD tools be developed to support these heterogeneous systems,
mixing fixed, programmable, and reconfigurable resources.
* Can we develop custom-generated reconfigurable logic, creating
application-specific reconfigurable arrays?
In this panel we will investigate the challenges of the next decade for FPGA
makers. Who will take advantage of these new technologies, and what will the
FPGAs of 2005 look like? Will FPGA-only houses be able to adapt to these new
constraints, or will they become IP vendors to organizations with expertise
in DSP and CPU design? Is there any role for FPGAs in more complex chips
(ASICs with FPGA IP or Field-Programmable Systems-on-a-Chip)?
Tuesday, February 23, 1999
7:30AM Breakfast
Session 6. FPGAs for Custom Computing
Chair: Carl Ebeling, University of Washington
8:30AM HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array,
William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker,
Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek,
Andre' DeHon, University of California, Berkeley
8:50AM A Reconfigurable Arithmetic Array for Multimedia Applications,
Alan Marshall, Hewlett Packard; Jean Vuillemin, Ecole Normale
Superiere; Tony Stansfield, Igor Kostarnov, Hewlett Packard;
Brad Hutchings, Brigham Young University
9:10AM Memory Interfacing and Instruction Specification for Reconfigurable
Processors, Jeffrey A. Jacob, Paul Chow, University of Toronto
9:30AM Coffee Break and Poster Presentations
Session 7. Placement and Routing
Chair: Martine Schlag, University of California, Santa Cruz
10:30AM Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs,
Yaska Sankar, Jonathan Rose, University of Toronto
10:50AM Satisfiability-Based Layout Revisited: Detailed Routing of Complex
FPGAs Via Search-Based Boolean SAT, Gi-Joon Nam, Karem A. Sakallah,
University of Michigan; Rob A. Rutenbar, Carnegie Mellon University
11:10AM Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA
Systems, Abdel Ejnioui; University of South Florida; N. Ranganathan,
University of Texas
11:30AM Poster Presentations
12:00 noon Lunch
Session 8. DPGAs and Pipeline Configurable FPGAs
Chair: David Lewis, University of Toronto
1:30PM Circuit Partitioning for Dynamically Reconfigurable FPGAs,
Huiqun Liu, D.F. Wong, University of Texas
1:50PM Fast Compilation for Pipelined Reconfigurable Fabrics, Mihai Budiu,
Seth Copen Goldstein, Carnegie Mellon University
2:10PM Configuration Caching Vs Data Caching for Striped FPGAs, Deepali
Deshpande, Arun K. Somani, Akhilesh Tyagi, Iowa State University
2:30PM Coffee Break and Poster Presentations
Session 9. Applications
Chair: Ray Andraka, Andraka Consulting Group
3:30PM String Matching on Multicontext FPGAs using Self-Reconfiguration,
Reetinder P.S. Sidhu, Alessandro Mei, Viktor K. Prasanna,
University of Southern California
3:50PM Reduction of Latency and Resource Usage in Bit-Level Pipelined Data
Paths for FPGAs, P. Kollig, B.M. Al-Hashimi, Staffordshire University
4:10PM Exploiting FPGA-Features during the Emulation of a Fast Reactive
Embedded System, Karlheinz Weiss, Thorsten Stekstor, Gernot Koch,
Wolfgang Rosenstiel, University of Tubingen
4:30PM Closing Remarks, Sinan Kaptanoglu, Steve Trimberger
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Article: 13695Steven Derrien wrote:<..... snip.....> > NET clock1 LOC=p4; > NET clock1 LOC=p162; > > Try: NET "clock1" LOC=P4; I believe the mapper is CaSe SeNsItIvE so try using P4, P162 etc. I also use "" around the net name. Also, check the EDIF or XNF netlist. Make sure that the name of the net AT THE I/O PAD is what you have in the UCF file. Synthesis tools have renaming rules, and it may have renamed the net to something at the I/O pad so that it could call it by regular name after the BUFGS. > In both cases, the mapping process fails with the following error > message : > > ERROR:x4kma:82 - Illegal site name used for clock placement: P4. Please > > consult the "Attributes, Constraints, and Carry Logic" section of the > > Libraries Guide for information on legal clock placement constraints. > > I have seen this error before. In my case Exemplar Leonardo was placing my LOC attrribute on the clock buffer instead of the I/O pad itself. This also goes to my previous comment about renaming. <....snip....> > Steven Derrien > PHD Student > IRISA, France Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 13696
My tool set: FPGA Express 3.0, verilog, Orca Foundry 9.3.1. Target device 3T80. I do the component instantiation GSR gsr0 (.GSR(RESET)); Problem....GSR is not mapped. FPGA Express message indicates it is in the edif netlist and an inspection of the netlist shows the GSR component. When the Orca mapper runs the resource report shows 0 of 1 GSR used. What gives? I run the tutorial (they are always so simple) it uses the GSR just fine. Anybody else have this kind of problem and if so what was the solution? Thanks Jerry EnglishArticle: 13697
Terry Harris wrote: > Peter Alfke <peter@xilinx.com> wrote: > > >Peter wrote: > >As was mentioned before: > >Low temperature is not an issue. > > So why don't you spec 'commercial' parts at -10 or -20? > > Cheers Terry... There is universal agreement that "commercial" means down to the freezing point of water.It might be confusing if every company would create its own definition. Otherwise, this is a good idea. All CMOS vendors could easily do it. Peter Alfke, Xilinx ApplicationsArticle: 13698
Here is a list of several VHDL books (all from Prentice Hall)
VHDL and AHDL Digital System Implementation: by Scarpino, Frank
This exploration of digital system design utilizing the combination of
AHDL and VHDL provides an interesting and informative perspective into modern
digital-system implementation. 1. An Introduction to Combinational Logic and
Hardware Description Language (AHDL).
VHDL Made Easy!: by Pellerin, David and Taylor, Douglas
Using a casual, examples-based style, this book and companion CD-ROM
introduces mainstream design engineers to VHDL and Hardware Description
Languages (HDLs) in general. The CD-ROM includes example VHDL source files and a
wide variety of valuable VHDL-related data.
VHDL for Designers: by Sjoholm, Stefan Lindh, Lennart
This practical guide will help electronics designers and students make
the most of VHDL with the latest, most widely-used design tools available. It
presents both the professional and academic side of designing with VHDL, and
shows how to take full advantage of VHDL with today's design tools.
Guide to VHDL Syntax, A: by Bhasker, Jayaram
Designed to alleviate such problems and frustrations, this guide
describes the complete syntax of the IEEE Std 1076-1993 version of VHDL --
showing the complete syntax of major VHDL constructs and sub-constructs in an
easy-to-read manner, with clear examples of each. Lists all major constructs in
the Table of Contents and cross-references all major and minor constructs in the
Index for quick reference.
VHDL Primer, A: by Bhasker, Jayaram
The aim of this book continues to be the introduction of the VHDL
language to the reader at the beginner's level. Introduces a set of simple and
commonly used features of the language so that readers can start writing models
in VHDL.
VHDL: Starter's Guide: From Simulation to Synthesis: by Yalamanchili, Sudhakar
Basic language concepts are motivated by familiarity with digital logic
circuits with simulation and synthesis presented as complementary design
processes. Coverage of basic synthesis concepts with tutorials, examples and
laboratory exercises.
Structured Logic Design with VHDL: by Armstrong, James R. and Gray, F. Gail
Previous books on this subject have concentrated just on the VHDL
hardware description language without really teaching the design process. This
new reference really shows how to design with VHDL in a synthesis context.
VHDL Primer, A: Revised Edition: by Bhasker, Jayaram
VHDL is an IEEE standard as well as an ANSI standard language for
describing digital designs--but it is a large and verbose language with many
complex constructs that have complex semantic meaning, and is difficult to
understand initially. Covers topics such as basic language elements, behavioral
modeling, dataflow modeling, structural modeling, generics and configurations,
subprograms and overloading, packages and libraries, advanced features, model
simulation, and hardware modeling examples.
VHDL Starter's Guide: by Yalamanchili, Sudhakar
Designed as an inexpensive companion text in courses that use VHDL, this
book provides students with a thorough grounding in the basic concepts and
language of VHDL, and allows them to apply what they've learned using realistic
examples. For schools wanting to introduce VHDL into their undergraduate
computer engineering sequence courses, this inexpensive supplement provides the
basics.
Specification and Design of Embedded Systems: by Gajski, Daniel D. Vahid, Frank
Narayan, Sanjiv and Gong, Jie
KEY TOPICS: Addresses two of the most significant topics in the design
of digital systems -- executable system specification and a methodology for
system partitioning and refinement into system-level components. Covers models
and architectures; specification languages; a specification example; translation
to VHDL; system partitioning; design quality estimation; specification
refinement into synthesizable models; and system-design methodology and
environment.
Computer Architecture: Single and Parallel Systems: by Zargham, Mehdi
This text takes a two-fold approach--(1) to provide a foundation for
understanding and evaluating the design principles incorporated in modern
computers, and to present basic techniques for designing parallel systems and
parallel algorithms. 9. Future Horizons for Architecture.
Modern VLSI Design: Systems on Silicon: by Wolf, Wayne
Designed for advanced courses in Computer Engineering, Computer Systems,
and Electrical Engineering. Displays pertinent devices and layouts including
transistor structures and characteristics, wires, vias, parasitics, design
rules, layout design, and tools.
Steven K. Knapp wrote:
> We maintain links to various VHDL books on The Programmable Logic Jump
> Station at http://www.optimagic.com/books.html#VHDL. However, I don't know
> of one written from a communication perspective (so please, no weeping :) ).
>
> -----------------------------------------------------------
> Steven K. Knapp
> OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
> E-mail: sknapp@optimagic.com
> Web: http://www.optimagic.com
> -----------------------------------------------------------
>
> Tim O wrote in message <367a71d1.6056222@news.oar.net>...
> >Can anyone give suggestions for books on synthesizable VHDL. I've
> >been working with PLD designs with VHDL for a while so what I'm really
> >looking for is something that _doesn't_ start out with the basics
> >i.e., more advanced topics and techniques but still within the bounds
> >of pratical, synthesizable code. If it's written from a communication
> >systems (or signal processing) perspective I'd probably weep from joy.
> >
> >
> > Thanks,
> >
> > Tim O'Connell
--
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Anna Acevedo Tel: USA 408-879-5338
Xilinx University Program Fax: USA 408-879-4442
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Article: 13699Is RESET a pad or an internal net? In Xilinx it has to be an internal net that has come in through a normal input buffer. You also have to use RESET to asynchronously clear or set ALL registers in the design or else GSR can't be used and won't be hooked up at all. Again in Xilinx, it's got to be all registers or none. I assume Orca is the same. Bob S. jerry english wrote: > > My tool set: FPGA Express 3.0, verilog, Orca Foundry 9.3.1. Target > device 3T80. > > I do the component instantiation > > GSR gsr0 (.GSR(RESET)); > > Problem....GSR is not mapped. FPGA Express message indicates it is in > > the edif netlist and an inspection of the netlist shows the GSR > component. When > the Orca mapper runs the resource report shows 0 of 1 GSR used. What > gives? I run the tutorial (they are always so simple) it uses the GSR > just fine. > > Anybody else have this kind of problem and if so what was the solution? > > Thanks > Jerry English
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