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I have started with the driver on the host side but the thing is I am still not cear about some things. I have access to the config registers from the host side. I also can initiate a data transfer from the host side and read data from the on-board RAM. I also have an option of configuring from the Processor bus side( interfaced with fpga). but I dont know how to give data to the pci bridge. i.e how to initiate a transfer from inside the fpga without using the on-board RAM or powerpc in the tranfer.The user manual says only how to configure i.e give the start address( source address in the ram ) , size of data and the destination address. It doesnt tell how to go about if i have to send data without using the RAM, the timing diagrams. Thanks, NiteshArticle: 94226
Hello guys, I have a JTAG cable with 1 line female output, but my board has only 2 lines- pins connector for JTAG. So, my question is how to make ( or simpler to buy ) an adapter between them ? Thank you for reading. Greetings FrankArticle: 94227
>I am looking at using a CRC to provide single bit error correction and >multiple bit error detection. I have worked with CRCs before and know >how to implement them. But I am lacking some of the theoretical >background on how to choose the polynomial. My data packets are a >total of 191 bits with a 31 bit header containing the CRC and 160 data >bits. The header will have its own error correction. I am trying to >determine an optimal CRC polynomial for the whole packet. Currently >there is space in the header for a CRC-8. I may be able to find a few >spare bits to make the CRC 10 or 12 bits if I have to. Roughly, it takes log2 N bits to tell you which bit to correct and another bit to tell you if there is an error. You probably want more bits to tell you if it's a correctable vs uncorrectable error. If you have 160 data bits, an 8 bit code isn't going to work very well. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94228
>One feature to look for is if your data is likely to have a lot '0's either >by error or otherwise then to use a algorithm that has a starting preload of >all '1's in the CRC. '0's then have an effect on the CRC generated right >from the start of the data and hence errors can be detected. If you have a >preload of '0's that isn't the case. The glitch that preloading the CRC register to non-0 catches is leading 0s getting added/or dropped from the message. (Clock screwups, not data screwus.) I'm not a math wiz, but I think it goes roughly like this: The final CRC is the remainder after dividing the message by the polynomial. Leading 0s don't change the answer. I think that preloading the CRC register is roughly adding that as high bits to the front of the message. So adding/dropping a leading 0 on the message shifts the preload and thus changes the remainder from the divide. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94229
I have an EDK project with a bunch of Xilinx cores and a bunch of custom cores. All the custom cores are attached to the OPB. I am using Synplify for the synthesis of all cores, save for the microblaze. The results of synthesis are output as an edn EDIF file. For some of the cores I am getting an EDIF file that has the USER_LOGIC_I (instantiated in the top-level vhdl wrapper) referenced as.... (instance USER_LOGIC_I (viewRef netlist (cellRef user_logic_32s_4s (libraryRef dependency_lib))) So for this one, the USER_LOGIC_I is a netlist. Some give this: (instance USER_LOGIC_I (viewRef syn_black_box (cellRef user_logic_work_tx_data_control_wrapper_structure_0)) So for this one, the USER_LOGIC_I is a black_box Why does synplify give two different synthesis results for essentially the same thing? These are both USER_LOGIC_I cores. They both do very different things, but why would one be a netlist and the other a black box? The black box cores cause errors when run through NGDBuild at a top-level (intantiated from system.edn). Hope this makes sense. It is more of a Synplify question.Article: 94230
So does the USB provide some signal that asserts once it is done tranferring data? Is it a pulse or true handshaking? Meaning, does the USB process assert a "done" signal until it sees a "ack done" signal from the serial out process? Does this happen in 32-bit increments ONLY? Are you assured that the USB does not try to send more data while you are shifting out the data serially? Or are there measures to take care of that? I am just reading in to what you wrote. I may not understand it correctly. I am not that familiar with CPLD's and what you can do with them (their limitations)...sorry. I am more of the FPGA camp. But if you provide more details, I think it can be hashed out.Article: 94231
Hi all, I am designing a memory controller and I want to use concurrent auto precharge. I am using a micron SDR-SDRAM ( http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAMx32.pdf ). The datasheet doesnot specify how to activate a row in bank m when the current state is bank n. Is there a way I can specify the row that should be activated? and which row will be activated (figure 24 in pg:23) when current state of bank m is page active at T0 (same figure) ? Please tell me where I can learn more about this. Thanks for any help. SubhasriArticle: 94232
Jerzy, You may wish to check out Xilinx answer record 18277 if HSWAP_EN = '1'. The title of the Answer Record is : Virtex/Spartan I/O - IO outputs might transition during configuration. Hope this helps, it was news to me when I heard it. - NewmanArticle: 94233
Hi, Does anyone know of a good Verilog to VHDL translation tool? Thanks in advance SudhirArticle: 94234
Hal Murray wrote: > If you have 160 data bits, an 8 bit code isn't going to work > very well. Single-error detection requires only a parity bit. For error correction you need more redundanvy. Hamming codes are the classical way to correct single-errors. Below is the table of redundant (Hamming) bits required. It shows that 8 additional bits can detect and correct a single error in 255 data bits, including the Hamming bits, so they can protect up to 247 original data bits, providing enough information to perform single-error correction.. Peter Alfke, from home. Hamming Single-Bit Error Correction Max data bits + parity bits = total bits 4 +3 = 7 11 +4 = 15 26 +5 = 31 57 +6 = 63 120 +7 = 127 247 +8 = 255 502 +9 = 511 1013 +10 = 1023 2036 +11 = 2047 4083 +12 = 4095 8179 +13 = 8192 etc.Article: 94235
I've been plagues lately with my machine seeming to have a limit on the number of documents or programs that can be opened. If I exceed that quota, I either get the MFC "failed to create an empty document" (in Aldec when I try to open another source file), or the application just plain not opening with no warnings (Xilinx, for example). The limit seems to decrease as I work, to the point where I can only have one application open, then I have to reboot the machine. I checked my disk array for space...there is about 160 GB of 490 GB total occupied, so disk space shouldn't be the issue. I looked at the temp folder, and that doesn't seem to be full either. This is windoze XP pro. Anybody seen this and have a cure?Article: 94236
Antti Lukats wrote: > >Avnet is not selling Linear ! Tthey sell power supply solutions >from TI, so I am not surprised. Maybe they did also take out the >Linear Tech's ad booklet from the DVD box !? > Yes, and replaced it with a TI booklet, see pictures at: http://members.aol.com/fpgastuff/s3e_sample_pack.zip Digilent now has a accessory page offering a power supply and parallel JTAG cable for the starter board: http://www.digilentinc.com/s3eaccessory I ordered one of those low cost ($37.50 USD) Digilent USB JTAG cables to try out, along with a couple of the 6 pin I/O cards. Oddly, there doesn't seem to be any documentation about the sample pack board at Xilinx, only on the Digilent pages as you pointed out earlier, which now also has the user's guide: http://www.digilentinc.com/Products/Documentation.cfm > >would you be interested to beta-test a standalone utility >to configure the sample Pack? > I could try it out briefly, as long as there are no exploding voltage regulators involved :) Also, the S3E sample packs are shipping with ES parts, which have a slightly different pinout and errata than the first production stepping. Have you seen any evidence of the JTAG startup problems discussed in the -ES errata ? > >6pin headers, actually there are 5 of them, the JP1 has same >pinout but only 1 I/O and 3 Input only > On mine, JP1 is the JTAG, and JP2 brings out the serial boot mode SPI pins, something I want to test with an external serial config prom before doing my own S3E board. > >I can send you discount reigstration code for the s3e >Starterkit discount, well I dont know >if that is valid either (but I am not going to use it anyway) > Thanks for the offer, but I'm sure Xilinx has plenty of time to fix their webpage with the discount offer before the kits start shipping, so I should (eventually) be able to register mine. Maybe they should have printed "Offer valid for 30 days after S3E Starter Kit online ordering commences" on the DVD case. > >the 40 pin header, funny 1 ground, and 5 unconnected pins !! > I think they pinned it out to be compatible with the older Digilent boards; but since they stuffed it with a different connector than the old boards anyway (straight male instead of right angle female), I'd rather have seen something like two twenty pin headers, each with one row grounded. BrianArticle: 94237
Yes, you should be able to click on UUT (unit under test) and get access to internal logic. Look for the Workspace window and click on the 'sim' tab. You should see UUT listed in the directory tree. "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:8cfvr1tslmm23tqn196n631hvfoi96r3d5@4ax.com... > On Fri, 6 Jan 2006 16:37:52 -0800, "Brendan Illingworth" > <billingworth@electrascan.com> wrote: > >>Hi All, >> >>I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and >>routing behavior in a Virtex II part. Ports that are declared in my VHDL >>entity declaration are simulated and shown in the wave window in ModelSim. >>My question is this; how does one specify in Xilinx ISE additional signals >>(that are not routed to IOB's) to be simulated in ModelSim? Using the >>"add >>probe" feature seems to route the signals to IOB pads and then simulates >>the >>result of that, I need to see the signal inside a slice (or at least right >>before or after the slice). > > In Modelsim, once the design has been loaded, using the GUI interface, > you can open windows displaying the design structure (as a directory > type tree), and the named signals. Navigate to the design sub-unit you > need to monitor; its signals are listed in the "signals" window. Select > those you need, right click, and "add selected signals to Wave window". > > Now simulate and they will be displayed. > > If you missed some, add them, restart, and simulate again. > > You can also do the same via TCL script of course; the GUI approach > simply generates the relevant script commands. Or you can save the Wave > window format as a ".do" script to recreate this test later. > > Caveat: above refers to ModelSim SE; I believe it's true of XE but I'm > not 100% certain) > > - BrianArticle: 94238
It takes only 8 Hamming bits to error-correct up to 247 data bits. See table below. Peter Alfke, from home Hamming Single-Bit Error Correction Max data bits + parity bits = total bits 4 +3 = 7 11 +4 = 15 26 +5 = 31 57 +6 = 63 120 +7 = 127 247 +8 = 255 502 +9 = 511 1013 +10 = 1023 2036 +11 = 2047 4083 +12 = 4095 8179 +13 = 8192 etc.Article: 94239
Does it always happen (not dependent on running applications) or only when you have certain applications running, like Aldec or Xilinx ISE? I'll forward your note onto to some XP people that I know and see what I get back. If I get back anything worth while I'll post it. Not that I'm an XP expert, but this kind of smells like a memory (mother board RAM) issue. Open up the Task Manager and take a look at available system memory when you start to experience this problem, just for grins. "Ray Andraka" <ray@andraka.com> wrote in message news:Qhkwf.41617$Mi5.28702@dukeread07... > I've been plagues lately with my machine seeming to have a limit on the > number of documents or programs that can be opened. If I exceed that > quota, I either get the MFC "failed to create an empty document" (in Aldec > when I try to open another source file), or the application just plain not > opening with no warnings (Xilinx, for example). The limit seems to > decrease as I work, to the point where I can only have one application > open, then I have to reboot the machine. > > I checked my disk array for space...there is about 160 GB of 490 GB total > occupied, so disk space shouldn't be the issue. I looked at the temp > folder, and that doesn't seem to be full either. > > This is windoze XP pro. > > Anybody seen this and have a cure?Article: 94240
Rob wrote: > Does it always happen (not dependent on running applications) or only when > you have certain applications running, like Aldec or Xilinx ISE? I'll > forward your note onto to some XP people that I know and see what I get > back. If I get back anything worth while I'll post it. > > Not that I'm an XP expert, but this kind of smells like a memory (mother > board RAM) issue. Open up the Task Manager and take a look at available > system memory when you start to experience this problem, just for grins. > Rob, thanks! Hard to tell, If I am at the computer it is because I am doing design work, which means one or more of those apps is open. It doesn't seem to be tied to any one of those apps though. I've seem MSword do it too with a long document (50 page book chapter with about 50 drawings). It is as though there is a memory leak, but it isn't showing up on the task manager. I haven't seen the RAM usage go over about 1.5GB (2GB RAM in the system), and I have the paging file set to 3072MB min, 8192MB max. I've never seen that file increase above the 3GB minimum.Article: 94241
I am working on drivers n the host side. I wasnt clear about few things. I can configure the bridge from the fpga side over the processor bus. In the manual its not stated as to how to do the data transfer without using the on-board RAM. It only specifies how to configure the bridge for the DMA transfer (with initiation fromthe fpga side ) i.e to specify the start address on the on-board ram , destination address and the size. How do I go about tranferring the data without using the on-board external RAM. Is it possible? Thanks, NiteshArticle: 94242
>My guess is that you haven't defined which pin on the >outside of your CPLD is connected to which signal on >the inside of your CPLD. I almost did that, but not quite. :-) The first time I got a project to go through the synthesize and fit I generated a programming file, and I was about to double click on Configure Device (iMPACT) and I suddenly thought "How does it know what pins I want my signals on?" :-) So I looked at the ISE quick start tutoral I had gone through a few weeks back when I first downloaded and installed ISE and figured out how to create UCF.Article: 94243
On Mon, 09 Jan 2006 04:20:31 GMT, "Rob" <robnstef@frontiernet.net> wrote: >Does it always happen (not dependent on running applications) or only when >you have certain applications running, like Aldec or Xilinx ISE? I'll >forward your note onto to some XP people that I know and see what I get >back. If I get back anything worth while I'll post it. > >Not that I'm an XP expert, but this kind of smells like a memory (mother >board RAM) issue. Open up the Task Manager and take a look at available >system memory when you start to experience this problem, just for grins. > > Actually I don't think this is a hardware issue (especially because a reset cures it). I think some app is leaking system resources (memory/windows/gdi handles etc) which is normally not supposed to happen with XP. One thing which is not clear with Ray's post is whether this continues to happen even if he closes all open apps. One thing to try is to open task manager (ctrl-alt-del) and see if there are any zombie processes which belong to dead applications. These may be keeping windows/other resources in memory. Close all apps which are not used, all processes which are not needed anymore and see if you can recover without a reboot. Also going to windowsupdate.microsoft.com to get the latest patches might help.Article: 94244
Hi All, Thanks a lot for your replies. Actually speaking I am trying to implement ethernet multiplexer or switch. the switch will have far more intelligence than mux, so my first step would be to try and implement a mux using the FPGA series which has a rocket IO support as Sean has said in the reply. the decision of using PHY ext. or internal to FPGA (implemented by Xilinx or Altera what ever I target to) will depend on various things. But right now I am in study phase of how to implement a Ethernet switch or Mux in an FPGA. so one more Q for all Superiors 1. Do I need a MAC for every input terminal of a mux or switch. Thank you very much for your replies . please keep posting your valuable helps I will need that a lot. Thanks & Regards, KedarArticle: 94245
Emel schrieb: > Hi, > > I designed a 7th order FIR filter using MATLAB fdatool and obtained > the VHDL code using the HDL Coder. I think that in the following part > of the code there is a problem (Delay pipe line is an 8 element > array, whose elements are 16 bit vectors. filter_in is a 16 bit > vector): > > IF reset = '1' THEN > delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0')); > ELSIF clk'event AND clk = '1' THEN > IF clk_enable = '1' THEN > delay_pipeline(0) <= signed(filter_in); > delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); > END IF; < END IF; > > This part simply shifts previous inputs and should be saving the new > input (filter_in) into delay_pipeline(0) (which it does). However, > after delay_pipeline(0) <= signed(filter_in);, it says > delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);. > As far as I know, the statements in a process are sequential. > So, if you change > delay_pipeline(0) right at the beginning, isn't the old value of > delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0) > (its new value) is assigned to delay_pipeline(1). Hi Emel, for instant relief follow Mikes advice and get yourself a simulator, you may need it anyway sometime. But to help you understand you should learn the difference between variables and signals in VHDL. Signals (assigned with <= ) are updated only at the end of each process. (look for Reader-Driver Model) Variables are instantly updated. What you said about sequential statements is right, but only affects signal assignments if you assign values to the same signal like this: Signal_1 <= '0'; if condition=true then Signal_1 <= '1'; end if; Here the first assignment serves as a default. The if-statement overwrites signal_1 whenever the condition becomes true. have a nice synthesis EilertArticle: 94246
Could you write your CRC+ specs., so.... maybe some of us (me) could send you some code to you..?!Article: 94247
Hi All Verilog users: I am trying to find some study material to cover the basics of logic design. Actually I am preparing for an interview. Can anyone of you point to me some material online or forward me any documents that you have in some of the topics of logic design i.e. - Timing issues with a logic delay block sandwiched between two flip flops etc - Setup and hold time concepts and formulas - Metastability etc - General timing issues and faced in logic design synthesis Your feedback will be greatly appreciated. Regards, Salah salah.kazi @ gmail . com salah.kazi@gmail.com -- Salahuddin (Salah) Kazi (416) 716-5634 (Cell), (905) 472-8890 (Home) Fax: (905) 201-8850, salah.kazi@gmail.com http://salahkazi.tripod.com/resume.htmArticle: 94248
"Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag news:1136777766.184395.129010@g49g2000cwa.googlegroups.com... > Antti Lukats wrote: >> >>Avnet is not selling Linear ! Tthey sell power supply solutions >>from TI, so I am not surprised. Maybe they did also take out the >>Linear Tech's ad booklet from the DVD box !? >> > Yes, and replaced it with a TI booklet, see pictures at: > > http://members.aol.com/fpgastuff/s3e_sample_pack.zip > I would say LT could win in court. I assume LT sponsored the sample pack and the booklet printing, so replacing it with ir-relavant stuff from the competition really isnt nice move from Avnet. > Digilent now has a accessory page offering a power supply > and parallel JTAG cable for the starter board: > > http://www.digilentinc.com/s3eaccessory > > I ordered one of those low cost ($37.50 USD) Digilent > USB JTAG cables to try out, along with a couple of the > 6 pin I/O cards. > unfortunatly I am not supporting this cable (as I dont have it) > Oddly, there doesn't seem to be any documentation about the > sample pack board at Xilinx, only on the Digilent pages as > you pointed out earlier, which now also has the user's guide: > > http://www.digilentinc.com/Products/Documentation.cfm > most of the info about Sample Pack at digilient website appeared within 2 hours from my email - their reply to me was: "be careful when throw rock in an glass house" ! I possible wasnt so easy on them in my first email but it really triggered some results, also documentation for other products appeared at digilent website a few hours later. >> >>would you be interested to beta-test a standalone utility >>to configure the sample Pack? >> > I could try it out briefly, as long as there are no > exploding voltage regulators involved :) > I defenetly hope so - my crash happened during some plug in plug out of the power and jtag cables, its defenetly not triggered by software > Also, the S3E sample packs are shipping with ES parts, > which have a slightly different pinout and errata than > the first production stepping. Have you seen any evidence > of the JTAG startup problems discussed in the -ES errata ? > no, I havent seen those startup problems, but there are other undocumented erratic behaviour, namly if you program the flash with the bitstream location at close at the configuration start address then you can not reprogram again using impact in JTAG mode. nice isnt it? The configuration state machine gets confused as it sees the signature from parallel flash during the jtag configuration sequence. my software has a special fix for this to be overcome. (by placing the flash in read status mode and those preventing the FPGA to see the signature from flash) for impact you need to set jumper in the middle position of the mode select and powercycle >> >>6pin headers, actually there are 5 of them, the JP1 has same >>pinout but only 1 I/O and 3 Input only >> > On mine, JP1 is the JTAG, and JP2 brings out the serial boot > mode SPI pins, something I want to test with an external serial > config prom before doing my own S3E board. > No, I dont think your board is different of what I have and you can not use JP2 for serial config, its not wired to proper pins, I also wanted to test out serial config and ended up doing a quick proto: http://xilant.com/content/view/35/2/ >>I can send you discount reigstration code for the s3e >>Starterkit discount, well I dont know >>if that is valid either (but I am not going to use it anyway) >> > Thanks for the offer, but I'm sure Xilinx has plenty of time > to fix their webpage with the discount offer before the kits > start shipping, so I should (eventually) be able to register mine. > > Maybe they should have printed "Offer valid for 30 days after > S3E Starter Kit online ordering commences" on the DVD case. > >> >>the 40 pin header, funny 1 ground, and 5 unconnected pins !! >> > I think they pinned it out to be compatible with the older > Digilent boards; but since they stuffed it with a different > connector than the old boards anyway (straight male instead > of right angle female), I'd rather have seen something like > two twenty pin headers, each with one row grounded. > > Brian -- Antti Lukats http://www.xilant.comArticle: 94249
>> If you have 160 data bits, an 8 bit code isn't going to work >> very well. >Single-error detection requires only a parity bit. >For error correction you need more redundanvy. Thanks. I was off by (most of) 1 bit. You don't need a separate bit to tell you that there is/isn't an error if you can reserve one of the 2^N positions for the no-error case. Thus 8 bits of Hamming only covers a 255 bit message rather than 256. There is still the question of how well a Hamming code matches the error pattern. Serial links often make multi-bit errors and things get even more interesting when you run an error on the serial link through 8b/10b decoders. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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