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Jim Granville wrote: > Ray Andraka wrote: > >> Mike, >> >> It is like there is a limit on the number of files that can be open. >> I jsut ran into it trying to open Xilinx ISE7. Memory usage was only >> at around 790M out of 2GB. It just wouldn't let Xilinx project >> manager open. Closing Synplify let me open Xilinx. > > > Does sound more like a files handles type issue - you could > do a simple recursive script, that opens a couple of hundred files, > and see where that falls over ? > That would confirm #Files ceiling, and you could run it on another > XP box ? > Has it always had the ceiling, from new ? > > -jg > Yes, it was a new box in November, and I did notice it pretty much from the get-go. Anyone know if there is a file handles limit set somewhere in XP?Article: 94326
Thank you so much!!!!!! Joseph Samson wrote: > Subhasri krishnan wrote: > > Thanks for the reply. But consider the following scenario. After the > > power up sequence, I open a row in bank n followed by multiple > > read/writes. The last read/write to the current bank has auto precharge > > enabled. So when I want to activate a row in bank m for the first time, > > should I issue an active command and is that meaningful because there > > is no example showing read/write with auto precharge interrupted by > > active command to another bank (or has this not been shown because > > during row activation we dont care about the DQ's? ). > > When the datasheet talks about interrupting, they mean that a read or > write burst is interrupted by another read or write cycle. Once the > precharge happens, you have to wait Trp time before issuing another command. > > From page 10: > "The bank(s) will be available for a subsequent > row access a specified time (tRP) after the PRECHARGE > command is issued." > > and > > "Once a bank has been > precharged, it is in the idle state and must be activated > prior to any READ or WRITE commands being issued to > that bank." > > > enabled. So when I want to activate a row in bank m for the first time, > > should I issue an active command > Yes, you have to issue an active command after a bank has been > precharged, but each bank can have a row open simultaneously - you don't > have to precharge Bank n in order to activate a row in Bank m. > > > --- > Joe Samson > Pixel VelocityArticle: 94327
On Mon, 09 Jan 2006 19:34:03 -0500, Ray Andraka <ray@andraka.com> wrote: >Jim Granville wrote: > >> Ray Andraka wrote: >> >>> Mike, >>> >>> It is like there is a limit on the number of files that can be open. >>> I jsut ran into it trying to open Xilinx ISE7. Memory usage was only >>> at around 790M out of 2GB. It just wouldn't let Xilinx project >>> manager open. Closing Synplify let me open Xilinx. >> >> >> Does sound more like a files handles type issue - you could >> do a simple recursive script, that opens a couple of hundred files, >> and see where that falls over ? >> That would confirm #Files ceiling, and you could run it on another >> XP box ? >> Has it always had the ceiling, from new ? >> >> -jg >> > >Yes, it was a new box in November, and I did notice it pretty much from >the get-go. Anyone know if there is a file handles limit set somewhere >in XP? I believe it's a limit on the number of "windows" one can open not files which can be opened from a single app. Take a look at this and see if it fixes your problem: http://support.microsoft.com/default.aspx?scid=kb;EN-US;q126962Article: 94328
austin wrote: > > The PCI standard is written to create and protect ASSP and ASIC device > sales, and is specifically worded to prevent alternate solutions. > Does Xilinx marketing pay you a bounty each time you make such an absurd claim on comp.arch.fpga? The PCI specs are written to guarantee interoperability across best/worst case device/backplane loading and topologies. That the required bus loading excludes FPGA vendors who haven't improved their Cin specs since their first family of 20+ years ago is certainly not the fault of the standards. BrianArticle: 94329
In article <1136835912.580889.298420 @f14g2000cwb.googlegroups.com>, news.guardiani@gmail.com says... > I lost about a week's work on this one last year and really tore into > the Xilinx FAEs about not posting the patch directly on the download > page. It is precisely this sort of attitude by Xilinx that has me using > Altera for all new designs (start the Xilinx vs. Altera debate!). Something like 6 months ago, the first time I tried to start up this home project (other events conspired against me and I only recently got back to it) I was going to go with Altera. I downloaded and installed their design software and started working with it a little bit. I switched to Xilinx when I found that the Altera software locked onto your MAC address and wouldn't run if it couldn't find the matching MAC. At the time the system I was using had two ethernet adapters and I was enabling one or the other depending on which of two different networks I wanted to connect to. But when I had the "wrong" adapter enabled the software wouldn't run. I can see the purpose in things like this to protect from piracy of expensive design software, but this was the FREE version. It doesn't need protecting...Article: 94330
Ray, Some things to try: If you think it's the Operating system, try running xp's system file checker via start -> Run -> "sfc /scannow" (without the quotes and the space before the '/') You will have to put the original xp Pro/Home installation disk into the CD drive and let it do its thing. It'll take a few minutes to complete and will probably reboot. corrupt file fix Perform a "Disk Cleanup": Double-click "My Computer" then right-click on your XP drive, select Properties > Disk Cleanup. Next, perform the following: 1) Open the "Command Prompt" and type: SFC /SCANNOW , and hit enter. (Important: Make sure there is a space between the 'C' and the ' / ' otherwise it won't work) [SFC = System File Checker]. (Have your XP CD available since you will be prompted to insert it in the CD drive. The SFC procedure will take approximately 20 - 30 minutes to complete.) 2) Afterward, perform a Checkdisk (file error-checking and repair procedure). Open the "Command Prompt" and type: CHKDSK /R , and hit enter and answer 'yes' to the question and restart your computer. 3) After performing the above procedures, run "Defrag". It may also be that Windows is having problems opening up a Temp file. Check for bad sectors on your hard drive. Or make sure that the TEMP variable is setup correctly. You can check the system variables by opening up the System Properties box and click on the Advanced tab. You will then see the Envrionment Variables button at the bottom of the window. You should make sure that the TEMP variable exists and that the folder/file it points to is valid. Rob "Rob" <robnstef@frontiernet.net> wrote in message news:jwlwf.3171$OU3.858@news01.roc.ny... > Does it always happen (not dependent on running applications) or only when > you have certain applications running, like Aldec or Xilinx ISE? I'll > forward your note onto to some XP people that I know and see what I get > back. If I get back anything worth while I'll post it. > > Not that I'm an XP expert, but this kind of smells like a memory (mother > board RAM) issue. Open up the Task Manager and take a look at available > system memory when you start to experience this problem, just for grins. > > > > "Ray Andraka" <ray@andraka.com> wrote in message > news:Qhkwf.41617$Mi5.28702@dukeread07... >> I've been plagues lately with my machine seeming to have a limit on the >> number of documents or programs that can be opened. If I exceed that >> quota, I either get the MFC "failed to create an empty document" (in >> Aldec when I try to open another source file), or the application just >> plain not opening with no warnings (Xilinx, for example). The limit >> seems to decrease as I work, to the point where I can only have one >> application open, then I have to reboot the machine. >> >> I checked my disk array for space...there is about 160 GB of 490 GB total >> occupied, so disk space shouldn't be the issue. I looked at the temp >> folder, and that doesn't seem to be full either. >> >> This is windoze XP pro. >> >> Anybody seen this and have a cure? > >Article: 94331
On 9 Jan 2006 08:01:22 -0800, "Marco" <marco@marylon.com> wrote: >Antti, thanks, sorry for the -2.5V, my fault! I searched on the >Spartan3 data sheet and on table 10, pag.10 of DS099-3 there seem to be >only 2.5V allowed, no 3.3V. >Marco We run LVDS inputs on S3's with Vccio = 3.3 (actually, 3.6 sometimes!) and it works fine. Common mode range is damn near rail-to-rail. The LVDS inputs are excellent comparators. JohnArticle: 94332
Rob wrote: > Ray, > > Some things to try: > > If you think it's the Operating system, try running xp's system > file checker via start -> Run -> "sfc /scannow" (without the quotes and the > space before the '/') > > You will have to put the original xp Pro/Home installation disk into the CD > drive and let it do its thing. It'll take a few minutes to complete and will > probably reboot. > > corrupt file fix > Perform a "Disk Cleanup": Double-click "My Computer" then right-click on > your XP drive, > select Properties > Disk Cleanup. Next, perform the following: > 1) Open the "Command Prompt" and type: SFC /SCANNOW , and hit enter. > (Important: Make > sure there is a space between the 'C' and the ' / ' otherwise it won't work) > [SFC = System > File Checker]. > > (Have your XP CD available since you will be prompted to insert it in the CD > drive. The > SFC procedure will take approximately 20 - 30 minutes to complete.) > > 2) Afterward, perform a Checkdisk (file error-checking and repair > procedure). > Open the "Command Prompt" and type: CHKDSK /R , and hit enter and answer > 'yes' to the > question and restart your computer. > > 3) After performing the above procedures, run "Defrag". > > > It may also be that Windows is having problems opening up a Temp file. > Check for bad sectors on your hard drive. Or make sure that the TEMP > variable is setup correctly. You can check the system variables by opening > up the System Properties box and click on the Advanced tab. You will then > see the Envrionment Variables button at the bottom of the window. You > should make sure that the TEMP variable exists and that the folder/file it > points to is valid. > > Rob > Rob, Thanks for the detailed help. I ran sfc /scannow (thanks for the instructions), but it didn't report finding anything. I also ran defrag earlier today, with no improvement. I've got chkdsk running now. The drive system is a Raid3 array, which as I understand it monitors the disk condition too. I did have a dead drive within a week of installing the system, but was able to keep going and replaced that drive a few days later. I am wondering if the raid3 isn't somehow messing with the temp file or paging file? The temp file is set up under the documents and settings folder for my login. It appears to be there, and the environment variables are set for both temp and tmp. Is there anything else to look for? What about those registry values someone else mentioned in a link? Mine are set to the 1024 and 3072 defaults mentioned in the link. There is also a 3rd number, 512 after that that is not mentioned in the website, probably a difference between XP pro and NT, which is what was referenced in the website.Article: 94333
hello all,
I am g.venkat ramdas doing my M.S in I2IT, pune.We are in
our final sem and we are looking for project ideas and companies which
work on fpga architectures and also in VHDL/Verilog programming .It
would be very helpful if we know what exactlycomapnies are looking for
in freshers and to know abt project ideas.I request all the experinced
people here to give ure valuable suggestion regarding project interns
anywhere in INDIA.Waiting for ure precious advice.
venkat
Article: 94334bjzhangwn wrote: > Now I want a Tcam ,and the need is below,read must be completed in 1 > cycle,Entry 2048,word length 32bits,If I can implemented it in the > fpga,can someone give me some advice.Thanks! That will be a huge cam on a fpga. I quickly tried with coregen and it would take 32768 SRL16 elements. On a Virtex4 those need SLICEM elements and if I remember correctly half of the slices were M-type. So that cam would fit to a XC4VLX160. I'd guess the timing is also in the range of 25-30ns but could be much worse. The timings on the data sheets are quite optimistic usually if compared to real designs using CAMs. I hope that the vendors would figure out better ways of using the fabric to generate CAMs (or add something to the LUTs). I woudn't mind some latency it's there also in the commercial components. --KimArticle: 94335
thank u for ur tips,the synthesis command "syn_keep" "syn_noprune" and "syn_preserve" can prevent instances or reg or wire from optimizing. Now I hope to keep the net connections and stop optimizing the whole design, fit the design to a FPGA, is there any solution?Article: 94336
Hi Ray, I found this website a while back. http://www.sysinternals.com/Utilities.html It's run by the guy who found the Sony 'rootkit' thingy. There's a whole bunch of freeware utilities that you can use to help diagnose your system. Sorry, it's not a solution per se, and I've not used this resource extensively myself (yet!) but it might help you move forward in your mission to find out what's going on. Good luck & HTH, Syms. "Ray Andraka" <ray@andraka.com> wrote in message news:Qhkwf.41617$Mi5.28702@dukeread07... > I've been plagues lately with my machine seeming to have a limit on the > number of documents or programs that can be opened. If I exceed that > quota, I either get the MFC "failed to create an empty document" (in Aldec > when I try to open another source file), or the application just plain not > opening with no warnings (Xilinx, for example). The limit seems to > decrease as I work, to the point where I can only have one application > open, then I have to reboot the machine. > > I checked my disk array for space...there is about 160 GB of 490 GB total > occupied, so disk space shouldn't be the issue. I looked at the temp > folder, and that doesn't seem to be full either. > > This is windoze XP pro. > > Anybody seen this and have a cure?Article: 94337
I think two cycles are necessary! "bjzhangwn" <bjzhangwn@126.com> ??????:1136820555.537510.298830@g43g2000cwa.googlegroups.com... > Now I want a Tcam ,and the need is below,read must be completed in 1 > cycle,Entry 2048,word length 32bits,If I can implemented it in the > fpga,can someone give me some advice.Thanks! >Article: 94338
Hi All, I am very new to the Ethernet area. I am trying to design and Implement an Ethernet switch or Multiplexer. so say if I am bridging between two 1-gbps channels with one 2-gbps channel. when I think of designing a TDM switch between the 2 channels of 1 gbps my basic design will contain a MAC and a FIFO right...? I was thinking that if the incoming data frame is long so that it will cross the TDM slot for that channel of 1 gbps. then I will have to break that frame store the remaining data in fifo and send it in the next slot. Here I am not getting is that how it will get reconstructed at the receiving end . So firstly is it allowed to break like this if yes then how to insert a packet number etc in the frame. Please Help... Thanks & Regards. KedarArticle: 94339
Xilinx ISE 8.1i WebPack has just become available. LeonArticle: 94340
Yes! almost all the altera's softwares but I think there must be more hidden directoris in the website. Do anyone know some? "Guido" <gvaglia@gmail.com> ??????:1136827900.145200.122030@f14g2000cwb.googlegroups.com... > ftp://ftp.altera.com/outgoing/release/ > > Here is the one where you can find the software. > > Guido >Article: 94341
On Mon, 09 Jan 2006 15:48:41 +0100, Eli Hughes <emh203@psu.edu> wrote: > Please just buy the EDK. For the $500 its costs, the printf problem > will be solved in about 30 minutes. The EDK its so much simple to do > what you want. Ok, could you point me to some documentation/tutorial for the EDK? I got an eval version with a Spartan 3 dev kit some time ago, but it was so confusing I never understood how to use it, and I couldn't find any useful beginners-guide back then. //michael -- Instead of email, use this: http://mtech.dk/thomsen/contact.phpArticle: 94342
Hi,Kim Enkovaara,You are right,The LUTs I need if the entrys is 2048 are huge,so I think if I delay the data read out(for example 4 or 5 cycles),and can the LUTs I need reduce?Thanks!And the frequency I need not too high,about 40Mhz!Article: 94343
bjzhangwn wrote: > Hi,Kim Enkovaara,You are right,The LUTs I need if the entrys is 2048 > are huge,so I think if I delay the data read out(for example 4 or 5 > cycles),and can the LUTs I need reduce?Thanks!And the frequency I need > not too high,about 40Mhz! The "efficient" CAM method I'm familiar with for the Xilinx silicon: SRLs can be used as CAMs if loaded in 16 cycles to accommodate 4 bits at a time for one entry; the 4 bits of the CAM word can be 1, 0, or X giving you the Ternary CAM capability. The output from 8 of these SRLs will indicate a single 32-bit word match requiring a minimum of 16536 SRLs for the comparison itself. The 2048 "hit" signals need to be combined depending on whether you need can guarantee only one hit, need "first hit" or "longest hit" where the latter two can be ugly. So in addition to the SRLs used for comparison, you need a mechanism that will load the SRLs in a minimum of 16 cycles per value and that will collate your 8 4-bit comparisons for each element into a single hit address. This isn't done well with FPGAs. The alternative is to use search tables rather than rely on a TCAM which means you no longer have anything near 1 cycle performance. Good luck in your design, - John_HArticle: 94344
Ray, the first channelizer/combiner will be GSM at 1X symbol rate, 270.833kHz, 200kHz spacing. So channel spacing and sample rate are not a simple integer relation. One of the things that I have been looking at is mixed-Radix FFT, such as 3-3-5-13, or 585, 117Mhz/585 would give 270.833kHz for a polyphase DFT. I have also been looking at resampling approaches such a Farrow Interpolation, and weighted-sinc interpolation. Still, I don't want to rule out a DDC approach. The decimation is large, 432, so I can definitely take advantage of multiplexing and distributed arith.Article: 94345
Brian, I am paid (in very small part) to watch this newsgroup, and comment. As for 'absurd claim', it seems you have never served on a standards body, as your comment has me laughing. A 'standard' serves the interests of the companies that promoted it (as well as providing a service to the industry). There is active work by any standards committee to exclude/disadvantage/hobble as many competitors as possible (legally). I used to call it "making every participant equally disadvantaged in order to level the playing field as much as possible prior to approval." A great example of this is when an ASIC is developed, and the company that has it, promotes it as a standard. In the process of getting it approved, it is inevitable that the standard will require a respin of the silicon in order that all vendors have a chance to participate. The original vendor must also respin their chip, as they are not "standard" until they do so. I have seen this multiple times in my 13 years of sitting on multiple ANSI/ATIS/IEEE/IEC standards committees. Since you don't know this, I suggest you go and volunteer to chair a committee, and learn something about the real world. AustinArticle: 94346
Ray Andraka wrote:
> Mike,
>
> It is like there is a limit on the number of files that can be open.
That sound plausible.
I remember in the DOS days, there were settings like:
FILES=50
BUFFERS=20
in a file called c:\config.sys
I expect there is such a setting/limit
somewhere in windows system control panel.
-- Mike Treseler
Article: 94347Hi, Thanks for the reply! But do not have "we" signal or input pin available. Please advice. JohnArticle: 94348
john wrote: > Hi, > > Thanks for the reply! But do not have "we" signal or input pin > available. Please advice. > > John > Surely you have something that indicates the usb data is valid, no? If not, then just clock the whole thing at your local clock.Article: 94349
I like the new Xilinx Webpack 8.1i interface under Linux, it works great. I am running the Webpack under Gentoo Linux with a 2.6.14 kernel. The Impact tool works well with the parallel port under Linux. I updated the Gentoo HOWTO-Xilinx at: http://gentoo-wiki.com/HOWTO_Xilinx with the steps that I took to get everything installed and working properly, including the kernel modules needed to get the parallel port JTAG working. Take care, -Chris -- /> Christopher Cole <\ <\ << Cole Design and Development \\ email: cole@coledd.com \\ \\ Computer Networking & Embedded Electronics \\ web: http://coledd.com >> \> \> </
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Compare FPGA features and resources
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