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Messages from 94275

Article: 94275
Subject: Re: "failed to create empty document"
From: Phil Hays <Spampostmaster@comcast.net>
Date: Mon, 09 Jan 2006 07:13:42 -0800
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

>The task manager isn't showing any unexpected large memory users, and 
>doesn't indicate that I am running out of memory.  The apps are all 
>latest versions.

Defragmented your disks recently?

You might want to use one of your two free support calls:

http://support.microsoft.com/oas/default.aspx?ln=en-us&x=7&y=4&c1=509&gprid=3223&


-- 
Phil Hays

Article: 94276
Subject: Re: how to speed up the program running in ddr sdram
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 9 Jan 2006 16:22:32 +0100
Links: << >>  << T >>  << A >>
"Athena" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag 
news:ee938f6.-1@webx.sUN8CHnE...
> Hi all,
>
> At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 
> to do some projects. As my programme is very large, there is not enough 
> space to put them in the bram, so I have to put them in the ddr sdram. 
> However, I found that when the programme is in the ddr sdram, the speed is 
> 20 times lower than in the bram. I couldn't endure it.
>
> Who knows how to speed up the programming in the ddr sdram?
>
> Please help me. Thank you very much!
>
> Athena

enable microblaze caches and try again, if you are not using EDK then you 
need to implement caches yourself

a poorly designed or badly coupled SDRAM controller can bring very large 
slowdown into the system,

-- 
Antti Lukats
http://www.xilant.com 



Article: 94277
Subject: tcam implemented in fpga
From: "bjzhangwn" <bjzhangwn@126.com>
Date: 9 Jan 2006 07:29:15 -0800
Links: << >>  << T >>  << A >>
Now I want a Tcam ,and the need is below,read must be completed in 1
cycle,Entry 2048,word length 32bits,If I can implemented it in the
fpga,can someone give me some  advice.Thanks!


Article: 94278
Subject: Re: Xilinx DCM
From: austin <austin@xilinx.com>
Date: Mon, 09 Jan 2006 07:32:56 -0800
Links: << >>  << T >>  << A >>
Morten,

CLKFX is only required if the CLK0, 90, 180, 270, CLK2X, or CLKDV output 
is also being used (besides the CLKFX output).

I suspect you are using something more than just CLKFX, which has 
triggered the software to use the DLL which requires CLKFB.

Note that CLKFB min frequency limit is above 24 MHz...

Austin

Morten Leikvoll wrote:

> I discovered that I had to provide feedback from CLK0 to CLKFB to get CLKFX 
> from the DFS.. I dont know if this is a requirement, but at least it gave me 
> the CLKFB I needed.
> 
> <debashish.hota@gmail.com> wrote in message 
> news:1136472616.867657.280820@g47g2000cwa.googlegroups.com...
> 
>>Hi all,
>>
>>i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which
>>you need to provide a feedback clock for phase alignmen). So my DCM is
>>working in without feedback (internal as well as external) mode.
>>
>>I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most
>>of the time it works fine but sometimes after giving a reset to FPGA or
>>reprogramming the FPGA the DCM is not able to multiply the clock to
>>give a 32Mhz clock and gives the same input 16Mhz clock as the output.
>>
>>But according to Xilinx DCM datasheet, in DFS mode we should be able to
>>multiply or divide clocks with frequency > 1 Mhz.
>>
>>So if anyone has faced any such problem or if there is any synthesis
>>attribute which I need to set etc then please guide me.
>>
>>Thanks in advance
>>Debashish
>>
> 
> 
> 

Article: 94279
Subject: about the ftp.altera.com
From: "Sophie Liu" <mailwz@263.net>
Date: Mon, 9 Jan 2006 23:47:46 +0800
Links: << >>  << T >>  << A >>

Hi, dears:
    You know altera put many documents and install files on their ftp =
station, ftp.altera.com

but can some one tell me the hidden directories of the this site? for I =
can not see any files in this station.

Tks



Article: 94280
Subject: Re: CRC error correction
From: Alex Colvin <alexc@TheWorld.com>
Date: Mon, 9 Jan 2006 15:54:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
>It shows that 8 additional bits can detect and correct a single error
>in 255 data bits, including the Hamming bits, so they can protect up to
>247 original data bits, providing enough information to perform
>single-error correction..

True enough. If you can guarantee only single-bit errors.
-- 
	mac the naf

Article: 94281
Subject: Re: Question on Alias in VHDL
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 09 Jan 2006 07:55:33 -0800
Links: << >>  << T >>  << A >>
Mike Harrison wrote:

> I can't figure out how to use alias to create vectors of arbitary signals... 

It can be done, but I don't do it
because alias identifiers are not visible
in simulation. If the expression is
used more than once, declare and
assign a variable or signal.
...
is
  variable lcdbufburst_v : std_logic_vector(2 downto 0);
begin
  lcdbufburst_v := lcdbufadr(1) & lcdbufadr(0) & lcdbufadr(8);
  ...

      -- Mike Treseler

Article: 94282
Subject: Re: spartan3 differential I/O
From: "Marco" <marco@marylon.com>
Date: 9 Jan 2006 08:01:22 -0800
Links: << >>  << T >>  << A >>
Antti, thanks, sorry for the -2.5V, my fault! I searched on the
Spartan3 data sheet and on table 10, pag.10 of DS099-3 there seem to be
only 2.5V allowed, no 3.3V.
Marco


Article: 94283
Subject: Re: CRC error correction
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 9 Jan 2006 08:12:37 -0800
Links: << >>  << T >>  << A >>
Nobody can ever guarantee the number of errors. It's all a question of
probability.
There are many different codes that are more efficient for detecting
and even correcting error bursts. Fire codes have been popular, and
Reed-Solomon codes are used extensively on audio CDs, where errror
bursts are likely.

Peter Alfke, Xilinx Applications


Article: 94284
Subject: Re: DMA with powerspan II -Fpga card
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 9 Jan 2006 16:19:02 -0000
Links: << >>  << T >>  << A >>
Nitesh

As I thing Brian said you need to look at the chip specification. Usually 
you will find a register/s location at a particular offset/s from the BAR 
base address for these kind of DMA transfers but I don't have a lot recent 
PLX experience to expand on that.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Nitesh" <nitesh.guinde@gmail.com> wrote in message 
news:1136781556.613473.256380@o13g2000cwo.googlegroups.com...
>I am working on drivers n the host side. I wasnt clear about few
> things.  I can configure the bridge from the fpga side over the
> processor bus. In the manual its not stated as to how to do the data
> transfer without using the on-board RAM. It only specifies how to
> configure the bridge for the DMA transfer (with initiation fromthe fpga
> side ) i.e to specify the start address on the on-board ram ,
> destination address and the size. How do I go about tranferring the
> data without using the on-board external RAM.
> Is it possible?
> Thanks,
> Nitesh
> 



Article: 94285
Subject: Re: Verilog to VHDL translation tool
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 09 Jan 2006 08:21:48 -0800
Links: << >>  << T >>  << A >>
Sudhir.Singh@email.com wrote:
> Does anyone know of a good verilog to vhdl translation tool.

There are some expensive ones,
but I don't know of any good ones.

Most synthesis tools allow me to
black-box a verilog module
as an unbound component.

The downside is the expense
of a mixed simulation license
if the verilog module doesn't work.

            -- Mike Treseler

Article: 94286
Subject: Re: CRC error correction
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 9 Jan 2006 16:26:56 -0000
Links: << >>  << T >>  << A >>
Some friends and I had a discussion about this a month or two ago. I 
remember being educated about this:-

"Of all practical error correction methods known to date, turbo codes, 
together with Low-density parity-check codes, come closest to approaching 
the Shannon limit, the theoretical limit of maximum information transfer 
rate over a noisy channel."
http://en.wikipedia.org/wiki/Turbo_code
http://en.wikipedia.org/wiki/Low-density_parity-check_code
Cheers, Syms.

"Peter Alfke" <alfke@sbcglobal.net> wrote in message 
news:1136823157.745092.145560@g43g2000cwa.googlegroups.com...
> Nobody can ever guarantee the number of errors. It's all a question of
> probability.
> There are many different codes that are more efficient for detecting
> and even correcting error bursts. Fire codes have been popular, and
> Reed-Solomon codes are used extensively on audio CDs, where errror
> bursts are likely.
>
> Peter Alfke, Xilinx Applications
> 



Article: 94287
Subject: Re: ISE 8.1Evaluation
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 09 Jan 2006 16:27:07 GMT
Links: << >>  << T >>  << A >>
Requires money = Buy

I don't want the webpack version as if I do decide to go for the tools, the 
projects will be for the larger devices not supported by Webpack. I want to 
be able to target the larger devices with my code now and run some 
simulations.

I hope this is precise enough.

Rog.

"Antti Lukats" <antti@openchip.org> wrote in message 
news:dptru4$otp$02$1@news.t-online.com...
> "Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag 
> news:%guwf.64944$Cj5.57950@newsfe6-win.ntli.net...
>> An Evaluation version would cost me approx. USD20 in shipping. I was 
>> wondering when the Evaluation version would be there to obtain.
>>
>> Rog.
>
> well, then be precise with wording
>
> eval version does not have a 'buy' price,
> shipping costs do apply, but it doesnt make the eval as 'purchaseable 
> product'
>
> order webpack 8.1 links are there, and I assume you should be able to
> obtain the webpack from online download very soon, it should actually
> provide evaluation of almost all the featueres of the full ISE so try that
> first in case the 8.1 eval CD order is not available yet
>
> -- 
> Antti Lukats
> http://www.xilant.com
> 



Article: 94288
Subject: Re: Xilinx USB Platform Cable not working anymore
From: Gilles GEORGES <georges@irisa.fr>
Date: Mon, 09 Jan 2006 17:27:57 +0100
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag 
> news:dptig7$jk$01$1@news.t-online.com...
> 
>>"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag 
>>news:dpteh3$9hk$1@amma.irisa.fr...
>>
>>>Dear,
>>>
>>>I received last week a Xilinx USB Platform Cable.
>>>Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel 
>>>2.6.6-1.435.2.3smp, the precompiled driver is not suitable.
> 
> [snip]
> 
>>>Firmware version = 1018.
>>>CPLD file version = 0006h.
>>>CPLD version = 1648h.
>>
>>that is weird on WinXP the file version and CPLD version are the same as 
>>displayed
> 
> sorry I meant displayed should be
> 
> CPLD file version = 0006h.
> CPLD version = 0006h.
> 
> antti
> 
> 
> 
Dear Antti,

I just tried the cable with same board on a Win XP computer and it 
works. I previously downgrade to cpld firmware V4 (taken in a ISE 6.3 
linux install) => not working under linux but working under windows. 
Then i upgrade to version 6 and still working under windows.

Going back to my Linux workstation nothing works.

There is a strange thing with Impact, the "CPLD version" differs with 
the "CPLD file version" while the two match on Windows.

Connecting to cable (Usb Port - USB22).
Checking cable driver.
File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 03FA.
  Max current requested during enumeration is 150 mA.
  Cable Type = 3, Revision = 0.
  Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 0021h.

Any idea.

Gilles

Article: 94289
Subject: Re: "failed to create empty document"
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 09 Jan 2006 08:45:16 -0800
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> Hard to tell, If I am at the computer it is because I am doing design 
> work, which means one or more of those apps is open.  It doesn't seem to 
> be tied to any one of those apps though.  I've seem MSword do it too 
> with a long document (50 page book chapter with about 50 drawings).  It 
> is as though there is a memory leak, but it isn't showing up on the task 
> manager.

I expect than one of the windows system
files has been corrupted. I would try
an online update or a setup/repair from
the windows CD.

At work, I use one machine for sim and docs
and a second machine for synth/p+r, both
using the same file server for sources.

           -- Mike Treseler

Article: 94290
Subject: Re: concurrent auto precharge - memory controller
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 9 Jan 2006 08:45:40 -0800
Links: << >>  << T >>  << A >>
Thanks for the reply. But consider the following scenario. After the
power up sequence, I open a row in bank n followed by multiple
read/writes. The last read/write to the current bank has auto precharge
enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command and is that meaningful because there
is no example showing read/write with auto precharge interrupted by
active command to another bank (or has this not been shown because
during row activation we dont care about the DQ's? ).

Joseph Samson wrote:
> Subhasri krishnan wrote:
> > Hi all,
> > I am designing a memory controller and I want to use concurrent auto
> > precharge. I am using a micron SDR-SDRAM (
> > http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAMx32.pdf ).
> > The datasheet doesnot specify how to activate a row in bank m when the
> > current state is bank n. Is there a way I can specify the row that
> > should be activated? and which row will be activated (figure 24 in
> > pg:23) when current state of bank m is page active at T0 (same figure)
> > ? Please tell me where I can learn more about this.
> > Thanks for any help.
> > Subhasri
> >
> Precharging means 'closing' a row so that a different row in that bank
> can be opened. The auto precharge example in Figure 24 assumes that the
> rows are already activated - remember, there can be several rows active
> at the same time as long as each row is in a different bank. In Figure
> 24, there is a row active in Bank n and a row active in Bank m.
> Figures 3 and 4 on page 12 show how to activate a row.
> 
> ---
> Joe Samson
> Pixel Velocity


Article: 94291
Subject: Re: CRC error correction
From: Duane Clark <dclark@junkmail.com>
Date: Mon, 09 Jan 2006 16:50:24 GMT
Links: << >>  << T >>  << A >>
Symon wrote:
> Some friends and I had a discussion about this a month or two ago. I 
> remember being educated about this:-
> 
> "Of all practical error correction methods known to date, turbo codes, 
> together with Low-density parity-check codes, come closest to approaching 
> the Shannon limit, the theoretical limit of maximum information transfer 
> rate over a noisy channel."
> http://en.wikipedia.org/wiki/Turbo_code
> http://en.wikipedia.org/wiki/Low-density_parity-check_code
> Cheers, Syms.

Although those codes are the best by that standard, that of course does 
not mean they are the best for all situations. Plain CRC codes are very 
simple and very fast. If you are in a situation that is unlikely to 
suffer burst errors, there is probably no reason to use anything else. 
Reed-Solomon codes are not so simple, but still very fast, though with a 
bit of latency. They have strong burst error correction ability and 
achieve a pretty good percentage of the Shannon limit.

Turbo codes and LPDC codes are complicated and (relatively) slow, mainly 
because they use an iterative process to arrive at a solution (I am only 
vaguely familiar with the LPDC codes). Back not so long ago, when 
hardware was expensive, you needed a good reason to use the more 
complicated codes, but that reason is slipping away as hardware gets 
much cheaper and much faster. If you are trying to squeeze every last 
tenth of a db of noise immunity out of a signal (for example, receiving 
signals from a spacecraft), it now might be worth it in many situations.

Article: 94292
Subject: Re: tcam implemented in fpga
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 09 Jan 2006 16:54:46 GMT
Links: << >>  << T >>  << A >>
"bjzhangwn" <bjzhangwn@126.com> wrote in message 
news:1136820555.537510.298830@g43g2000cwa.googlegroups.com...
> Now I want a Tcam ,and the need is below,read must be completed in 1
> cycle,Entry 2048,word length 32bits,If I can implemented it in the
> fpga,can someone give me some  advice.Thanks!

Is your cycle running at 1 MHz? 



Article: 94293
Subject: Re: Easier initializing of blockram (spartan3)
From: Ray Andraka <ray@andraka.com>
Date: Mon, 09 Jan 2006 11:56:27 -0500
Links: << >>  << T >>  << A >>
Morten Leikvoll wrote:
> Instead of using INIT_XX=>"...." I would like to write like "INIT(W,A)=>D" 
> where W is the buswidth and D is the initial value (including parity bus) at 
> the port at adress A. This is a plain mapping function and maybe someone has 
> done this before me so I dont have to rewrite it?
> 
> 
You still need the init_xx= attributes , however you can put the 
primitive inside a wrapper and write a set of functions to deconstruct 
an integer array passed as a generic and generate the proper init_xx 
attributes.  You can even handle data split across multiple BRAMs this way.

Do it with a vhdl function (I am assuming you are using VHDL, this would 
be really ugly with verilog) that accepts the data array (array of 
integers, passed into your wrapper as a generic), an index which 
corresponds to the XX in INIT_XX, and the msb and lsb of the slice the 
function is to generate.  From the widht of the field (msb:lsb) you can 
infer the length of the output bit vector, as well as the address into 
your integer array that holds the data. The output of the function is a 
bit vector to match the generic on the BRAM primitive.  You can write a 
second function to convert the bit vector to the hex string needed for 
the attribute.

Article: 94294
Subject: Re: Xilinx USB Platform Cable not working anymore
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 9 Jan 2006 16:58:41 -0000
Links: << >>  << T >>  << A >>
We have seen some strange things happening from time to time with these 
cables. We have seen them appear to stop working only to recover the next 
day and start working again.


John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"Gilles GEORGES" <georges@irisa.fr> wrote in message 
news:dpteh3$9hk$1@amma.irisa.fr...
> Dear,
>
> I received last week a Xilinx USB Platform Cable.
> Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel 
> 2.6.6-1.435.2.3smp, the precompiled driver is not suitable.
> I successfully made the cable working by using the Jungo windrvr6 driver. 
> I successfully run impact and programmed more than 10 fpga and PROM.
>
> Then i tried to use XMD (we bought the cable for PPC405 debugging purpose) 
> and the application apply a firmware update to the cable.
> Since nothing working, neither impact or XMD. When i try to detect JTAG 
> chain in Impact, it give me a lot of "unknown" devices.
>
> This is my impact log :
>
> ************************************
> CABLE DETECTION
> ************************************
>
> // *** BATCH CMD : setPreference -pref UserLevel:NOVICE
> // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED
> // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE
> // *** BATCH CMD : setPreference -pref UseHighz:FALSE
> // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP
> // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION
> // *** BATCH CMD : setPreference -pref AutoSignature:FALSE
> // *** BATCH CMD : setPreference -pref KeepSVF:FALSE
> // *** BATCH CMD : setPreference -pref svfUseTime:FALSE
> // *** BATCH CMD : setPreference -pref UserLevel:NOVICE
> // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED
> // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE
> // *** BATCH CMD : setPreference -pref UseHighz:FALSE
> // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP
> // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION
> // *** BATCH CMD : setPreference -pref AutoSignature:FALSE
> // *** BATCH CMD : setPreference -pref KeepSVF:FALSE
> // *** BATCH CMD : setPreference -pref svfUseTime:FALSE
> // *** BATCH CMD : setMode -bs
> GUI --- Auto connect to cable...
> // *** BATCH CMD : setCable -port auto
> AutoDetecting cable. Please wait.
> CB_PROGRESS_START - Starting Operation.
> Connecting to cable (Parallel Port - parport0).
> WARNING:iMPACT:2377 -  Module parport_pc is not loaded. Please reinstall 
> the cable drivers. See Answer Record 18612.
> Cable connection failed.
> Connecting to cable (Parallel Port - parport1).
> WARNING:iMPACT:2377 -  Module parport_pc is not loaded. Please reinstall 
> the cable drivers. See Answer Record 18612.
> Cable connection failed.
> Connecting to cable (Parallel Port - parport2).
> WARNING:iMPACT:2377 -  Module parport_pc is not loaded. Please reinstall 
> the cable drivers. See Answer Record 18612.
> Cable connection failed.
> Connecting to cable (Parallel Port - parport3).
> WARNING:iMPACT:2377 -  Module parport_pc is not loaded. Please reinstall 
> the cable drivers. See Answer Record 18612.
> Cable connection failed.
> Connecting to cable (Usb Port - USB21).
> Checking cable driver.
> File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA.
> File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 
> 03FA.
>  Max current requested during enumeration is 150 mA.
>  Cable Type = 3, Revision = 0.
>  Setting cable speed to 6 MHz.
> Cable connection established.
> Firmware version = 1018.
> CPLD file version = 0006h.
> CPLD version = 1648h.
> CB_PROGRESS_END - End Operation.
> Elapsed time =      7 sec.
>
> ***********************************************
> JTAG IDENTIFICATION
> ***********************************************
>
> // *** BATCH CMD : Identify
> PROGRESS_START - Starting Operation.
> Identifying chain contents ....read count != nBytes, rc = 20000015.
> read failed 20000015.
> '1': : Manufacturer's ID =Unknown
> INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> '2': : Manufacturer's ID =Unknown
> INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> '3': : Manufacturer's ID =Unknown
> INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part.
> '4': : Manufacturer's ID =Unknown , Version : 14
> INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> GUI --- ************* Process Interrupted by User *************
> Process Interrupted by 
> User----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> write cmdbuffer failed 20000015.
> Validating chain...
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> Boundary-scan chain validated successfully.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
> write cmdbuffer failed 20000015.
>
> I have tried to force CPLD update several times but i allways get the same 
> working.
>
> Can someone help please.
>
> I there a possibilty to reprogram the CPLD with the default firmware ?
>
> Best regards,
>
> Gilles 



Article: 94295
Subject: Re: dma on fpga pci card
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 09 Jan 2006 17:09:04 GMT
Links: << >>  << T >>  << A >>
"Nitesh" <nitesh.guinde@gmail.com> wrote in message 
news:1136671134.056348.151120@g47g2000cwa.googlegroups.com...
>I had posted earlier my issues with Fpga card.
>
> http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74
>
> The  AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The
> powerpc inside teh fpga has linux running..I have some data in my PLB
> master/slave module which has to be transferred to the host pc. So I
> was suggested to llok into DMA transfer part. I went through the
> powerspan II manual . It doesnt provide the details of data cycle for
> the DMA . i.e it only says to write the DMA configuration registers
> with the source address , destination address... and then raisethe go
> signal. Now my problem is that the source address  needs to be the
> on-board RAM address. I dont want to use the onboard RAM.I dont want to
> use the powerpc either. I wanted to write a module in vhdl to do the
> confguration adn the forward the data to the bridge. I dont know
> whether this is possible. I
>
> I dont have experience in this field. How can I do a transfer of data
> from my master/slave module to the host computer?
> Is there a way ?
> Thanks,
> Nitesh

If you want to write a VHDL module to do the DMA, you need to interface to 
the PCI core in your FPGA.  The manual for the core should have information 
on DMA operation. 



Article: 94296
Subject: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
From: cdsmith69@gmail.com <cdsmith69@gmail.com>
Date: Mon, 09 Jan 2006 17:11:47 GMT
Links: << >>  << T >>  << A >>
In article <1136696831.548553.204390
@z14g2000cwz.googlegroups.com>, cdsmith69@gmail.com says...

...the same thing I said several times before.

It looks like my original posting attempts through google groups 
finally showed up after 3 days.  Sorry about the double or 
triple posts.  It won't happen again now that I have a real 
newsreader setup.

Article: 94297
Subject: Re: How to keep the design from Synplify or XST optimizing
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 09 Jan 2006 17:13:00 GMT
Links: << >>  << T >>  << A >>
"zephyrer" <zephyrer@gmail.com> wrote in message 
news:1136598989.134301.62220@g44g2000cwa.googlegroups.com...
> Hi, I have a problem that after Synplify or XST optimizing, my 16x8 RAM
> is reduced to 1x8. This is not my hope. How to avoid this?

One silly idea:  check your address register to make sure it's defined as a 
4-bit value, not a single bit register.  I sometimes forget my dimensions in 
the definitions. 



Article: 94298
Subject: Re: Easier initializing of blockram (spartan3)
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Mon, 9 Jan 2006 18:21:37 +0100
Links: << >>  << T >>  << A >>

"Ray Andraka" <ray@andraka.com> wrote in message 
news:OBwwf.41652$Mi5.32734@dukeread07...
> Morten Leikvoll wrote:
>> Instead of using INIT_XX=>"...." I would like to write like 
>> "INIT(W,A)=>D" where W is the buswidth and D is the initial value 
>> (including parity bus) at the port at adress A. This is a plain mapping 
>> function and maybe someone has done this before me so I dont have to 
>> rewrite it?
>>
>>
> You still need the init_xx= attributes , however you can put the primitive 
> inside a wrapper and write a set of functions to deconstruct an integer 
> array passed as a generic and generate the proper init_xx attributes.  You 
> can even handle data split across multiple BRAMs this way.
>
> Do it with a vhdl function (I am assuming you are using VHDL, this would 
> be really ugly with verilog) that accepts the data array (array of 
> integers, passed into your wrapper as a generic), an index which 
> corresponds to the XX in INIT_XX, and the msb and lsb of the slice the 
> function is to generate.  From the widht of the field (msb:lsb) you can 
> infer the length of the output bit vector, as well as the address into 
> your integer array that holds the data. The output of the function is a 
> bit vector to match the generic on the BRAM primitive.  You can write a 
> second function to convert the bit vector to the hex string needed for the 
> attribute.

I'm not sure if I can get it to work with arrays as I dont know how to pass 
these parameters several times using the same name... Maybe something will 
pop up in my head.

I just tried this.. It compiles but I have yet to verify if the bit 
shuffling is ok. I use one side as an instruction word of 36bit (32+4 
parity) and want to initialize a program for simulation. This should be in 
the default libraries for all BRAM configurations.
Warning:ugly formatted long-line code follows:

entity RAMB16_S9_S36i is
generic
(
 init_000:bit_vector(35 downto 0):=(others=>'0');
 init_001:bit_vector(35 downto 0):=(others=>'0');
[...... stuff deleted....]
 init_1FF:bit_vector(35 downto 0):=(others=>'0')
);
Port
(
      DOA : out std_logic_vector(7 downto 0);
      DOB : out std_logic_vector(31 downto 0);
      DOPA : out std_logic_vector(0 downto 0);
      DOPB : out std_logic_vector(3 downto 0);
      ADDRA : in std_logic_vector(10 downto 0);
      ADDRB : in std_logic_vector(8 downto 0);
      CLKA : in std_logic;
      CLKB : in std_logic;
      DIA : in std_logic_vector(7 downto 0);
      DIB : in std_logic_vector(31 downto 0);
      DIPA : in std_logic_vector(0 downto 0);
      DIPB : in std_logic_vector(3 downto 0);
      ENA : in std_logic;
      ENB : in std_logic;
      SSRA : in std_logic;
      SSRB : in std_logic;
      WEA : in std_logic;
      WEB : in std_logic
);
end RAMB16_S9_S36i;

architecture Behavioral of RAMB16_S9_S36i is

  constant INIT00 :bit_vector(255 downto 0):= init_007(31 downto 0) & 
init_006(31 downto 0) & init_005(31 downto 0) & init_004(31 downto 0) & 
init_003(31 downto 0) & init_002(31 downto 0) & init_001(31 downto 0) & 
init_000(31 downto 0);
  constant INIT01 :bit_vector(255 downto 0):= init_00F(31 downto 0) & 
init_00E(31 downto 0) & init_00D(31 downto 0) & init_00C(31 downto 0) & 
init_00B(31 downto 0) & init_00A(31 downto 0) & init_009(31 downto 0) & 
init_008(31 downto 0);
[...... stuff deleted....]
  constant INIT3F :bit_vector(255 downto 0):= init_1FF(31 downto 0) & 
init_1FE(31 downto 0) & init_1FD(31 downto 0) & init_1FC(31 downto 0) & 
init_1FB(31 downto 0) & init_1FA(31 downto 0) & init_1F9(31 downto 0) & 
init_1F8(31 downto 0);

  constant INITP00:bit_vector(255 downto 0):=
   init_007(35 downto 32) & init_006(35 downto 32) & init_005(35 downto 32) 
& init_004(35 downto 32) & init_003(35 downto 32) & init_002(35 downto 32) & 
init_001(35 downto 32) & init_000(35 downto 32)&
   init_00F(35 downto 32) & init_00E(35 downto 32) & init_00D(35 downto 32) 
& init_00C(35 downto 32) & init_00B(35 downto 32) & init_00A(35 downto 32) & 
init_009(35 downto 32) & init_008(35 downto 32)&
   init_017(35 downto 32) & init_006(35 downto 32) & init_005(35 downto 32) 
& init_004(35 downto 32) & init_003(35 downto 32) & init_002(35 downto 32) & 
init_001(35 downto 32) & init_000(35 downto 32)&
   init_01F(35 downto 32) & init_00E(35 downto 32) & init_00D(35 downto 32) 
& init_00C(35 downto 32) & init_00B(35 downto 32) & init_00A(35 downto 32) & 
init_009(35 downto 32) & init_008(35 downto 32)&
   init_027(35 downto 32) & init_026(35 downto 32) & init_025(35 downto 32) 
& init_024(35 downto 32) & init_023(35 downto 32) & init_022(35 downto 32) & 
init_021(35 downto 32) & init_020(35 downto 32)&
   init_02F(35 downto 32) & init_02E(35 downto 32) & init_02D(35 downto 32) 
& init_02C(35 downto 32) & init_02B(35 downto 32) & init_02A(35 downto 32) & 
init_029(35 downto 32) & init_028(35 downto 32)&
   init_037(35 downto 32) & init_036(35 downto 32) & init_035(35 downto 32) 
& init_034(35 downto 32) & init_033(35 downto 32) & init_032(35 downto 32) & 
init_031(35 downto 32) & init_030(35 downto 32)&
   init_03F(35 downto 32) & init_03E(35 downto 32) & init_03D(35 downto 32) 
& init_03C(35 downto 32) & init_03B(35 downto 32) & init_03A(35 downto 32) & 
init_039(35 downto 32) & init_038(35 downto 32);

[...... more stuff deleted....]
  constant INITP07:bit_vector(255 downto 0):=
   init_1C7(35 downto 32) & init_1C6(35 downto 32) & init_1C5(35 downto 32) 
& init_1C4(35 downto 32) & init_1C3(35 downto 32) & init_1C2(35 downto 32) & 
init_1C1(35 downto 32) & init_1C0(35 downto 32)&
   init_1CF(35 downto 32) & init_1CE(35 downto 32) & init_1CD(35 downto 32) 
& init_1CC(35 downto 32) & init_1CB(35 downto 32) & init_1CA(35 downto 32) & 
init_1C9(35 downto 32) & init_1C8(35 downto 32)&
   init_1D7(35 downto 32) & init_1D6(35 downto 32) & init_1D5(35 downto 32) 
& init_1D4(35 downto 32) & init_1D3(35 downto 32) & init_1D2(35 downto 32) & 
init_1D1(35 downto 32) & init_1D0(35 downto 32)&
   init_1DF(35 downto 32) & init_1DE(35 downto 32) & init_1DD(35 downto 32) 
& init_1DC(35 downto 32) & init_1DB(35 downto 32) & init_1DA(35 downto 32) & 
init_1D9(35 downto 32) & init_1D8(35 downto 32)&
   init_1E7(35 downto 32) & init_1E6(35 downto 32) & init_1E5(35 downto 32) 
& init_1E4(35 downto 32) & init_1E3(35 downto 32) & init_1E2(35 downto 32) & 
init_1E1(35 downto 32) & init_1E0(35 downto 32)&
   init_1EF(35 downto 32) & init_1EE(35 downto 32) & init_1ED(35 downto 32) 
& init_1EC(35 downto 32) & init_1EB(35 downto 32) & init_1EA(35 downto 32) & 
init_1E9(35 downto 32) & init_1E8(35 downto 32)&
   init_1F7(35 downto 32) & init_1F6(35 downto 32) & init_1F5(35 downto 32) 
& init_1F4(35 downto 32) & init_1F3(35 downto 32) & init_1F2(35 downto 32) & 
init_1F1(35 downto 32) & init_1F0(35 downto 32)&
   init_1FF(35 downto 32) & init_1FE(35 downto 32) & init_1FD(35 downto 32) 
& init_1FC(35 downto 32) & init_1FB(35 downto 32) & init_1FA(35 downto 32) & 
init_1F9(35 downto 32) & init_1F8(35 downto 32);

begin

   RAMB16_S9_S36_inst : RAMB16_S9_S36
   generic map
 (
  INIT_A => X"000", --  Value of output RAM registers on Port A at startup
  INIT_B => X"000000000", --  Value of output RAM registers on Port B at 
startup
  SRVAL_A => X"000", --  Port A ouput value upon SSR assertion
  SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion

  INIT_00 => INIT00,
  INIT_01 => INIT01,
[...... even more stuff deleted....]
  INIT_3F => INIT3F,

  INITP_00 =>INITP00,
  INITP_01 =>INITP01,
  INITP_02 =>INITP02,
  INITP_03 =>INITP03,
  INITP_04 =>INITP04,
  INITP_05 =>INITP05,
  INITP_06 =>INITP06,
  INITP_07 =>INITP07
 )
   port map
 (
  DOA => DOA,      -- Port A 8-bit Data Output
  DOB => DOB,      -- Port B 32-bit Data Output
  DOPA => DOPA,    -- Port A 1-bit Parity Output
  DOPB => DOPB,    -- Port B 4-bit Parity Output
  ADDRA => ADDRA,  -- Port A 11-bit Address Input
  ADDRB => ADDRB,  -- Port B 9-bit Address Input
  CLKA => CLKA,    -- Port A Clock
  CLKB => CLKB,    -- Port B Clock
  DIA => DIA,      -- Port A 8-bit Data Input
  DIB => DIB,      -- Port B 32-bit Data Input
  DIPA => DIPA,    -- Port A 1-bit parity Input
  DIPB => DIPB,    -- Port-B 4-bit parity Input
  ENA => ENA,      -- Port A RAM Enable Input
  ENB => ENB,      -- PortB RAM Enable Input
  SSRA => SSRA,    -- Port A Synchronous Set/Reset Input
  SSRB => SSRB,    -- Port B Synchronous Set/Reset Input
  WEA => WEA,      -- Port A Write Enable Input
  WEB => WEB       -- Port B Write Enable Input
 );
end Behavioral;




Article: 94299
Subject: Re: "failed to create empty document"
From: Ray Andraka <ray@andraka.com>
Date: Mon, 09 Jan 2006 12:26:10 -0500
Links: << >>  << T >>  << A >>
Mike Treseler wrote:

> Ray Andraka wrote:
> 
>> Hard to tell, If I am at the computer it is because I am doing design 
>> work, which means one or more of those apps is open.  It doesn't seem 
>> to be tied to any one of those apps though.  I've seem MSword do it 
>> too with a long document (50 page book chapter with about 50 
>> drawings).  It is as though there is a memory leak, but it isn't 
>> showing up on the task manager.
> 
> 
> I expect than one of the windows system
> files has been corrupted. I would try
> an online update or a setup/repair from
> the windows CD.
> 
> At work, I use one machine for sim and docs
> and a second machine for synth/p+r, both
> using the same file server for sources.
> 
>           -- Mike Treseler

Do the on-line updates repair/replace all of the windows files?  I keep 
the system updated with the windoze updates, and none of the updates 
have fixed it.  I've been reluctant to do the windows repair from the CD 
because my experience in the past with NT meant doing that and then 
going back and redoing all the updates, service packs etc, plus the 
occasional reinstall of applications.  I suppose doing the repair from 
the CD is the next step, I'm jsut dreading it because it probably also 
means a day lost getting things back to where they are now.

My main machine is an Athon 64x2 hypersonic cyclone ocx.  Moving to this 
I more or less abandoned the two machine set up I had previously, 
although I still have the second machine here untouched but not powered 
up unless I need it.  The previous set-up was a dual P3-800 for the 
docuementation, design entry, sim, internet access etc and a dual 
K7-1800 for par and synthesis.  My hearing was getting affected by the 
vacuum cleaner like sound emanating from those two machines, and the 
excess heat in the room was rather impressive.  Part of the reason I 
retired the dual P3-800 was to get back onto a single machine to reduce 
the noise and heat load, as well as to avoid the network bottleneck 
between machines.  Simulation as well as the synth and par do run 
noticibly faster on the cyclone, provided I can open everything I need 
opened.  It is also quite a bit cooler, and with the liquid cooling is 
virtually silent compared with the vacuum cleaner.



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