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On Thu, 12 Aug 2010 03:20:59 -0500, maxascent wrote: > Phil, what board are you using? Cant you just swap the oscillator for a > faster one? An Enterpoint Drigmorn2. The oscillator is a tiny little SMD thing, enclosed on one side by the SDRAM chip and on the other by a large SMD capacitor. Replacing it with something else would involve a fair amount of careful SMD rework... not something I'm keen on doing to a £120 development board. Wiring a tin-can oscillator up to one of the GPIOs wouldn't be hard, though I don't have any 66MHz or 75MHz tin-cans in my spares box :( -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 148651
On Jul 1, 11:03=A0am, Frank van Eijkelenburg <fei.technolut...@gmail.com> wrote: > Hi, > > I have a custom made PCIe board with a Virtex 5 FPGA on which I > implemented a DMA unit which uses the PCIe endpoint block plus v1.14. > I also implemented simple read/write operations from the PC to the > board (the board responds with completion TLPs). The read/write > operations are working, DMA is not working > > The board is inserted in a pc with Windows 7 64 bits platform. An > application allocates virtual memory and passes the memory block to > the driver. The driver locks the memory and converts the virtual > addresses into physical addresses. These physical addresses are > written to the FPGA. > > When I start an DMA operation, I can see in chipscope the correct > physical addresses in the TLP header. However, I do not see the > correct values in the allocated memory. What can I do to check where > it is going wrong? > > Another question is about the memory request TLPs. What should I use, > 32 or 64 bit write requests? Or do I have to check runtime if the > physical memory address is below or above the 4 GB (and use > respectively 32 and 64 bit requests)? > > Thanks in advance, > > Frank Could somebody please help me to identify as to what the "4177" suffix calls out on this specific Xilinx Virtex-5 device and if it is compatible to the same device without this suffix. XC5VTX240T-2FF1759I4177 vs. XC5VTX240T-2FF1759I . Avnet list them both on their website but the with the "4177" suffix the price is roughly $1,000.00 more?. It doesnt seem like it would be a specific customer code as they advertize both to the public? Any help with this is appreciated. Tks, DaveArticle: 148652
Could someone please help me to identify the suffix, "4177", on this Virtex-5 device and what it calls out as well as the meaning? Could I use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 suffix)? Avnet advertizes them both however the one with the "4177" suffix is roughly $1,000.00 more? It seems it wouldnt be a custom device or customer code as they advertize both to the public? Anyones Help on this is appreciated. XC5VTX240T-2FF1759I4177 ? Thank you, DaveArticle: 148653
Their database is a mess. I am pretty sure it is the same device. In any case, just give them a call... /Mikhail "FPGA" <dgregory@sgidirect.com> wrote in message news:34881a42-1124-46aa-86ea-24600e356cb8@l20g2000yqm.googlegroups.com... > Could someone please help me to identify the suffix, "4177", on this > Virtex-5 device and what it calls out as well as the meaning? Could I > use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 > suffix)? Avnet advertizes them both however the one with the "4177" > suffix is roughly $1,000.00 more? It seems it wouldnt be a custom > device or customer code as they advertize both to the public? Anyones > Help on this is appreciated. > > XC5VTX240T-2FF1759I4177 ? > > Thank you, > > DaveArticle: 148654
On Aug 12, 12:16=A0pm, FPGA <dgreg...@sgidirect.com> wrote: > Could someone please help me to identify the suffix, "4177", on this > Virtex-5 device and what it calls out as well as the meaning? Could I > use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 > suffix)? Avnet advertizes them both however the one with the "4177" > suffix is roughly $1,000.00 more? It seems it wouldnt be a custom > device or customer code as they advertize both to the public? Anyones > Help on this is appreciated. > > XC5VTX240T-2FF1759I4177 ? > > Thank you, > > Dave This is not a standard device and it should not be listed on Avnet's website. The extra digits refer to a Specification Control Document, SCD, that indicate how this device deviates from the production datasheet or is tested in a way that a customer has requested that is different from the standard test program. Ed McGettigan -- Xilinx Inc.Article: 148655
Hi,
I'am seeking a way to use VIO and core inserter at the same time. I
found that if I want to use VIO , I must also instantiating ILA. I feel
it's awkward.
Please help me find a better way.Thanks.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148656"rickman" <gnuarm@gmail.com> wrote in message news:c26e6846-bfea-4123-9a2f-9aa2fed77ec3@j8g2000yqd.googlegroups.com... > Why is Google too dense to fix their SPAM problem? There are so many > ways they could address the problem and as far as I can tell, they > treat it as a PR concern and have tried to give us a control that does > nothing! You can flag posts as being spam very easily now. Each post > has a link at the bottom that lets you report spam. There are times > when I flag every post that come into the groups I read. I see > nothing happen with that SPAM. The existing SPAM posts are not > deleted. The same SPAM posts are not prevented. In other words, it > is a control that is not wired into anything. > > Once I switched from a newsreader to Google I decided I liked it and > don't want to return. But I am getting tired of dealing with all the > SPAM. There are some days with some groups that the SPAM outnumbers > the real posts by 10 to 1. It makes the groups nearly useless. I > believe there is a similar page at embeddedrelated.com. Does that > work any better? > > Rick I've found that if you report enough spam with the same return address, a program (probably) at Google Groups will notice this and temporarily disable the Google Groups account it was posted with. This often requires getting the full return address using a newsreader, rather than the partial return address you can see through Google Groups. Spammers find the nickname associated with their accounts easier to change. Disabling an account this way takes reporting about 40 spam messages with the same return address, using at least two return addresses of your own (but can be about half of them reported with each return address, with only those in newsgroups you care about reported with both return addresses. Expect this 40 number to rise gradually. More info at: http://groups.google.com/group/alt.support.diabetes/browse_thread/thread/192a32920e586a78/602f8e19821ca84d?q= Getting attention from their humans (if any) is more difficult, and often takes months. Do not expect them to ever send you any return email. Robert MilesArticle: 148657
"jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message news:eYednd6r2dXWAoPRnZ2dnUVZ_qadnZ2d@giganews.com... > > this site was doing a great job keeping out the spam. How did this slip > through? > > --------------------------------------- > Posted through http://www.FPGARelated.com No obvious sign that it was trying to sell anything, which for some people means that it doesn't qualify as spam. In other words, not everything that is off-topic is spam. Robert MilesArticle: 148658
Hello,
I am trying to measure the execution time of some code using a
CoreTimer block connected to a Cortex-M1 processor design in an Actel
Fusion part.
My problem is that TMR_current_value() always returns 0. I am trying
to run in TMR_ONE_SHOT_MODE but I have also tried continuous mode but
no change. I have also double checked that the CoreTimer block is
attached to the APB bus and that the base address in hardware
corresponds to CORETMR_BASE_ADDR in my C source.
Can anyone suggest a reason that TMR_current_value() always returns
0?
Below I attache my C code.
int main( void )
{
int i;
uint32_t tmr_read_val, tmr_pre_val, tmr_diff;
const uint32_t tmr_load_val = 0x12345678;
uint32_t gpio_out = GPOUT_INIT_STATE;
GPIO_init( &g_gpio, COREGPIO_BASE_ADDR, GPOUT_INIT_STATE );
TMR_init(&g_timer, CORETMR_BASE_ADDR,
TMR_ONE_SHOT_MODE,PRESCALER_DIV_2,tmr_load_val);
TMR_start(&g_timer);
i=0;
while(1){
i++;
if ( (i % 0x1FFF) == 0 ){
tmr_pre_val = tmr_read_val;
tmr_read_val = TMR_current_value(&g_timer);
tmr_diff = tmr_pre_val - tmr_read_val;
GPIO_set_outputs( &g_gpio, gpio_out++ );
TMR_reload(&g_timer,tmr_load_val);
}
}
}
Article: 148659Aaron We recently ran into this ourselves. I think the answer is that you cannot instantiate a VIO or ILA and then use Core Inserter to add another ILA. The problem is the ICON primitive. There is only one per chip and if you insert an ILA it uses the ICON. There is not another you can use with your instantiated VIO or ILA. Please correct me if I am wrong on this. PeteArticle: 148660
On Aug 12, 9:42=A0am, Philip Pemberton <usene...@philpem.me.uk> wrote: > On Thu, 12 Aug 2010 03:20:59 -0500, maxascent wrote: > > Phil, what board are you using? Cant you just swap the oscillator for a > > faster one? > > An Enterpoint Drigmorn2. > > The oscillator is a tiny little SMD thing, enclosed on one side by the > SDRAM chip and on the other by a large SMD capacitor. Replacing it with > something else would involve a fair amount of careful SMD rework... not > something I'm keen on doing to a =A3120 development board. > > Wiring a tin-can oscillator up to one of the GPIOs wouldn't be hard, > though I don't have any 66MHz or 75MHz tin-cans in my spares box :( > > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ > If mail bounces, replace "10" with the last two digits of the current yea= r Then there's the idea of using a 100 MHz clock from the CLKFX output and using clock enables to select the main clock or the 90 degree (at 50MHz) version.Article: 148661
On Aug 13, 2:12=A0pm, self <padu...@gmail.com> wrote: > Aaron > > We recently ran into this ourselves. =A0I think the answer is that you > cannot instantiate a VIO or ILA and then use Core Inserter to add > another ILA. > > The problem is the ICON primitive. There is only one per chip and if > you insert an ILA it uses the ICON. =A0There is not another you can use > with your instantiated VIO or ILA. > > Please correct me if I am wrong on this. > > =A0 Pete In FPGA devices with multiple internal BSCAN ports you can have multiple ICON cores. Ed McGettigan -- XilinxArticle: 148662
On Aug 14, 7:33=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Aug 13, 2:12=A0pm, self <padu...@gmail.com> wrote: > > > Aaron > > > We recently ran into this ourselves. =A0I think the answer is that you > > cannot instantiate a VIO or ILA and then use Core Inserter to add > > another ILA. > > > The problem is the ICON primitive. There is only one per chip and if > > you insert an ILA it uses the ICON. =A0There is not another you can use > > with your instantiated VIO or ILA. > > > Please correct me if I am wrong on this. > > > =A0 Pete > > In FPGA devices with multiple internal BSCAN ports you can have > multiple ICON cores. > > Ed McGettigan > -- > Xilinx Ed, why do you answer if you do not know the answer to what was really asked? multiply BSCAN - YES (but was not asked) multiply ICON pors - YES (but was not asked) manually inserted VIO at the same time with CORE INSERTE - NO (this was the question) AnttiArticle: 148663
On Aug 15, 10:05=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Aug 14, 7:33=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Aug 13, 2:12=A0pm, self <padu...@gmail.com> wrote: > > > > Aaron > > > > We recently ran into this ourselves. =A0I think the answer is that yo= u > > > cannot instantiate a VIO or ILA and then use Core Inserter to add > > > another ILA. > > > > The problem is the ICON primitive. There is only one per chip and if > > > you insert an ILA it uses the ICON. =A0There is not another you can u= se > > > with your instantiated VIO or ILA. > > > > Please correct me if I am wrong on this. > > > > =A0 Pete > > > In FPGA devices with multiple internal BSCAN ports you can have > > multiple ICON cores. > > > Ed McGettigan > > -- > > Xilinx > > Ed, > > why do you answer if you do not know the answer to what was really > asked? > > multiply BSCAN - YES (but was not asked) > multiply ICON pors - YES (but was not asked) > > manually inserted VIO at the same time with CORE INSERTE - NO (this > was the question) > > Antti- Hide quoted text - > > - Show quoted text - I was replying to a post that was not the OP to correct a misunderstanding. I'm not sure why this raised your ire. Ed McGettigan -- Xilinx Inc.Article: 148664
Pete
I agreed with you that the problem come from the ICON primitive. But
when I have instantiated a ICON and some VIO in my source files, if the
ngdbuild can detect the unused CONTROL port of the ICON core and present
them to the user , I think we can use the core inserter. I wonder if I can
do this based on the current version of ISE.
>Aaron
>
>We recently ran into this ourselves. I think the answer is that you
>cannot instantiate a VIO or ILA and then use Core Inserter to add
>another ILA.
>
>The problem is the ICON primitive. There is only one per chip and if
>you insert an ILA it uses the ICON. There is not another you can use
>with your instantiated VIO or ILA.
>
>Please correct me if I am wrong on this.
>
> Pete
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148665On Aug 16, 8:18=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Aug 15, 10:05=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Aug 14, 7:33=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Aug 13, 2:12=A0pm, self <padu...@gmail.com> wrote: > > > > > Aaron > > > > > We recently ran into this ourselves. =A0I think the answer is that = you > > > > cannot instantiate a VIO or ILA and then use Core Inserter to add > > > > another ILA. > > > > > The problem is the ICON primitive. There is only one per chip and i= f > > > > you insert an ILA it uses the ICON. =A0There is not another you can= use > > > > with your instantiated VIO or ILA. > > > > > Please correct me if I am wrong on this. > > > > > =A0 Pete > > > > In FPGA devices with multiple internal BSCAN ports you can have > > > multiple ICON cores. > > > > Ed McGettigan > > > -- > > > Xilinx > > > Ed, > > > why do you answer if you do not know the answer to what was really > > asked? > > > multiply BSCAN - YES (but was not asked) > > multiply ICON pors - YES (but was not asked) > > > manually inserted VIO at the same time with CORE INSERTE - NO (this > > was the question) > > > Antti- Hide quoted text - > > > - Show quoted text - > > I was replying to a post that was not the OP to correct a > misunderstanding. =A0I'm not sure why this raised your ire. > > Ed McGettigan > -- > Xilinx Inc. Hi and sorry, sorry, sorry, humble apologies! It was me not reading previous posts carefully enough well the issue is not with the FPGA device at all, its even irrelevant if it has 1 more BSCAN primitives, one ICON can have up to 15 ports that can be used (16th is the ICON own identify slot) so there is absolutely no technical reasons for not being able VIO and core inserter, except that the Xilinx software doesn't allow it. Antti PS this maybe a very small excuse for my running of Ed this Monday morning, but I am in the painful process of firing an employee. I possible make more headache over it then he does. So repeating, to Ed personally: Sorry, Sorry, Sorry, you are the man who does help when you can. I had no excuse (except my mood) for the comment I made.Article: 148666
On Aug 13, 6:59=A0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com> wrote: > Hi, > =A0 =A0 I'am seeking a way to use VIO and core inserter at the same time.= I > found that if I want to use VIO , I must also instantiating ILA. I feel > it's awkward. > Please help me find a better way.Thanks. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com While not quite what you want to do, a work around is to put the VIO and ILA in using the generator flow. Just hook the ILA up to anything convenient at the top level. Go through place and route, and then open the design in FPGA editor. Under the tools menu is an entry for ILA. Select that, and you will get a pop up window that will allow you to reconnect the ILA to the signals you want. Save the ncd, and take it through PAR again. Regards, John McCaskill www.FasterTechnology.comArticle: 148667
Hello, When initializing input/output signals in a multilevel VHDL design, is it "better" to initiate the values in the component declaration in the toplevel? or the submodule entity declaration? Does it make a difference? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148668
On 8/16/2010 3:24 PM, hvo wrote:
> When initializing input/output signals in a multilevel VHDL design, is it
> "better" to initiate the values in the component declaration in the
> toplevel? or the submodule entity declaration? Does it make a difference?
The module entities should drive their port outputs in response to
an active reset input. I use direct instances which do not
require component declarations. A properly bound component declaration
can override generic values but has no effect on reset values.
-- Mike Treseler
Article: 148669Mike Treseler wrote: > I use direct instances which do not > require component declarations. Agreed. Component declarations are a PITA and a maintenance nightmare. Avoid if you can. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 148670
On Mon, 16 Aug 2010 17:24:00 -0500, "hvo" wrote:
>When initializing input/output signals in a multilevel VHDL design, is it
>"better" to initiate the values in the component declaration in the
>toplevel? or the submodule entity declaration? Does it make a difference?
I guess you're talking about default values of input ports?
entity widget is
port (clk: in std_logic;
mode: in std_logic = '0'; -- like this?
count: out std_logic_vector);
That is not an initialisation in the ordinary sense;
it's a default value. It is used only if the port
is unconnected when you instance the entity, and
in that case the port acts as though it is permanently
driven with the default value. If there's no default,
an unconnected input port takes its "normal" default
value ('U' for std_logic, -huge for integer, etc, etc).
For synthesisable designs I generally agree with Mark
and Mike that components are not worth the trouble,
but if you do use components then you must be
careful about these default input values, because
you can get some slightly surprising results.
If you insist on using components, my standard
advice is to make the defaults the same on both
entity and component. At the end of this post
there's a long tedious ramble explaining why.
In theory there are some interesting creative
uses for defaults that differ between component
and entity. In practice I've never found a
situation where it was any use to me.
Finally, a word of caution. Default input values
are a pretty neat idea, but increasingly I choose
never to use them. There is very little additional
work in writing an explicit tie-off in the instance's
port connection list, and I think that makes my intent
much clearer. It also insulates me from the risk that
some well-meaning goon will change the entity default
in the future, and will fail to notice because all his
own tests use explicit connection to the port.
~~~~~~~~~~~~~~~~ long and boring bit ~~~~~~~~~~~~~~~
A default on an ENTITY's port is somewhat like an
internal pullup inside a chip. If you cut off the
chip's pin, the internal pullup will still work.
A default on a COMPONENT's port is like a pullup
built in to a socket. If you don't solder that
socket connection to the PCB, the pullup will
drive it and therefore will drive anything that
you plug in to the socket.
So, if you're using component instantiation,
it all depends on how you bind the entity to
the component.
- If you use default binding (in other words,
you don't write a configuration) then the
entity's ports exactly match the component's,
and default values on the entity's inputs
have no effect. However, if your component
instance has an unconnected port, that port
will use the default (if any) on the
COMPONENT. The entity's default is ignored.
- If you write a configuration, it is possible
to bind an entity to a component that has
different ports. In this case you may choose
to leave some of the entity's ports not bound
to ports on the component. These floating
entity ports will then take their entity
defaults. When you instance the component,
any floating component ports will take their
component defaults.
If you use direct instantiation, things are
simpler because there is no component to worry
about. Ports on the entity that are not
connected at instantiation will get their
default values.
~~~~~~~~~~~ end of long and boring bit ~~~~~~~
--
Jonathan Bromley
Article: 148671Thanks,John. Your idea make things better , though it still need generate the CDC by hand. >On Aug 13, 6:59=A0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com> >wrote: >> Hi, >> =A0 =A0 I'am seeking a way to use VIO and core inserter at the same time.= > I >> found that if I want to use VIO , I must also instantiating ILA. I feel >> it's awkward. >> Please help me find a better way.Thanks. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >While not quite what you want to do, a work around is to put the VIO >and ILA in using the generator flow. Just hook the ILA up to anything >convenient at the top level. Go through place and route, and then >open the design in FPGA editor. Under the tools menu is an entry for >ILA. Select that, and you will get a pop up window that will allow you >to reconnect the ILA to the signals you want. Save the ncd, and take >it through PAR again. > >Regards, > >John McCaskill >www.FasterTechnology.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148672
On Aug 17, 2:57=A0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Thanks,John. Your idea make things better , though it still need generate > the CDC =A0by hand. > > > > >On Aug 13, 6:59=3DA0am, "aaron123" <Aaronsmagazine@n_o_s_p_a_m.gmail.com= > > >wrote: > >> Hi, > >> =3DA0 =3DA0 I'am seeking a way to use VIO and core inserter at the sam= e > time.=3D > > I > >> found that if I want to use VIO , I must also instantiating ILA. I fee= l > >> it's awkward. > >> Please help me find a better way.Thanks. > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >While not quite what you want to do, a work around is to put the VIO > >and ILA in using the generator flow. Just hook the ILA up to anything > >convenient at the top level. =A0Go through place and route, and then > >open the design in FPGA editor. Under the tools menu is an entry for > >ILA. Select that, and you will get a pop up window that will allow you > >to reconnect the ILA to the signals you want. =A0Save the ncd, and take > >it through PAR again. > > >Regards, > > >John McCaskill > >www.FasterTechnology.com > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com On the FPGA Editor ILA tool pop up window, there is a write CDC button. If after you make your changes, you press that it will write out a new CDC file for that LIA core for you. Regards, John McCaskill www.FasterTechnology.comArticle: 148673
This is my testbench code.
When I load it and want see signals in wave, after I add it, wave is
empty.
I do everything but the problem isn't solve.
Can anyone help me?
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_dff is
end test_dff;
architecture behavioral of test_dff is
component dff
port(din,clk,rst:in std_logic;
dout:out std_logic);
end component;
signal clk1:std_logic:='0';
signal rst1:std_logic:='0';
signal din1:std_logic;
signal dout1:std_logic;
begin
unit0: dff port map(din=>din1,clk=>clk1,rst=>rst1,dout=>dout1);
process
begin
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
din1<='0';
wait for 100 ns;
din1<='1';
wait for 100 ns;
end process;
clock: process
begin
clk1<=not clk1 after 25 ns;
wait for 50 ns;
end process clock;
stimulus: process
begin
wait for 5 ns; rst1<='1';
wait for 4 ns; rst1 <='0';
wait;
end PROCESS stimulus;
end behavioral;
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148674
On Tue, 17 Aug 2010 07:38:39 -0500, "somayeh2010" wrote:
>This is my testbench code.
It never stops. I wonder if that's why you don't see any waves?
Try adding a timeout process:
process begin
wait for 500 ns;
report "Normal end of simulation" severity FAILURE;
wait;
end process;
>When I load it and want see signals in wave, after I add it, wave is
>empty.
Which simulator? Did you remember to run the simulation
after loading it?
Simulators usually log only those signals that are already in the wave
window when you start the run. If you're using ModelSim, for example,
you should...
- start the simulator GUI, but then work in the command console
because the menus are tedious
- load the simulation BUT DO NOT START IT RUNNING:
vsim -novopt test_dff
- set up the waves:
add wave -r /*
- run the simulation:
run -all
Other things that might make a difference (using ModelSim):
- try adding the -novopt option to the load command (vsim)
- just before starting simulation, issue the command
log -r /*
This instructs the simulator to log ALL signals, so that
you can add them to the waves later.
- Having created the waveform display, try issuing this command:
restart -force; run -all
>I do everything but the problem isn't solve.
Ah, if only that were true :-) But it's a charming way
to say "I tried really hard but I'm still stuck".
If you're using ModelSim, try the things I suggested.
If you're using some other simulator, tell us what it is.
--
Jonathan Bromley
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