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Messages from 135100

Article: 135100
Subject: Compiler Options
From: "ALuPin@web.de" <ALuPin@web.de>
Date: Tue, 16 Sep 2008 07:28:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

there is a GUI compiler option "Check for Synthesis" available in
Modelsim. Is there some similar option available for Active-HDL ?

Rgds,
ALuPin


Article: 135101
Subject: Re: Compiler Options
From: Jon Beniston <jon@beniston.com>
Date: Tue, 16 Sep 2008 07:38:02 -0700 (PDT)
Links: << >>  << T >>  << A >>

> there is a GUI compiler option "Check for Synthesis" available in
> Modelsim.

I don't think so. Also, keep in mind that different synthesis tools
can sometimes synthesize some constructs that others can't.

Jon

Article: 135102
Subject: Re: Compiler Options
From: "ALuPin@web.de" <ALuPin@web.de>
Date: Tue, 16 Sep 2008 08:19:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Jon,

the main reason for using that compiler option is to detect missing
signals in sensitivity lists.

ALuPin

Article: 135103
Subject: Two JTAG Parallel IV Cable in a single PC.
From: Pablo <pbantunez@gmail.com>
Date: Tue, 16 Sep 2008 08:29:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everybody,

my question is very simple. Has anyone put two JTAG Parallel IV
(Parallel) Cable on a PC?.

I have connected two FPGA and I want to Debug them (in realtime) with
two JTAG Cables. First of all I tried to put a USB To Parallel
Connector, but Xilinx doesn't accept this Virtual Parallel Port.

My second option was putting a PCI Parallel Connector as LPT2. But it
fails again. I couldn't assign a valid BIOS Address ( for LPT: 0x286,
0x386) and Xilinx Impact didn't find it.

My intention is going on looking for a solution, but your experience
could avoid me quite a lot of time.

best regards.

Article: 135104
Subject: Re: Xilinx build system
From: LittleAlex <alex.louie@email.com>
Date: Tue, 16 Sep 2008 08:31:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 16, 7:05 am, Rob <BertyBoos...@googlemail.com> wrote:
> Hi fellow forumers,
>
> We currently have lots of designs implemented with different versions
> of ISE. Often when a bug needs to be fixed on an old design the
> engineer will check out the code and find that it was last compiled
> with an older version of ISE. The user will therefore usually migrate
> to the latest version they have installed on their computer. In the
> past some designs have simply not built because of things like syntax
> changes with UCF files, but I am also worried about more subtle
> problems that might arise from using the newer ISE version.
> Also, when compiling large designs, a user's computer is utilised
> quite heavily (especially memory) limiting what can be done on that PC
> until the build finishes.
>
> For these reasons I was thinking of having an "ISE build PC" which has
> all of the versions of ISE we use installed on it. Then, using build
> scripts (tcl??), the build process can be automated and the process
> will be 100% repeatable and can be performed on an expensive behemoth
> PC rather than the user's work station.
>
> The thing is, I'm not sure how to implement such a thing, or indeed
> whether it is a sensible plan. I've had a look through the Xilinx Tcl
> stuff and there doesn't seem to be a way of getting a version for the
> tools that are being invoked.
> Has anyone implemented anything like this? Is it sensible??
>
> Cheers
> Rob

I have done something similar.

You will need to install all of the versions in separate directories
(you knew that); I use c:\Xilinx\<ise version>\...  (ie, \xilinx\71i,
\xilinx\82i, etc.)  The entire path has to be free of space
characters, and probably any special characters.  You need to have
matching EDK's for all ISE's, if you use Microblaze.

If you look at the environment after the install, you'll find a bunch
of Xilinx variables:  'XILINX', 'XILINX_EDK', etc, and some stuff in
%PATH%.  Save a copy of your environment before any installs, and
after each install so you can find them.

Then make a '.cmd' file that wraps the xilinx commands, setting all
the environment variables first. For example, my Xilinx_71.cmd:

set XILINX=C:\Xilinx\71i
set XILINX_EDK=C:\Xilinx\71i\EDK
set PATH=%PATH%;C:\Xilinx\71i\EDK\bin\nt;C:\Xilinx\71i\bin\nt;
C:\Xilinx\71i\bin\nt\ise.exe

Hope that helps...

Article: 135105
Subject: Re: Two JTAG Parallel IV Cable in a single PC.
From: LittleAlex <alex.louie@email.com>
Date: Tue, 16 Sep 2008 08:32:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 16, 8:29 am, Pablo <pbantu...@gmail.com> wrote:
> Hi everybody,
>
> my question is very simple. Has anyone put two JTAG Parallel IV
> (Parallel) Cable on a PC?.
>
> I have connected two FPGA and I want to Debug them (in realtime) with
> two JTAG Cables. First of all I tried to put a USB To Parallel
> Connector, but Xilinx doesn't accept this Virtual Parallel Port.
>
> My second option was putting a PCI Parallel Connector as LPT2. But it
> fails again. I couldn't assign a valid BIOS Address ( for LPT: 0x286,
> 0x386) and Xilinx Impact didn't find it.
>
> My intention is going on looking for a solution, but your experience
> could avoid me quite a lot of time.
>
> best regards.

If it were me, I'd use one parallel, and one USB.  Or two USB.  Two
parallel adapters on one PC is asking for trouble...

Article: 135106
Subject: Re: Moving to Altera from Xilinx
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Tue, 16 Sep 2008 09:05:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 15, 1:54=A0pm, cs_post...@hotmail.com wrote:
> I think this might be as simple as Xilinx having more low-cost eval
> boards on the market, so that hobbyist, student, and professional
> development type projects are more likely to end up in their silicon,
> and more likely to end up asking basic questions about it here.
> Wheras in more professional usage problems that can't =A0be solved in
> house might be more likely to end up with the FAE's than on the
> newsgroups.

That's possible, but I suspect also that to a large degree it's a
question of inertia. Comp.arch.fpga has always been X dominated,
whereas I suspect many A users frequent Altera's web Forums (for
better or worse).

Tommy

Article: 135107
Subject: Info request about Synplify and Foundation usage
From: flatiron@libero.it
Date: Tue, 16 Sep 2008 09:12:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear all,
I'm try to use VHDL code with some old XC5202PQ100-6 part that I've
from my old design. Old design was did by using Foundation 2.1i and
Schematic Entry, now I'm searching a way to use the VHDL coding to do
some simple example and learn VHDL. My Foundation tools was only a
base installation then I don't have the Express feature then no VHDL
compiler will available, but I've the Synplify 9.2 tool and I can make
the mapping of VHDL circuit. Now I'm asking if there is a way to
export the mapped file trough the netlist description (xnf, edf) into
the old Foundation and merge this device with other device into the
Schematic Editor. In other word there is a way to import into the
Foundation tool a device, like a black box then into the device
library and then use it for the design flow implement stage?

Thanks for reply.

Regards
Grinch

Article: 135108
Subject: Re: need fast FPGA suggestions [ AFPGA ? ]
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Tue, 16 Sep 2008 09:23:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 26, 8:53=A0am, "Robert F. Jarnot" <Robert.F.Jar...@jpl.nasa.gov>
wrote:
> Glenn,
>
> =A0 =A0 =A0 =A0 I have tried hard to get data on the Achronix parts, but =
have never
> succeeded in obtaining any useful/detailed information at all, nor have
> I ever received any kind of a response from the company when requesting
> information. =A0Have you come across a source of substantive data on thes=
e
> mysterious devices?

I just went there and the data sheet has a revision of Sep 15
(yesterday!).

That must be the "hottest" data sheet I have ever seen (in more than
one sense).

Very interesting technology, can't wait to hear more about it.

Tommy


Article: 135109
Subject: Re: Xilinx build system
From: sky465nm@trline4.org
Date: Tue, 16 Sep 2008 18:33:29 +0200 (CEST)
Links: << >>  << T >>  << A >>
Rob <BertyBooster@googlemail.com> wrote:
>Hi fellow forumers,

>We currently have lots of designs implemented with different versions
>of ISE. Often when a bug needs to be fixed on an old design the
>engineer will check out the code and find that it was last compiled
>with an older version of ISE. The user will therefore usually migrate
>to the latest version they have installed on their computer. In the
>past some designs have simply not built because of things like syntax
>changes with UCF files, but I am also worried about more subtle
>problems that might arise from using the newer ISE version.
>Also, when compiling large designs, a user's computer is utilised
>quite heavily (especially memory) limiting what can be done on that PC
>until the build finishes.

>For these reasons I was thinking of having an "ISE build PC" which has
>all of the versions of ISE we use installed on it. Then, using build
>scripts (tcl??), the build process can be automated and the process
>will be 100% repeatable and can be performed on an expensive behemoth
>PC rather than the user's work station.

* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
  http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine

* Network boot with different setups (PXE).

This way all the software instances will think they have the machine for
themselfes.


Article: 135110
Subject: Re: Xilinx build system
From: General Schvantzkopf <schvantzkopf@yahoo.com>
Date: Tue, 16 Sep 2008 12:20:19 -0500
Links: << >>  << T >>  << A >>
On Tue, 16 Sep 2008 07:05:01 -0700, Rob wrote:

> Hi fellow forumers,
> 
> We currently have lots of designs implemented with different versions of
> ISE. Often when a bug needs to be fixed on an old design the engineer
> will check out the code and find that it was last compiled with an older
> version of ISE. The user will therefore usually migrate to the latest
> version they have installed on their computer. In the past some designs
> have simply not built because of things like syntax changes with UCF
> files, but I am also worried about more subtle problems that might arise
> from using the newer ISE version. Also, when compiling large designs, a
> user's computer is utilised quite heavily (especially memory) limiting
> what can be done on that PC until the build finishes.
> 
> For these reasons I was thinking of having an "ISE build PC" which has
> all of the versions of ISE we use installed on it. Then, using build
> scripts (tcl??), the build process can be automated and the process will
> be 100% repeatable and can be performed on an expensive behemoth PC
> rather than the user's work station.
> 
> The thing is, I'm not sure how to implement such a thing, or indeed
> whether it is a sensible plan. I've had a look through the Xilinx Tcl
> stuff and there doesn't seem to be a way of getting a version for the
> tools that are being invoked.
> Has anyone implemented anything like this? Is it sensible??
> 
> Cheers
> Rob

It's trivial to do on Linux, just keep all of the different tool releases 
in separate directories and have your build scripts set the $XILINX 
variable to the path of the desired tools set and then set the search 
paths,

setenv PATH ${XILINX}/bin/${PLATFORM}:${PATH}
setenv LD_LIBRARY_PATH ${XILINX}/bin/${PLATFORM}:/usr/X11R6/lib:${LD_LIBRARY_PATH}

You don't need TCL for Xilinx scripts, simple shell scripts (csh or bash) 
are good enough. All of the Xilinx build tools (xst, ngdbuild, map, par) 
are meant to be used from the command line. If you want to see what the 
switches are to a tool just use the -h switch. For example to get the 
switches for par on a Virtex5 do 
par -h virtex5. 


Article: 135111
Subject: Re: Compiler Options
From: Jon Beniston <jon@beniston.com>
Date: Tue, 16 Sep 2008 10:22:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 16 Sep, 16:19, "ALu...@web.de" <ALu...@web.de> wrote:
> Hi Jon,
>
> the main reason for using that compiler option is to detect missing
> signals in sensitivity lists.
>
> ALuPin

Use @* if you're coding in Verilog.

Cheers,
Jon

Article: 135112
Subject: Re: Xilinx build system
From: Alex Colvin <alexc@TheWorld.com>
Date: Tue, 16 Sep 2008 20:15:16 +0000 (UTC)
Links: << >>  << T >>  << A >>
>* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
>  http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine

Definitely -- Eventually the different ISEs will require different OS 
releases or at least different versions of cygwin.

PCs in general are hostile to supporting more than one version of 
anything.

-- 
	mac the naf

Article: 135113
Subject: Re: Two JTAG Parallel IV Cable in a single PC.
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 16 Sep 2008 16:44:31 -0400
Links: << >>  << T >>  << A >>
> If it were me, I'd use one parallel, and one USB.  Or two USB.  Two
> parallel adapters on one PC is asking for trouble...

Two USB cables are not supported as far as I know. I am not sure about 2 
parallel. I did try using 1 USB and 1 parallel in the past and it worked.


/Mikhail 



Article: 135114
Subject: security system password by voice recognition commands
From: pemiliv <emrith@gmail.com>
Date: Tue, 16 Sep 2008 13:55:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
HI everyone, i'm starting in the world of DSP, i have a project its a
security system by voice patter recognition, and i have used
pic16f877a in others projects, but it seems not enough for dsp, thou
it has a ADC converter 10 bit - fmax = 20mhz, and i was thinking to
combine with fpga spartan 3a (sending the digital signal to spartan
and then maybe do some fft and filter processing ) ... but i friend of
mine has a  TMS320 C6713 dsk and he told to me that is better with it,
i new in all of this, i dont know how to use C6713 dsk ...so i need
some advice, baby steps that i could take to do this project, please
someone...

Article: 135115
Subject: Xilinx Spartan E
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 16 Sep 2008 16:16:39 -0700
Links: << >>  << T >>  << A >>
What happend to the Spartan E?

Is it eaten up by the Spartan 3A
and 3AN?

The Spartan 3A starter kit from
Xilinx looks like it's from Digilent.
But the Digilent web site didn't show
the Spartan 3A development kit.

Brad Smallridge
Ai Vision
 



Article: 135116
Subject: Re: Xilinx Spartan E
From: Eric Smith <eric@brouhaha.com>
Date: Tue, 16 Sep 2008 16:47:26 -0700
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> What happend to the Spartan E?

If you mean Spartan-3E, nothing happened to it.  It's still
readily available.

Article: 135117
Subject: Re: Xilinx build system
From: sky465nm@trline4.org
Date: Wed, 17 Sep 2008 02:55:12 +0200 (CEST)
Links: << >>  << T >>  << A >>
Alex Colvin <alexc@theworld.com> wrote:
>>* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
>>  http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine

>Definitely -- Eventually the different ISEs will require different OS 
>releases or at least different versions of cygwin.

>PCs in general are hostile to supporting more than one version of 
>anything.

Things PC lacks solid support for:
 * Serial or ethernet boot console.
 * Efficient instruction set (compare to mips/arm).
 * Virtualisation.

As for the default software side it tend to be single minded in all respects.

But it's cheap, and there was a saying in the 80's:
  .. No one got fired for buying IBM.
    Which the decision makers seem to subscribe to.


Article: 135118
Subject: Re: Ultra low power FPGAs
From: "Steve Knapp" <steveD.O.TknappA.Tprevailing-technologyD.O.Tcom>
Date: Tue, 16 Sep 2008 20:30:11 -0700
Links: << >>  << T >>  << A >>


"Michael Dreschmann" <michaeldre@gmx.de> wrote in message 
news:48ca60a7.262828953@news.t-online.de...
> Hi all!
>
> For an actual project I'm looking for an ultra low power FPGA. The
> size is not so important, we probably don't need much more resources
> that an CPLD would provide but power is absolutely critical.
> I heard already about Siliconblue but does someone of you know of any
> other devices playing in the same league to get some overview?
> Siliconblue seams to be very new on the market and this means a
> certain risk. Some nonvolatile config memory also would be preferable.
>
> Thanks,
> Michael

Hi Andy,

Depending on your power budget and density needs, I'd recommend looking at 
the following products.  The SiliconBlue and Actel parts are FPGAs, the 
Altera MAX IIZ and Xilinx parts are CPLDs.  The all have static currents 
measured in uA.

SiliconBlue iCE65 (ultra low power FPGA with uA current at 32 KHz, low mA 
dynamic in the MHz range, traditional 4-input LUT architecture)

Actel Igloo (also ultra low-power FPGA with uA standby current ("freeze" 
mode), a little higher static, higher dynamic, non-traditional FPGA 
architecture but high functional)

Altera MAX IIZ (low-density CPLD, good standby, higher dynamic due to 1.8V 
operating current, only two parts so far in the family)

Xilinx CoolRunner-II (low-density CPLD, good standby, higher dynamic due to 
1.8V operating current, broad family)

I've used all in different evaluations and projects (I've used the non-'Z' 
versions of the the MAX IIZ).  My experiences with the SiliconBlue part have 
been on their iCEman65 evaluation board.  I thought I blew out the 
SiliconBlue part because the needle on the current meter in my cheap bench 
supply sat on the bottom peg.  Fortunately, it was still alive and operating 
at 32.768 kHz, using a miserly 23 uA!

SiliconBlue and Actel both have a dynamic power advantage over the other 
folks (at the same density) because they operate at a lower voltage (IIRC, 
1.5V or 1.2V for Actel and 1.2V or 1.0V for SiliconBlue).  The others 
operate at 1.8V.  Dynamic power directly scales by the square of the input 
voltage.

If you can afford more power static power and need the extra density, I'd 
recommend looking also at the Altera Cyclone III FPGA family.  But, IIRC, 
the static currents are in the low mA range.

-- Steve Knapp
   www.prevailing-technology.com


Article: 135119
Subject: Free H/W Co-sim solution (Call for Wiki participation)
From: akineko <akineko@gmail.com>
Date: Tue, 16 Sep 2008 21:57:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello everyone,

We have developed H/W Co-simulation solutions, which you can bring
real hardware devices to your Verilog simulation.
To demonstrate that such H/W co-simulation solution is easy-to-use and
pragmatic in various projects, we have decided to provide one of our
solutions free of charge.
The solution is "SPIlink" and it allows you to take real SPI devices
into your simulation.
We have set up a public Wiki page so that you can obtain necessary
info and data from the Wiki page.

http://easycosim.wikispaces.com/

To use the solution, you need a Xilinx Spartan3A[N] Starter Kit Board
(FPGA image is provided) and Verilog simulator.
In addition to SPI devices, the SPIlink can be used to co-simulate
with real I2C devices (small external circuit required).

By having Wiki participation from wider audience in ASIC/FPGA design
community, we can enhance the Wiki page and the solution itself.
Please use Wiki's mail if you have any questions or requests regarding
to the free SPIlink solution.

We look forward to your participation.

Best regards,
Aki Niimura
Ponderosa Design

Article: 135120
Subject: Re: Moving to Altera from Xilinx
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Wed, 17 Sep 2008 08:03:31 +0100
Links: << >>  << T >>  << A >>
On Mon, 15 Sep 2008, cs_posting@hotmail.com wrote:

|-----------------------------------------------------------------------|
|"[..]                                                                  |
|                                                                       |
|[..]                                                                   |
|Wheras in more professional usage problems that can't  be solved in    |
|house might be more likely to end up with the FAE's than on the        |
|newsgroups."                                                           |
|-----------------------------------------------------------------------|

I had a simple problem created by Xilinx policy which could only be
resolved by a Xilinx employee (I do not control Xilinx's faulty
website therefore I can not fix it), which an idiotic Xilinx Field
Application Engineer did not manage to fix. Fortunately I started
another webcase on exactly the same complaint and was assigned a
different field application engineer, this time one who could
think. Unfortunately this incompetence of Xilinx's adversely delayed
me by weeks.

Article: 135121
Subject: Re: Compiler Options
From: "ALuPin@web.de" <ALuPin@web.de>
Date: Wed, 17 Sep 2008 04:01:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Jon,

I am using VHDL, so the sensitivity lists have to be completed
manually.

Rgds
ALuPin


Article: 135122
Subject: Random Mask Generation on FPGAs
From: Klaus Niedermayer <Klaus_Niedermayer@yahoo.com>
Date: Wed, 17 Sep 2008 12:15:11 +0100
Links: << >>  << T >>  << A >>
Hi

I would like to implement an encryption algorithm on my FPGA. The 
problem that I face here is that I need to generate each time I run
the algorithms 6 different random masks with 32-bits each. So I am 
wondering if anyone has a suggestion how to do that best? Until now I 
used LFSR to generate some single bits randomly, however now I should 
have in some way "independed" masks for 50.000 different runs.

Thanks!
Klaus

Article: 135123
Subject: Re: Random Mask Generation on FPGAs
From: Lorenz Kolb <lorenz.kolb@uni-ulm.de>
Date: Wed, 17 Sep 2008 13:26:45 +0200
Links: << >>  << T >>  << A >>
Klaus Niedermayer wrote:
> Hi
> 
> I would like to implement an encryption algorithm on my FPGA. The 
> problem that I face here is that I need to generate each time I run
> the algorithms 6 different random masks with 32-bits each. So I am 
> wondering if anyone has a suggestion how to do that best? Until now I 
> used LFSR to generate some single bits randomly, however now I should 
> have in some way "independed" masks for 50.000 different runs.
> 
> Thanks!
> Klaus


Hi,

what about using those few random bits You currently create for driving 
a chain of registers and adders used in pseudo noise sequences?

Depends on how "random" Your random values have to be ...

Regards,

Lorenz

Article: 135124
Subject: 1QN representation
From: knight <krsheshu@gmail.com>
Date: Wed, 17 Sep 2008 04:34:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi

how can i represent any number in 32 bit signed 1QN format..
Let the number be 1.5








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