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Messages from 134925

Article: 134925
Subject: Re: Are Xilinx tools that bad, or am I missing something?
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 07 Sep 2008 09:09:27 -0700
Links: << >>  << T >>  << A >>
thutt wrote:
<snip>
> At this point, 'kbd_leds' is not assigned inside
> 'harp_keyboard_controller', so then I tried to remove the signal from
> the entity declaration, and the corresponding assignment in the
> instantiation of the 'harp_keyboard_controller' entity.
> 
> I rebuilt my project and it fails to function properly.
<snip>

Are you certain that all the *other* I/O in your design are properly 
constrained to the pins you want?  An unconstrained pin will often move 
when other I/O are removed with unpredictable results.

Please let me know if you regularly visit *both* newsgroups or if only 
one is your normal place to search for responses.  Cross-posting to 
multiple newsgroups often causes more troubles than it solves.

Article: 134926
Subject: Re: Are Xilinx tools that bad, or am I missing something?
From: thutt <thutt151@comcast.net>
Date: 07 Sep 2008 09:33:13 -0700
Links: << >>  << T >>  << A >>
Muzaffer Kal <kal@dspia.com> writes:

> On 06 Sep 2008 20:12:16 -0700, thutt <thutt151@comcast.net> wrote:
> >The 'signal' at the top level isn't removed, it's still present and
> >quasi-used.  It works like this:
> >
> >   -- S3E demo board has 4 slider switches & 8 LEDs.
> >   -- I combine the switches and the LEDs to get 16 banks of 8 LEDs.
> >   -- I have an array, 16 x 8 of std_logic which corresponds to the
> >      LED values.
> >   -- The bank of LEDs which is actively connected to the actual
> >      on-board LEDs is selected by the slider switches.
> >
> >The signal which was assigned to the output port of the
> >'harp_keyboard_controller' entity was one element of the 16-element
> >array.  That element of the array was not used for anything else in
> >the design -- it's just for outputting the most recent byte received
> >from the attached PS2 keyboard.
> >
> >At the point that I removed the assignment to the output port in the
> >top level design, the 'harp_keyboard_controller' did not use the port
> >at all -- it did not assign anything to it at all; it was completely
> >unused.
> >
> >So, I just don't understand why removing a port that it unused can
> >make the design fail.
> 
> I have one question and a suggestion. What exactly do you mean by
> "project ... fails to function properly" ? What parts of it break
> down? That may help to figure out what's going on.

I'm working on building a single board computer using the S3E demo
board.  At present, I've gotten most of the component cobbled
together, and I've reached the point that I can actually write
software for the system.   I'm now working on writing a low-level
driver which will interpret the make & break codes from the PS2
keyboard.

I do not yet use the on-board RAM of the S3E board, but instead have
written a RAM simulator using the serial port on the S3E board which
is hooked up to a program running on my host computer.

When I start the RAM simulator program on the host computer, I give it
a binary file to load (the program I wish to run).

The current program I am running reads data from the keyboard and
outputs the hex values on the screen.  I'm using this information to
figure out how to write the low-level driver.

Finally, to answer your question, when the output port signal is
included in the 'harp_keyboard_controller' entity, the program which
I'm running actually executes until I stop it.

When I remove the 'kbd_leds' output port, the cpu executes a bunch of
instructions (probably a few hundred) and then hangs.

It's pretty obvious that something is wrong, but I just don't
understand how removing a completely unused signal can cause the
Xilinx tools to generate such a radically different output.

> The suggestion is based on an assumption. If you left the switch
> selection still at the keyboard output, does it help to change it to
> another of the 16 possibilities?

It makes no difference.  I was originally using index '8' into the
array.  I switched it to '0' and the design still works.

Last night I also made a new signal, 'gungla' in my top level design
and used that instead of the arbitrary index into the array.

The system fails in exactly the same way as if I had removed the
output port from 'harp_keyboard_controller'.

The next test was to remove the 'kbd_leds' output port, and use:

    leds(0) <= (others => '0");

in my top level entity.  In this case, the system also fails in the
same way.

So, somehow the design is now dependent upon using some index into the
16x8 array -- the array is used only for output to the LEDs.

If you're interested in more detail, you can check out the on-going
work at http://www.harp-project.com/

The site deliberately runs behind the work that I've actually
completed, so it's not up-to-date with this issue.

I've trimmed the posting list to just comp.arch.fpga.

-- 
Inconceivable!

Article: 134927
Subject: Re: Are Xilinx tools that bad, or am I missing something?
From: thutt <thutt151@comcast.net>
Date: 07 Sep 2008 09:34:04 -0700
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> writes:

> thutt wrote:
> <snip>
> > At this point, 'kbd_leds' is not assigned inside
> > 'harp_keyboard_controller', so then I tried to remove the signal from
> > the entity declaration, and the corresponding assignment in the
> > instantiation of the 'harp_keyboard_controller' entity.
> > I rebuilt my project and it fails to function properly.
> <snip>
> 
> Are you certain that all the *other* I/O in your design are properly
> constrained to the pins you want?  An unconstrained pin will often
> move when other I/O are removed with unpredictable results.
> 
> Please let me know if you regularly visit *both* newsgroups or if only
> one is your normal place to search for responses.  Cross-posting to
> multiple newsgroups often causes more troubles than it solves.

All the IO is constrained to specific pins using a constraints file.

-- 
Inconceivable!

Article: 134928
Subject: Re: Are Xilinx tools that bad, or am I missing something?
From: thutt <thutt151@comcast.net>
Date: 07 Sep 2008 09:35:44 -0700
Links: << >>  << T >>  << A >>
Sean Durkin <news_sep08@durkin.de> writes:

> thutt wrote:
>  > Am I misunderstanding something, or is the Xilinx software really that
> > bad?  In other words, should removing a completely unused signal cause
> > my design to be synthesized in a way so that it no longer works?
> > 
> > If that's the case, then can you explain to me how that can be?
> 
> What you describe very often happens when there are constraints missing,
> usually timing constraints.
> 
> When certain paths are not constrained, they tools just lay them out so
> it's most convenient for them. In many cases and with slow clocks this
> is not a problem. Modern FPGAs are fast, and if it's a slow clock and a
> small FPGA you can basically go around the entire chip twice and not
> have any timing issues.

All the I/O is actually constrained, but I have not done anything with
timing yet.  I guess I'll try to check out information about timing.
Thanks for the info.  Hopefully this will pan out.

thutt
-- 
Inconceivable!

Article: 134929
Subject: Re: Best way to buy Xilinx FPGAs?
From: Bob Smith <usenet@linuxtoys.org>
Date: Sun, 07 Sep 2008 10:19:00 -0700
Links: << >>  << T >>  << A >>
Rick Collins wrote:
 > I almost forgot.  They will also ask you for the "application".  They
 > are typically happy with something vague like, communications or
 > industrial control.  It is seldom that they ask for much specifics.  But
 > you might want to have something in mind just in case.  The most
 > important thing is to talk with confidence and be short and direct in
 > your answers.  Don't offer up any info they don't ask for.
 >
 > In some ways, it is a bit of fun.  But don't take it all too seriously.
 >
 > BTW, what *is* your application?  Are you building a prototyping
 > module?  What else will be on the board?


Yes, a prototyping board.  Our first board has a 100K Spartan 3E
in a 100 QFP on a PC/104 form factor card.  The board uses slave
parallel for download over USB.  This makes the board particularly
Linux friendly since you can program it without JTAG dongles or
special device drivers.


One final question. .... what kind of discounts are the norm
for 250 or 1000 piece orders?


thanks
Bob Smith

Article: 134930
Subject: Spartan 3E evaluation board manufacturers
From: "Alessandro" <apoppi@email.it>
Date: Sun, 7 Sep 2008 20:06:41 +0200
Links: << >>  << T >>  << A >>
Hi!

I'm the designer of this zx-spectrum clone project: 
www.zxbada.bbk.org/badaloc_fpga

I'm looking for evaluation board or starter kit manufacturers. May somebody 
provide me with the one from which he/she bought it's board?

I already own the Spartan 3E $149 board from xilinx, but I'm looking for 
something as close as possible to this configuration:

Spartan 3E 500 in PQ208 package
Almost any pin available on some kind of strip/connector
Fast static ram (example 1MB 10ns)
Spi prom for configuration
Power supply, xtal osc (50MHz would be perfect)
rs-232 port
Vga output

The spi prom is preferable to the dedicated xilinx prom because my project 
uses it as data (rom images) storage.
The PQ208 package is preferable because I'm planning to make a pcb which 
should be assembled "by hands"

I found this: 
http://www.sparkfun.com/commerce/product_info.php?products_id=8458 it's ok 
but missing ram and vga. I will add them on a separate pcb, I think, if I 
don't find anything closer to my requirements.

Thanks in advance and Best Regards!
Alessandro



Article: 134931
Subject: Re: Best way to buy Xilinx FPGAs?
From: dalai lamah <antonio12358@hotmail.com>
Date: Sun, 07 Sep 2008 18:13:31 GMT
Links: << >>  << T >>  << A >>
Un bel giorno rickman digit:

> You will need to give them a program name and an estimated annual
> quantity.  That quantity should be a minimum of 5000 per year; they
> don't/can't hold you to it.  To be safe, tell them the volume will
> start slowly, but it will ramp over the next year or two.  It will
> take about a week to get the quote and then you can turn around and
> put in the order.  You can refer to the 250 piece purchase as a pilot
> production run.

I wish I had a distributor so naive... :)

-- 
emboliaschizoide.splinder.com

Article: 134932
Subject: Re: Spartan 3E evaluation board manufacturers
From: Olaf Kaluza <olaf@criseis.ruhr.de>
Date: Sun, 7 Sep 2008 20:50:33 +0200
Links: << >>  << T >>  << A >>
Alessandro <apoppi@email.it> wrote:

 >I'm looking for evaluation board or starter kit manufacturers. 

I am not a manufacturer, but I was an owner of a ZX many years
ago. :-)

 >The PQ208 package is preferable because I'm planning to make a pcb which 
 >should be assembled "by hands"

I made this board for testing. It uses the VQ100, perhaps you like the
idea, because it is possible to use this kind of pcb on top of more
easier design.
If you like I can provide you with the eagle-file, but it has less IO
than a PQ208. But the good news, it is easy to made it by yourself.

http://www.criseis.ruhr.de/sany0465.jpg
http://www.criseis.ruhr.de/sany0466.jpg

BTW: Is is possible to push the ZX inside a XC3S100E? Or is it to
small?

Olaf

Article: 134933
Subject: Re: Spartan 3E evaluation board manufacturers
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 7 Sep 2008 21:18:38 +0200
Links: << >>  << T >>  << A >>
Alessandro wrote:

> I'm looking for evaluation board or starter kit manufacturers. May somebody 
> provide me with the one from which he/she bought it's board?

Take a look at this list:

http://www.fpga-faq.com/FPGA_Boards.shtml

Some nice header boards are available from Enterpoint, e.g. this one:

http://www.enterpoint.co.uk/moelbryn/darnaw1.html

But if it is already working with your board, why not designing the final
board with the components you need? Would be cool, if it fits inside a
joystick, like this one:

http://www.amazon.de/Commodore-DTV-Joystick-inkl-C64-Spieleklassiker/dp/B00094OCUG

> I found this: 
> http://www.sparkfun.com/commerce/product_info.php?products_id=8458 it's ok 
> but missing ram and vga. I will add them on a separate pcb, I think, if I 
> don't find anything closer to my requirements.

I don't think that it is a good idea to add external ram, because of the
high frequencies on the lines. But maybe a SDRAM, accessed with a lower
frequency, would work for your project.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134934
Subject: Re: Spartan 3E evaluation board manufacturers
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 7 Sep 2008 21:28:38 +0200
Links: << >>  << T >>  << A >>
Olaf Kaluza wrote:

> BTW: Is is possible to push the ZX inside a XC3S100E? Or is it to
> small?

Looks like it is too small. Someone wrote, that his Z80 project needed 2992
LUTs:

http://www.embeddedrelated.com/groups/fpga-cpu/show/2582.php

I think the Z80, only, should be below 1000 LUTs, but I don't think VGA and
the rest of the peripherals will fit in 2160 LUTs of the XC3S100E.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134935
Subject: Re: Spartan 3E evaluation board manufacturers
From: "Alessandro" <apoppi@email.it>
Date: Sun, 7 Sep 2008 21:44:07 +0200
Links: << >>  << T >>  << A >>
Olaf Kaluza wrote:

> I made this board for testing. It uses the VQ100, perhaps you like the
> idea, because it is possible to use this kind of pcb on top of more
> easier design.

Yes, that's exactly what the sparkfun site provides for the 3E 500.

> If you like I can provide you with the eagle-file, but it has less IO
> than a PQ208. But the good news, it is easy to made it by yourself.
>
> http://www.criseis.ruhr.de/sany0465.jpg
> http://www.criseis.ruhr.de/sany0466.jpg

Thanks a lot! But I think that moving to the PQ208 would require almost a 
large reworking

> BTW: Is is possible to push the ZX inside a XC3S100E? Or is it to
> small?

It is small. The current project (T80 plus the logic required for a working 
16K spectrum, would be more if I had access to the DDR ram onboard) takes 
about 25% of the 500. I think a 250 would be fine, as there are more than 
16KB of blockram available for video dualport purposes.

To tell it right, 8KB would be enough because you may "dualport" only the 
first half of the 16K bank and rely on external memory for the remainder 
(the video frame buffer is 6912 bytes). With 16K and more, however, a 128K 
spectrum may be syntesized (it requires two video banks).

Of course, anyone who own the xilinx 3E board is kindly requested to run my 
clone on it :-)

Ciao!
Alessandro



Article: 134936
Subject: Re: Spartan 3E evaluation board manufacturers
From: Olaf Kaluza <olaf@criseis.ruhr.de>
Date: Sun, 7 Sep 2008 22:16:50 +0200
Links: << >>  << T >>  << A >>
Frank Buss <fb@frank-buss.de> wrote:



 >I don't think that it is a good idea to add external ram, because of the
 >high frequencies on the lines. But maybe a SDRAM, accessed with a lower
 >frequency, would work for your project.

Why not sram? I think 512kb is enought for a few ZX Spectrum and
much easier to use than a SDRAM.

Olaf


Article: 134937
Subject: Re: Spartan 3E evaluation board manufacturers
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 7 Sep 2008 23:05:31 +0200
Links: << >>  << T >>  << A >>
Olaf Kaluza wrote:

> Why not sram? I think 512kb is enought for a few ZX Spectrum and
> much easier to use than a SDRAM.

SDRAM is very cheap, e.g. below $3 for larger quantities for 8 megabyte:

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=557-1072-1-ND

SRAM is more than 16 times more expensive:

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=428-2075-ND

It is not very difficult to integrate and access SDRAM in your own circuit
(if you don't use DDR) and would be nice to have a small platform with a
FPGA with 8mb RAM, VGA output etc., because then you can implement much
more than just a ZX Spectrum with it, e.g. a multichannel 100MHz logic
analyzer with 8mb memory and VGA output

Or install a MIPS processor on it (I hope they don't violate patents) :

http://opencores.com/projects.cgi/web/mips789/overview 

and compile Linux for it, which would be very difficult with 512kb.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134938
Subject: Re: Spartan 3E evaluation board manufacturers
From: "Alessandro" <apoppi@email.it>
Date: Sun, 7 Sep 2008 23:10:05 +0200
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> http://www.fpga-faq.com/FPGA_Boards.shtml

Interesting, I'm browsing it!

> Some nice header boards are available from Enterpoint, e.g. this one:
> http://www.enterpoint.co.uk/moelbryn/darnaw1.html

And this too.

> But if it is already working with your board, why not designing the
> final board with the components you need? Would be cool, if it fits
> inside a joystick, like this one:

I don't know if I could squeeze it in a so small space. My intention is 
making a board that could fit the original rubber keyboard of the 48K 
spectrum. In the original design, built around an xpla3 384 macrocells cpld, 
I put a lot of extra features such as sd-card snapshots, banked memory for 
ResiDOS compatibility (http://www.worldofspectrum.org/residos/) 21MHz 
maximum Z80 speed (this is based on a real Zilog PLCC44 Z80 chip), serial 
port for rs-232 based snapshots, programmable 10-inputs joystick (can be 
mapped on any of the spectrum 40 keys for total compatibility with any game) 
and vga scan conversion. I don't think I could make it so small.

> I don't think that it is a good idea to add external ram, because of
> the high frequencies on the lines.

Yes, I agree... but only the 3E 1600 would have enough ram to run a complete 
48K spectrum without any external memory (48K of ram plus 16 of rom are 
requireq for this thing to work). The 1200 only has 56K of blockram. 
Furthermore, the cpld clone works as a 128K spectrum too and 512K are 
required to run residos. Hence, I think I can't avoid external memory.

> But maybe a SDRAM, accessed with a
> lower frequency, would work for your project.

This is a painful matter. The Xilinx 3E development board does have a ddr 
chip installed, but I'm actually unable to use it because of the intricacies 
of ddr controllers. I took a look at what the MIG created: it's far more 
complicated than the whole project itself! And the source code was filled 
with "patches" made to get it work on the 3E board, where the correct "line 
pairs" wiring between ddr anf fpga was not taken into account for some 
reason I don't understand. Are ddr chips really so difficult to drive?

Another point is: the current project, which only relies on internal 
blockram, runs the T80 at 42MHz with no problem. I'm not sure a ddr chip 
would have a so low latency to be able to supply the randomly accessed data 
in such a short amount of time (a T80 opcode fetch currently enables the 
MREQ for just ONE clock cycle. A "data" memory access it two clock periods 
long).

21MHz would be fine enough, but I think it could not work either. Imho the 
only way is a fast static ram, such as one of the many 512K / 1MB 10ns chips 
available on the market.

If I'm wrong, and someone could tell a way to access the ddr on the xilinx 
board in a fast enough way, any suggestion is of course appreciated! I've 
heard of many people spending a lot of time to get a ddr work and the whole 
matter seems a little critical, I mean I would be afraid using such a chip 
on final board because it looks very path/wiring/etc sensitive. I feel more 
comfortable with static ram. Furthermore, I don't need such an amount of 
storage.

On the fpga side, the reason for using the PQ208 package is the relatively 
easy "hand" soldering combined to a nice amount of logic and blockram.

The current .bit file on the website, when loaded into the xilinx board, 
cycles a few border colors (those familiar with zx-spectrum knows what I'm 
talking about) waiting for a bootrom to be uploaded by rs-232 then reads a 
16K rom image from spi flash address $10000 (1MB offset). If a spectrum 16K 
rom was programmed there, then you had a VGA-PS/2 keyboard 16K spectrum :-)

Ciao!
Alessandro



Article: 134939
Subject: Re: Spartan 3E evaluation board manufacturers
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 7 Sep 2008 23:19:00 +0200
Links: << >>  << T >>  << A >>
Alessandro wrote:

> Are ddr chips really so difficult to drive?

Yes. And designing your own board with DDR SDRAM needs a lot of knowlegde
(or expensive programs) for routing and very expensive scopes for searching
bugs (and most likely your first board with DDR SDRAM won't work).

Use non-DDR SDRAMs in your design. I'm not sure, but I think there is no
lower limit for the clock and you can implement your own SDRAM controller,
which is easy, if you don't need the highest performance with burst-access,
caching etc.

SRAM would work, too, but then you can run small systems on it, only, and
not something more interesting, like Linux.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134940
Subject: Re: Spartan 3E evaluation board manufacturers
From: "Alessandro" <apoppi@email.it>
Date: Sun, 7 Sep 2008 23:24:22 +0200
Links: << >>  << T >>  << A >>
Frank Buss wrote:
> Olaf Kaluza wrote:

> It is not very difficult to integrate and access SDRAM in your own
> circuit (if you don't use DDR) and would be nice to have a small
> platform with a FPGA with 8mb RAM, VGA output etc., because then you

I agree. I will take a look at sdram (I suppose they are single data rate, 
opposed to double data rate of ddr) to see if I can afford the intricacies 
of controlling it. Are sdram going to be obsolete because of ddr, or is it a 
"parallel" market?

I've also found  this interesting board 
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable 
with 16MB of "cellular ram", or psdram, which can be accessed like an 
asynchronous chip (self refresh is internally provided) but, unfortunately, 
it's speed is 70ns in async mode.

> can implement much more than just a ZX Spectrum with it, e.g. a
> multichannel 100MHz logic analyzer with 8mb memory and VGA output

It would be nice!

Ciao
Alessandro



Article: 134941
Subject: Re: LVDS Receiver in FPGA
From: Not <nospam@yahoo.com>
Date: Sun, 07 Sep 2008 19:11:30 -0700
Links: << >>  << T >>  << A >>
I'm currently working on a board with two Virtex-5
parts running LVDS IO between the two FPGAs.  The interface
between the FPGAs is 23 pairs of LVDS, with a source
synchronous clock.  This is using a modified version
of the ChipSync logic documented in XAPP860.  The LVDS
IO is running DDR at 500MHz giving 1Gbs per pair, or 23 Gbps
total.

We also have an interface running at 644MHz, but that
is not yet tested.

I haven't looked at running without a source sync clock,
but it should be possible if you are willing to put in
a method to adjust the delay on either the clock, or each of
the data pairs (IDELAY + logic).  Again look at XAPP860.

If you need clock recovery, the look at the Xilinx parts
with RocketIO.


woko wrote:
> Hi FPGA specialist,
> 
> we are would like to know if it is currently possible to implement
> high speed LVDS receiver or transmitter in FPGAs.
> 
> Our next gerneration PCB board would have about 12 LVDS receiver
> (SN65LV1224B) , 6 LVDS  transmitter (SN65LV1023A) and an FPGA
> onboard.
> Please note that the LV1224 and LV1023 transmit thair LVDS in a single
> differential line, there is no LVDS clock pair necessary. The clock
> speed would be 48Mhz which would lead to a LVDS bandwidth of 576Mbs
> (12bit transmitting).
> It would save us money and FPGA IOs if we could get the serialization
> and deserialization  in the FPGA.
> 
> I could find application notes about LVDS in a cyclone3, but I don't
> think that reception works without a clock pair.
> 
> Is anybody out there which as experience with this kind of LVDS in a
> FPGA?
> We would be obliged for some practical hits...
> 
> 
> Curious about your answers,
> Wolfgang Kopp
> 
> 
> 

Article: 134942
Subject: Re: Spartan 3E evaluation board manufacturers
From: "MikeWhy" <boat042-nospam@yahoo.com>
Date: Mon, 8 Sep 2008 00:14:34 -0500
Links: << >>  << T >>  << A >>

"Alessandro" <apoppi@email.it> wrote in message 
news:ga157k$6ck$1@aioe.org...
> Hi!
>
> I'm the designer of this zx-spectrum clone project: 
> www.zxbada.bbk.org/badaloc_fpga
>
> I'm looking for evaluation board or starter kit manufacturers. May 
> somebody provide me with the one from which he/she bought it's board?
>
> I already own the Spartan 3E $149 board from xilinx, but I'm looking for 
> something as close as possible to this configuration:
>
> Spartan 3E 500 in PQ208 package
> Almost any pin available on some kind of strip/connector
> Fast static ram (example 1MB 10ns)
> Spi prom for configuration
> Power supply, xtal osc (50MHz would be perfect)
> rs-232 port
> Vga output

There's this: http://www.knjn.com/board_Xylo.html. Seems way overpriced at 
$300 USD.

Also take a look at Digilent's Nexys2 
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable. 
$100 USD. Sounds like a good match except the FG320 package, 16 MB SDRAM, 
and Xilinx platform flash. VGA output is 8-bit color only.

Why not go straight for your own protoboard instead? Can't you just simulate 
the SRAM if you're concerned about timing?



Article: 134943
Subject: Signed multiplication
From: knight <krsheshu@gmail.com>
Date: Sun, 7 Sep 2008 23:10:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi

Can anyone tell me how can i multiply two signed numbers in FPGA.
How the logic is really implemented..
ie., if i multiply two signed numbers are they multiplying the
positive number and the 2's complement (if the number is negative)
directly ..?
Or are they really changing the negative number to positive and do
normal multiplication and appends the sign accordingly..?
And is the positive number, and its 2's complement form same always...?

Article: 134944
Subject: Re: need sme help on data encryption based on fpga
From: Mark McDougall <markm@vl.com.au>
Date: Mon, 08 Sep 2008 18:04:19 +1000
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:

> The other proudly proclaims that you while you need help
> badly enough to shout your request out into a field of total strangers,
> you can be bothered neither to 

I also suspect that if someone did actually feel charitable enough to
help, anything less than fully working source code (or perhaps even a
synthesized bitstream) would either be ignored or met with a request for
further assistance in producing said bitstream.

Any generic 'help' request posted with such obvious apathy deserves to be
thoroughly ignored IMHO.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 134945
Subject: Re: Signed multiplication
From: "RCIngham" <robert.ingham@gmail.com>
Date: Mon, 08 Sep 2008 04:17:05 -0500
Links: << >>  << T >>  << A >>
>hi
>
>Can anyone tell me how can i multiply two signed numbers in FPGA.
>How the logic is really implemented..
>ie., if i multiply two signed numbers are they multiplying the
>positive number and the 2's complement (if the number is negative)
>directly ..?
>Or are they really changing the negative number to positive and do
>normal multiplication and appends the sign accordingly..?
>And is the positive number, and its 2's complement form same always...?
>

It depends on the FPGA and the way you specify the multiplication
operation.

If it uses a hardware "DSP" or "MAC" resource, the logic internal to that
block will know what to do with the sign bits.

Otherwise, the synthesis tool will know how to handle the bits if, for
instance, you are writing in VHDL and declare the signals to be of type
'signed'.

What FPGA are you using?
What language are you writing in?
Why don't you do some experiments and look at the log files and gate-level
netlist?
Have you tried multiplying -1 x -1?


Article: 134946
Subject: Re: Best way to buy Xilinx FPGAs?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Mon, 08 Sep 2008 12:03:04 +0100
Links: << >>  << T >>  << A >>
On Sun, 07 Sep 2008 10:19:00 -0700, Bob Smith <usenet@linuxtoys.org>
wrote:


> > BTW, what *is* your application?  Are you building a prototyping
> > module?  What else will be on the board?
>
>
>Yes, a prototyping board.  Our first board has a 100K Spartan 3E
>in a 100 QFP on a PC/104 form factor card.  The board uses slave
>parallel for download over USB.  This makes the board particularly
>Linux friendly since you can program it without JTAG dongles or
>special device drivers.
>
>
>One final question. .... what kind of discounts are the norm
>for 250 or 1000 piece orders?
>
If you go to em.avnet.com and search for specific Xilinx part numbers
you will find prices. For most devices I have tried, (e.g. XC3S2000) you
get 1-off, 25 and 100-off prices, e.g. 

1-$140.4000
25-$117.5400
100+-$98.6400

which can perhaps be used to calibrate your expected discount, or at
least place bounds on it. 

However for the XC3S100E only the 1-off price is shown ($11.56) - it may
be worth calling them, or trying the same search on NuHorizons.com

- Brian

Article: 134947
Subject: Re: Signed multiplication
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Mon, 08 Sep 2008 12:14:12 +0100
Links: << >>  << T >>  << A >>
On Sun, 7 Sep 2008 23:10:31 -0700 (PDT), knight <krsheshu@gmail.com>
wrote:

>hi
>
>Can anyone tell me how can i multiply two signed numbers in FPGA.
>How the logic is really implemented..
>ie., if i multiply two signed numbers are they multiplying the
>positive number and the 2's complement (if the number is negative)
>directly ..?
>Or are they really changing the negative number to positive and do
>normal multiplication and appends the sign accordingly..?
>And is the positive number, and its 2's complement form same always...?

If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5)
for most FPGAs you just use the * operator and expect the tools to use
the in-built multipliers.

For more details, read the documentation on these multiplier or DSP48
blocks.

For larger operators, this works well enough as long as you don't need
the highest achevable speeds (maybe this is fixed in ISE 10?).

But if you are "rolling your own" multiplier (perhaps to get a properly
pipelined 32*32 multiplier for speed, using the internal components) the
easiest way is to convert to unsigned numbers, and handle the sign bits
separately.

- Brian

Article: 134948
Subject: Re: Signed multiplication
From: Jon Beniston <jon@beniston.com>
Date: Mon, 8 Sep 2008 04:35:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 Sep, 07:10, knight <krshe...@gmail.com> wrote:
> hi
>
> Can anyone tell me how can i multiply two signed numbers in FPGA.
> How the logic is really implemented..
> ie., if i multiply two signed numbers are they multiplying the
> positive number and the 2's complement (if the number is negative)
> directly ..?
> Or are they really changing the negative number to positive and do
> normal multiplication and appends the sign accordingly..?
> And is the positive number, and its 2's complement form same always...?

How many bits of the result do you need? If you only need the same
number of output bits as input, I don't think it matters whether the
numbers are signed or unsigned.

Jon

Article: 134949
Subject: No connect pins on xc4vfx20
From: michaeldre@gmx.de (Michael Dreschmann)
Date: Mon, 08 Sep 2008 12:00:09 GMT
Links: << >>  << T >>  << A >>
Hi!

I'm doing a layout for an xc4vfx20 Virtex4. In the pinout datasheet on
page 249 (figure 3-7) there are some pins described as "no connect".
May I connect them to anyting or mustn't I connect them? In the first
case I could use them to route signals to pads more in the center of
the BGA.

Thanks,
 Michael



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