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Messages from 73400

Article: 73400
Subject: Re: Bi Dir Synthesis Problem in Quartus?
From: "Subroto Datta" <sdatta@altera.com>
Date: Tue, 21 Sep 2004 14:18:23 GMT
Links: << >>  << T >>  << A >>
You need to use Quartus II 3.0 or higher. Look carefully in the upper right 
corner of the Assignment Editor. It is locate to the right of the Timing 
button and above the Check All button. On a side note the default value of 
the Preserve Hierarchical Boundary setting is Off. So if you did not turn it 
on in the first place, you are running into something else. One thing you 
may want to do is export the OE signal and the dataout as outputs from the 
lower level block and then feed them into a tristate upper at the top level.

- Subroto Datta
Altera Corp.

"Ryan" <ryanspicer@tecton.co.uk> wrote in message 
news:462a3d93.0409210256.6894c9d8@posting.google.com...
> Hi Subroto
>
> Thanks for your response. This may be a really stupid question but I
> dont seem to have a 'logic options' button in the assignment editor!
> How do I display it?? I cant find where to turn it on in the 'view'
> options.
>
> Thanks again
> Ryan
>
>
> "Subroto Datta" <sdatta@altera.com> wrote in message 
> news:<IKB3d.10962$YD.8442@newssvr31.news.prodigy.com>...
>> . I have looked at the help files
>> > under "preserve hierarchical boundary logic option" and it recommends
>> > that I turn the "preserve_hierarchical_boundary" setting to off. I
>> > can't find this option in the Assignment editor as it suggests. Where
>> > would I be able to change this setting which supposedly would cure my
>> > bi-directional synthesis problem?
>>
>> >
>> > Thanks
>> > Ryan
>>
>>
>> Hi Ryan,
>>     You can make this seting from the Assignment Editor->Logic Options
>> Panel. Open the Assignment Editor and click on the Logic Options button 
>> in
>> the upper right hand corner. Once this is done, if you click on the
>> Assignment Name field you should see this setting in the drop down. This
>> Assignment should be applied to the Instance of A for which you want to 
>> turn
>> this value OFF. This is specified in the To field of the Assignment 
>> Editor.
>>
>> Therefore the easiest sequence of steps is:
>>
>> 1. Open the Project Navigator->Hierarchy Tab.
>> 2.Find the instance of A for which hierarchy should not be preserved.
>> 3.Right click on the instance and select Locate in Assignment Editor. You
>> will see a row with the Instance name in there.
>> 4.Click on the Logic Options button in the upper right hand corner of the
>> Assignment Editor.
>> 5. Select the Preserve Hierarchy Boundary setting in the cell that is at 
>> the
>> intersection of Assignment Name and the row in Step 3.
>> 6. Set the value in the cell adjacent to the cell in Step 5 under the 
>> Value
>> column.
>>
>> Hope this helps.
>> Subroto Datta
>> Altera Corp. 



Article: 73401
Subject: Re: bad nph file
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 21 Sep 2004 14:35:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
Rune Christensen <rune.christensen@adslhome.dk> wrote:
 : Hello

: I'm using the xilinx webpack and I get an error about a bad nph file.

: The problem is that I want to use a Spartan2 xc2s200-5pq208.

: I'm using webpack 6.3.01i

: Loading device for application Xst from file 'v200.nph' in environment 
: F:/Xilinx.
: FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file 
: Process will terminate.  To resolve this error, please consult the Answers 
: Database and other online resources at http://support.xilinx.com. If you 
: need further assistance, please open a Webcase by clicking on the "WebCase" 
: link at http://support.xilinx.com
: ERROR: XST failed
: Process "Synthesize" did not complete.

: Can someone tell me what is wrong?

You pulled webpack 6.3 too early.
 
During installation, a lot of files get first installed and then erased.

Webcase first told me something like: "You did something wrong, probably
having some old installations in the background. Go, reinstall" but now
webpack 6.3 was withdrawn and a reworked webpack is to be expected soon.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 73402
Subject: Re: Stratix II vs. Virtex 4 - features and performance
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 21 Sep 2004 14:46:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <5c156a0b.0409202037.2c3ce6b4@posting.google.com>,
Dave Greenfield <davidg@altera.com> wrote:
>Stratix II Design Security:

>The Stratix II devices come with both the non-volatile key and
>volatile key storages for design security.  Altera chose to only
>market the non-volatile key solution because it delivers the optimal
>features and functionality for customers. A volatile key solution
>requires a battery to backup the key when the power is off, which is
>not ideal as it increases the cost of the solution, board
>manufacturing complexity and is simply less reliable.   Significant
>protections is put in place to make sure the non-volatile key is
>secure within the Stratix II FPGA.
>
>Reading poly fuses on a 9 layer 90nm process is not trivial. It cannot
>be done in "less than an hour". Our feature has been designed to make
>it as painful as possible to crack, and has been verified by
>independent security consultants. Since all crypto systems are
>crackable, including ones by our competitors, it is a question of how
>much money and time one is willing to spend on this endeavor.

Give me enough of a reason: $$$, and geting the fuses out in less than
an hour as a repeat performance wouldn't be a problem.  

Call me biased, but please market the volatile-key solution, as this
forces sidechannel attacks and other tricks to be used.  It's still
not perfect, but it is a LOT better.

>The battery solution for a volatile key provides no data integrity.
>What is the purpose of having security if you can over write a
>"supposedly secure design" (a design that has been loaded with an
>encrypted bit-stream) with any other design. You can do this in Virtex
>4 devices which have a security key on board. A hacker can load a new
>design into a device with a security key onboard without knowing the
>key that resides onboard. He can also change the original key itself.
>A poly fuse system provides data integrity since the only bit-stream
>you can load is the encrypted bit-stream. A hacker trying to load any
>other bit-stream will be not be successful in loading the device and
>cannot change the original design.

True, BUT:  If you are in a position where an attacker CAN load a
bitfile of his choice/physical access to the board, you've lost
anyway.  I can see an advantage to authentication, but not enough to
weaken confidentiality by using non-volatile memory for the keys.

>A 256 bit key in this situation provides minimal added security beyond
>a 128 bit key. 

For some strange reason, the NSA doesn't fully agree.  In their
authorization of AES for use in secured governmental communication,
they require that Secret and Top Secret use 192 or 256 bit keys.

I agree that in practice it won't make a difference, but you can't
blame em for the marketing advantage.

>If you are going to spend the money to attempt cracking
>either Altera or Xilinx devices by reverse engineering the silicon,
>the entire method is dependent on how difficult you make the reverse
>engineering rather than the key length.

And THIS is why you should push the volatile solution.  You have a
group of nonvolatile cells.  The work in reverse engineering is going
to be a strong O(1) operation, as once it is done, it is simply a
matter of delidding the chip, probing in the right places, and reading
the results.

Compared with the volatile solution: you are probably going to need to
do power or signal analysis on the encryption in action.  Which means
you are probably going to need to add probes to the power/ground pins,
on a live board, without disrupting the power supply to the
configuration loader (which can be made even harder by potting the
FPGA with wires for the config voltage around it).
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 73403
Subject: Re: Stratix II vs. Virtex 4 - features and performance
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 21 Sep 2004 14:48:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <b890a7a.0409210258.6490580d@posting.google.com>,
Kolja Sulimma <news@sulimma.de> wrote:
>> Since no known method exists
>> for cracking AES, a brute force attack is the only way to attempt to
>> crack the key. 
>Nope. 
>Ever heard of differential power analysis?

Well, thats a side-channel attack on IMPLEMENTATIONS.  Probably the
best way to attack the Xilinx bitfile security is either power or EM
(signal) analysis, or figuring out a weakness in the readback
protection.

The best way to attack the Altera-marketed approach is just
know-where-to-sand-and-drill.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 73404
Subject: Re: Virtex 4 integrated A/Ds? Yes it does.
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 21 Sep 2004 08:17:29 -0700
Links: << >>  << T >>  << A >>
Jerry,

Well, that is a good question.  Since we are the first to ever put an 
A/D on an FPGA, I would suggest that it is not as easy as you suggest.

PLLs, Serdes, A/D, all have a similar problem:  they want it quiet!

Problem with a FPGA is that generally speaking, they are not very quiet 
at all.

It is a significant challenge to put a very sensitive circuit right next 
to a 50KW transmitter, and expect it to not be affected by it.

Also, making analog elements in a straight CMOS logic process is no 
simple task either.  Digital process guarantees that the transistors 
switch on, and off, quickly.  That is about it.  Try to make an analog 
design in a digital process that will yield 100%.

All extremely challenging, and by no means a solved problem.

Once we have a proven A/D technology that meets all requirements, then 
we can discuss market needs.  Until then, the system monitor is a 
relaxed application (temperature, voltage) that does not require the 
kinds of static and dynamic specifications that challenge most A/Ds.

The DLL grew into the DCM/PMCD...etc.  Other fetaures have also grown 
and improved with time in subsequent generations.  The A/D is just one 
more element in that 'toybox.'

Austin

Jerry wrote:
> While the subject is open, Austin why doesn't Xilinx integrate higher
> performance A/Ds on board.
> Say 60 Msps, 10 to 12 bits would be nice. Is it a matter of market demand?
> 
> "Austin Lesea" <austin@xilinx.com> wrote in message
> news:cino83$k6j1@cliff.xsj.xilinx.com...
> 
>>Michael,
>>
>>Yes.
>>
>>The 200Ks/s successive approximation converter eight differential 1 V
>>p-p inputs, as well as the Vccint sense channel, and the temperature
>>sense channel.  There are alarm registers for all channels, and various
>>modes it can operate in.  Upon power up, before configuration, the A/D
>>is in monitor mode, and outputting data if needed using a JTAG command.
>>
>>The temperature sensor has a shut down feature to prevent operation in
>>excess of the absolute maximum specified ratings.
>>
>>The primary purpose for the A/D is to sense internal voltages, and the
>>die temperature.  I don't know how many times you have wanted to know
>>the die temperature, but we need to know that quite often, especially
>>when someone claims that the device is not meeting timing (which it
>>usually is, except they are running it at 110C!).
>>
>>Lots to learn here about what the A/D might be useful for.  One
>>application is to detect tampering in security applications, among others.
>>
>>Austin
>>
>>Michael wrote:
>>
>>>Does anyone know if it is possible to use the "system monitor" analog
>>>inputs as regular A/Ds and use the digital data output from these
>>>convertors as inputs to internal logic in the FPGA?
> 
> 
> 

Article: 73405
Subject: Re: Ring Oscillator Redux
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 21 Sep 2004 08:20:20 -0700
Links: << >>  << T >>  << A >>
Ben,

KEEP or SAVE.

Austin

Ben Jackson wrote:

> In article <6fO3d.84788$D%.79178@attbi_s51>,
> Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:
> 
>>There was a thread about ring oscillators recently.  I tried to build one in
>>a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the
>>ring of inverters into a single inverter.
> 
> 
> Maybe the KEEP attribute would work?
> 
> http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0125_78.html
> 

Article: 73406
Subject: Re: Stratix II vs. Virtex 4 - power
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 21 Sep 2004 08:49:03 -0700
Links: << >>  << T >>  << A >>
Dave,

V4 works, we have data, and we have parts.

No risk.

Yields are already  excellent.

Notice the million 90 nm S3 sold announcement today?

Sounds like you folks are still driving wafers to get yield?  Too bad.

As for "judicious use of low Vt": come on, who are you trying to fool?

Everyone has done that since .35 micron technology node.  It doesn't 
work anymore.  Look at your own leakage data.  Why folks are just plain 
angry and upset when they see those leakage numbers (not to mention the 
surge).

Makes it hard for us, as we actually have to show them our working parts 
on boards and the presentation on triple oxide before they believe us. 
After all, Intel, TI, IBM are all making chips that boil water as well....

Intel with its chips that fry systems is just one example of a total 
failure to address power (because they can not).  Why did they (Intel, 
TI, IBM) not use triple oxide?  Because they need every one of their 
transistors to be the fastest possible, so they can not take advantage 
of it.  ASIC design is a different animal.  They can not derive any 
benefit from triple oxide.  That is why they do not use it.  You knew that.

You, and we, do not need every transistor to be as fast as possible. 
For example, the configuration memory need not be fast.  In fact, making 
the config memory with 130 nm transistors in V4 makes it more immune to 
single event upsets AND gives us low leakage!  How is that for a direct 
user benefit? (that you do not offer)

No comparison, no contest.

If all you have is FUD, you'd better go back and find something else to 
talk about on this board.

Austin

Dave Greenfield wrote:

> Responding to comments on 90-nm power . . . 
> 
> Claims here are challenging to understand. It appears that Xilinx
> suggest power goes down by 50% at the same time performance doubles,
> due mainly to a triple oxide process (benefit to leakage power) and
> embedding hard IP (benefit to dynamic power). Let's take a look at
> these claims.
> 
> Leakage and triple oxide: Xilinx claims triple oxide is used in CRAM
> to reduce leakage current by 50%. In Stratix II, CRAM accounts for 5%
> of total leakage. Does this imply CRAM leakage in Virtex devices had
> been 50% of the chip's total leakage? Current collateral also glosses
> over the tradeoffs of triple oxide, which the rest of the industry
> (including the likes of Intel, TI, IBM, etc.) have analyzed and have
> deemed too risky and too costly at 90nm for the small benefit
> provided. Triple oxide adds die size (larger transistors). It also
> requires ~4 more wafer processing steps. Both of these aspects
> increase the wafer cost. Both of these factors also reduce yield.
> Because there are now not two, but three different oxides it takes
> longer to tighten up the process and thus deliver sustainable, regular
> yields (i.e. guaranteed delivery). Finally, rapid yield enhancement
> requires driving wafer volume, but the limited use of triple oxide at
> either UMC or some other potential foundry highlights that Virtex 4
> may be stuck driving the triple oxide yield enhancement alone.
> 
> Dynamic power and the benefits of embedding more hard IP: Xilinx
> suggests dynamic power goes down by a factor of 7x by embedding hard
> IP. The Virtex 4 documentation suggests the new multipliers run up to
> 500 MHz and consume only 57 uW/MHz. In the SX55 device (with 512
> multipliers), that is 15 W of dynamic power just for DSP. Dynamic
> power for the core, RAMs, and I/O, and then leakage are on top of
> this. I'll assume the 7x factor likely doesn't apply here. Low-k helps
> reduce dynamic power by about 10% and gives a boost to performance of
> ~ 10% (part of Altera's power reduction arsenal). It doesn't look like
> Virtex 4 will get this low-K benefit.
> 
> There are other process techniques besides triple oxide to reduce
> leakage power.  For instance, Altera implements different Vt's using
> different implants to reduce leakage power.  This is how we get a low
> leakage CRAM.  It is safer than triple-oxide, and yields leakage power
> reductions that are quite similar.  We also judiciously apply
> non-minimum length transistors.  Configuration RAM is a solved problem
> since there is no performance requirement, we can use both these
> techniques to greatly reduce sub-threshold leakage.
> 
> The Stratix II ALM is power-friendly.  (1) It reduces the number of
> logic levels, so we can use lower leakage routing transistors and
> maintain speed.  (2) It reduces the amount of routing needed by
> absorbing more logic into the larger logic functions, so we replace
> the still-somewhat-leaky routing transistors with low-leakage CRAM
> cells.
> 
> My assessment is that Virtex 4 is primarily trying to get power
> reductions through process techniques, while most of the semiconductor
> industry has concluded this is not sufficient -- you also need to get
> gains at the architecture level.
> 
> Dave Greenfield
> Sr. Director of Product Marketing  High Density FPGAs
> Altera Corporation

Article: 73407
Subject: Re: Stratix II vs. Virtex 4 - power
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 21 Sep 2004 09:07:04 -0700
Links: << >>  << T >>  << A >>
Further,

We used:

- low Vt transistors
- architectural improvements
- design improvements
- three oxides

Why?  Because we have to in order to meet our customer's needs.

So do not compare us with a "gas guzzler" using old technology, old 
design, and old architectures.

No comparison, no contest.

Austin

Austin Lesea wrote:
> Dave,
> 
> V4 works, we have data, and we have parts.
> 
> No risk.
> 
> Yields are already  excellent.
> 
> Notice the million 90 nm S3 sold announcement today?
> 
> Sounds like you folks are still driving wafers to get yield?  Too bad.
> 
> As for "judicious use of low Vt": come on, who are you trying to fool?
> 
> Everyone has done that since .35 micron technology node.  It doesn't 
> work anymore.  Look at your own leakage data.  Why folks are just plain 
> angry and upset when they see those leakage numbers (not to mention the 
> surge).
> 
> Makes it hard for us, as we actually have to show them our working parts 
> on boards and the presentation on triple oxide before they believe us. 
> After all, Intel, TI, IBM are all making chips that boil water as well....
> 
> Intel with its chips that fry systems is just one example of a total 
> failure to address power (because they can not).  Why did they (Intel, 
> TI, IBM) not use triple oxide?  Because they need every one of their 
> transistors to be the fastest possible, so they can not take advantage 
> of it.  ASIC design is a different animal.  They can not derive any 
> benefit from triple oxide.  That is why they do not use it.  You knew that.
> 
> You, and we, do not need every transistor to be as fast as possible. For 
> example, the configuration memory need not be fast.  In fact, making the 
> config memory with 130 nm transistors in V4 makes it more immune to 
> single event upsets AND gives us low leakage!  How is that for a direct 
> user benefit? (that you do not offer)
> 
> No comparison, no contest.
> 
> If all you have is FUD, you'd better go back and find something else to 
> talk about on this board.
> 
> Austin
> 
> Dave Greenfield wrote:
> 
>> Responding to comments on 90-nm power . . .
>> Claims here are challenging to understand. It appears that Xilinx
>> suggest power goes down by 50% at the same time performance doubles,
>> due mainly to a triple oxide process (benefit to leakage power) and
>> embedding hard IP (benefit to dynamic power). Let's take a look at
>> these claims.
>>
>> Leakage and triple oxide: Xilinx claims triple oxide is used in CRAM
>> to reduce leakage current by 50%. In Stratix II, CRAM accounts for 5%
>> of total leakage. Does this imply CRAM leakage in Virtex devices had
>> been 50% of the chip's total leakage? Current collateral also glosses
>> over the tradeoffs of triple oxide, which the rest of the industry
>> (including the likes of Intel, TI, IBM, etc.) have analyzed and have
>> deemed too risky and too costly at 90nm for the small benefit
>> provided. Triple oxide adds die size (larger transistors). It also
>> requires ~4 more wafer processing steps. Both of these aspects
>> increase the wafer cost. Both of these factors also reduce yield.
>> Because there are now not two, but three different oxides it takes
>> longer to tighten up the process and thus deliver sustainable, regular
>> yields (i.e. guaranteed delivery). Finally, rapid yield enhancement
>> requires driving wafer volume, but the limited use of triple oxide at
>> either UMC or some other potential foundry highlights that Virtex 4
>> may be stuck driving the triple oxide yield enhancement alone.
>>
>> Dynamic power and the benefits of embedding more hard IP: Xilinx
>> suggests dynamic power goes down by a factor of 7x by embedding hard
>> IP. The Virtex 4 documentation suggests the new multipliers run up to
>> 500 MHz and consume only 57 uW/MHz. In the SX55 device (with 512
>> multipliers), that is 15 W of dynamic power just for DSP. Dynamic
>> power for the core, RAMs, and I/O, and then leakage are on top of
>> this. I'll assume the 7x factor likely doesn't apply here. Low-k helps
>> reduce dynamic power by about 10% and gives a boost to performance of
>> ~ 10% (part of Altera's power reduction arsenal). It doesn't look like
>> Virtex 4 will get this low-K benefit.
>>
>> There are other process techniques besides triple oxide to reduce
>> leakage power.  For instance, Altera implements different Vt's using
>> different implants to reduce leakage power.  This is how we get a low
>> leakage CRAM.  It is safer than triple-oxide, and yields leakage power
>> reductions that are quite similar.  We also judiciously apply
>> non-minimum length transistors.  Configuration RAM is a solved problem
>> since there is no performance requirement, we can use both these
>> techniques to greatly reduce sub-threshold leakage.
>>
>> The Stratix II ALM is power-friendly.  (1) It reduces the number of
>> logic levels, so we can use lower leakage routing transistors and
>> maintain speed.  (2) It reduces the amount of routing needed by
>> absorbing more logic into the larger logic functions, so we replace
>> the still-somewhat-leaky routing transistors with low-leakage CRAM
>> cells.
>>
>> My assessment is that Virtex 4 is primarily trying to get power
>> reductions through process techniques, while most of the semiconductor
>> industry has concluded this is not sufficient -- you also need to get
>> gains at the architecture level.
>>
>> Dave Greenfield
>> Sr. Director of Product Marketing  High Density FPGAs
>> Altera Corporation

Article: 73408
Subject: Re: Stratix II vs. Virtex 4 - power
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 21 Sep 2004 16:13:35 GMT
Links: << >>  << T >>  << A >>
Thanks for the dissertation.  I'm afraid I miss your point, though.

You've done a great job analyzing the tradeoffs from your view.  As
engineers, I'm sure we can all appreciate that different tradeoffs are
"better" to different people from direct experience, knowledge, and
expectations (such as the troubles the industry had bringing up the low-K
dielectric).

If parts from any manufacturer run hotter and cost more, the market will
gravitate away from those devices.  If there are cool, fast, cheap,
feature-rich devices, we won't give a Vt whether there are extra process
steps or yield issues that could have produced a "better" part if another
approach were taken.

Particularly troublesome to me is the conclusion that brand-X apparently has
their head up their triple oxide because non-FPGA vendors are implementing
their application-specific hardware on other processes.  I don't SEE the
connection.

I love to see input from all vendors, but I see more competitor negatives
than company positives here.  Lets find out how good our new parts are, not
how bad their chips are.  Maybe we're temporarily stuck in the political
mindset here in the US.


"Dave Greenfield" <davidg@altera.com> wrote in message
news:5c156a0b.0409202043.6124369d@posting.google.com...
> Responding to comments on 90-nm power . . .
>
> Claims here are challenging to understand. It appears that Xilinx
> suggest power goes down by 50% at the same time performance doubles,
> due mainly to a triple oxide process (benefit to leakage power) and
> embedding hard IP (benefit to dynamic power). Let's take a look at
> these claims.
>
> Leakage and triple oxide: Xilinx claims triple oxide is used in CRAM
> to reduce leakage current by 50%. In Stratix II, CRAM accounts for 5%
> of total leakage. Does this imply CRAM leakage in Virtex devices had
> been 50% of the chip's total leakage? Current collateral also glosses
> over the tradeoffs of triple oxide, which the rest of the industry
> (including the likes of Intel, TI, IBM, etc.) have analyzed and have
> deemed too risky and too costly at 90nm for the small benefit
> provided. Triple oxide adds die size (larger transistors). It also
> requires ~4 more wafer processing steps. Both of these aspects
> increase the wafer cost. Both of these factors also reduce yield.
> Because there are now not two, but three different oxides it takes
> longer to tighten up the process and thus deliver sustainable, regular
> yields (i.e. guaranteed delivery). Finally, rapid yield enhancement
> requires driving wafer volume, but the limited use of triple oxide at
> either UMC or some other potential foundry highlights that Virtex 4
> may be stuck driving the triple oxide yield enhancement alone.
>
> Dynamic power and the benefits of embedding more hard IP: Xilinx
> suggests dynamic power goes down by a factor of 7x by embedding hard
> IP. The Virtex 4 documentation suggests the new multipliers run up to
> 500 MHz and consume only 57 uW/MHz. In the SX55 device (with 512
> multipliers), that is 15 W of dynamic power just for DSP. Dynamic
> power for the core, RAMs, and I/O, and then leakage are on top of
> this. I'll assume the 7x factor likely doesn't apply here. Low-k helps
> reduce dynamic power by about 10% and gives a boost to performance of
> ~ 10% (part of Altera's power reduction arsenal). It doesn't look like
> Virtex 4 will get this low-K benefit.
>
> There are other process techniques besides triple oxide to reduce
> leakage power.  For instance, Altera implements different Vt's using
> different implants to reduce leakage power.  This is how we get a low
> leakage CRAM.  It is safer than triple-oxide, and yields leakage power
> reductions that are quite similar.  We also judiciously apply
> non-minimum length transistors.  Configuration RAM is a solved problem
> since there is no performance requirement, we can use both these
> techniques to greatly reduce sub-threshold leakage.
>
> The Stratix II ALM is power-friendly.  (1) It reduces the number of
> logic levels, so we can use lower leakage routing transistors and
> maintain speed.  (2) It reduces the amount of routing needed by
> absorbing more logic into the larger logic functions, so we replace
> the still-somewhat-leaky routing transistors with low-leakage CRAM
> cells.
>
> My assessment is that Virtex 4 is primarily trying to get power
> reductions through process techniques, while most of the semiconductor
> industry has concluded this is not sufficient -- you also need to get
> gains at the architecture level.
>
> Dave Greenfield
> Sr. Director of Product Marketing - High Density FPGAs
> Altera Corporation



Article: 73409
Subject: Re: Stratix II vs. Virtex 4 - availability & fab partnership
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 21 Sep 2004 16:32:05 GMT
Links: << >>  << T >>  << A >>
"Dave Greenfield" <davidg@altera.com> wrote in message
news:5c156a0b.0409202028.232c526f@posting.google.com...

[ snip ]

> I would strongly prefer to leave this site to the technologists.
> Altera will continue to respond though with marketing oriented
> postings when the facts are not properly presented or when marketing
> questions arise.
>
> Dave Greenfield
> Sr. Director of Product Marketing - High Density FPGAs
> Altera Corporation

After reading the third post on this newsgroup, I realize the issues
involved.  You're  SENIOR marketing "professional" - a director? - who
should know that ENGINEERS - the primary customers - don't respond well to
marketing CRAP even if it comes from Xilinx.  This newsgroup hasn't been
poisoned by continuous marketing blather.  The professions who *do* deliver
information on this newsgroup - Altera and Xilinx both noted - usually keep
the marketing to a minimum though sometimes the company line gets to them so
strong that something slips.

The cost/performance advantages that the Altera devices can provide (versus
the cost/performance advantages that the Xilinx devices deliver) are turning
my perceptions back toward my Altera roots.  You are doing a SEVERE
DISSERVICE to the local rep and FAE who are trying to win back my business
by being a sincere marketing ass (in keeping with the republican/democrat
mindset).

Please produce whitepapers on the Altera website and highlight those papers
on the Altera home page if you hope to keep the respect of anyone sitting on
the fence.




Article: 73410
Subject: Mr. Greenfield, spare us the propaganda !
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 21 Sep 2004 09:41:15 -0700
Links: << >>  << T >>  << A >>
Yesterday, Altera rolled out its Sr. Marketing Attack Dog to poison this
newsgroup with his marketing messages.

That is something Austin, Steve and I have successfully fought off for many
years. Xilinx also has its Marketing Rottweilers, but we managed o convince
them that this newsgroup (and Xilinx) is better off without their marketing
messages. We have been fairly successful in keeping this newsgroup technical
and helpful. (Well, Austin sometimes stepped over the line, but he is
forgiven sunce he is so technically astute, and otherwise so helpful.)

You readers have to decide: If you welcome this style of marketing in this
newsgroup, then count me out, and I hang my shingle elsewhere. I will not
share space with such marketing filth, and I will not stoop so low to write
a rebuttal. Until Nov 2, this country has already one kind of poison warfare
too many, we do not need another one in this ng.

For many years, I have teased Altera about their absence from this ng, and
later I have welcomed Paul Laventis for his positive contributions. But I
will have nothing in common with Dave Greenfield.

Peter Alfke, Xilinx Applications

> 


Article: 73411
Subject: Understanding output width in signed multipliers
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 21 Sep 2004 16:44:42 +0000 (UTC)
Links: << >>  << T >>  << A >>
using Xilinx DDS and MULTIPLIER cores, I simulated a system with scalable
output. However after the scaler I notice a loss of amplitude of a factor
two, even when the output scaler was at maximum positive value (0111..) or
minimum negative value (1000..).

Thinking hard, I see that only one case ( 1000... * 1000..) delivers a
result with both the top bits different. So if I clip the value range for
the scale factor at the low end to exclude 1000..., the second top bit will
never be different than the top bit and for an M bit * N bit multiplication
using only (M+N-1) bits of the result will not drop any information.

Is that right?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 73412
Subject: Re: Mr. Greenfield, spare us the propaganda !
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 21 Sep 2004 17:09:22 GMT
Links: << >>  << T >>  << A >>
The sad thing is that it may not be "Altera" that rolled out this extreme
annoyance.  It may have been the one man.

I want to keep this newsgroup technical and keep seeing the contributions
from folks like you, Peter, your compatriot Austin, and your competitor
Paul.

Thanks for sticking with us.


"Peter Alfke" <peter@xilinx.com> wrote in message
news:BD75A7BA.8B02%peter@xilinx.com...
> Yesterday, Altera rolled out its Sr. Marketing Attack Dog to poison this
> newsgroup with his marketing messages.
>
> That is something Austin, Steve and I have successfully fought off for
many
> years. Xilinx also has its Marketing Rottweilers, but we managed o
convince
> them that this newsgroup (and Xilinx) is better off without their
marketing
> messages. We have been fairly successful in keeping this newsgroup
technical
> and helpful. (Well, Austin sometimes stepped over the line, but he is
> forgiven sunce he is so technically astute, and otherwise so helpful.)
>
> You readers have to decide: If you welcome this style of marketing in this
> newsgroup, then count me out, and I hang my shingle elsewhere. I will not
> share space with such marketing filth, and I will not stoop so low to
write
> a rebuttal. Until Nov 2, this country has already one kind of poison
warfare
> too many, we do not need another one in this ng.
>
> For many years, I have teased Altera about their absence from this ng, and
> later I have welcomed Paul Laventis for his positive contributions. But I
> will have nothing in common with Dave Greenfield.
>
> Peter Alfke, Xilinx Applications
>
> >
>



Article: 73413
Subject: Re: Understanding output width in signed multipliers
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Tue, 21 Sep 2004 17:32:01 GMT
Links: << >>  << T >>  << A >>
On Tue, 21 Sep 2004 16:44:42 +0000 (UTC), Uwe Bonnes
<bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

>using Xilinx DDS and MULTIPLIER cores, I simulated a system with scalable
>output. However after the scaler I notice a loss of amplitude of a factor
>two, even when the output scaler was at maximum positive value (0111..) or
>minimum negative value (1000..).
>
>Thinking hard, I see that only one case ( 1000... * 1000..) delivers a
>result with both the top bits different. So if I clip the value range for
>the scale factor at the low end to exclude 1000..., the second top bit will
>never be different than the top bit and for an M bit * N bit multiplication
>using only (M+N-1) bits of the result will not drop any information.
>
>Is that right?

Yes.

In a two's-complement multiplication with inputs S+n and S+m, where S
represents a sign bit and n, m represent the number of remaining bits,
the product will have dimensions 2S+n+m in all cases except
10...0*10...0 (i.e., max neg times max neg).  If you can avoid this
case, you can throw away the redundant-sign-bit MSB.

How to avoid it?  You can, as suggested, use a clipper to limit one of
the inputs to a negative value of 10...01.  Or if, as is often the
case, one of the inputs comes from a coefficient table, you can
select/scale your coefficients to avoid the max. negative number.

Obligatory clarification for those who care: In casual conversation
(i.e., at parties, coronations, parole hearings) we often refer to the
MSB of a two's-comp number as the sign bit.  It's more accurate to
call it a magnitude bit with a negative weight.  For example, the bits
in a 4-bit, two's-comp number have weights (from MSB to LSB) of -8, 4,
2, and 1.  Looking at two's-comp this way removes a lot of the mystery
from two's-comp arithmetic.

Bob Perlman
Cambrian Design Works

Article: 73414
Subject: Re: Mr. Greenfield, spare us the propaganda !
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 21 Sep 2004 10:36:49 -0700
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Yesterday, Altera rolled out its Sr. Marketing Attack Dog to 
 > poison this newsgroup with his marketing messages.

I had to actually go read one of his messages to know how
to answer this.   Being an unmoderated newsgroup, one has to
be selective in what to read.  I always specifically read your
posts, but many others I skim, maybe reading a few words.

I do hope you will stay, and that Altera will learn the right
and wrong way to make customers.   I do believe that many of
the detail given are better stated on a web site, possibly
referenced in the newsgroup.

All newsgroups have a fair amount of noise, and just like in
analog circuits it is something one learns to live with.
Some other groups are much worse in noise, though maybe not
in propaganda.

Thanks for all the good advice over the years,

-- glen


Article: 73415
Subject: Re: Understanding output width in signed multipliers
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 21 Sep 2004 17:41:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
Bob Perlman <bobsrefusebin@hotmail.com> wrote:
: Obligatory clarification for those who care: In casual conversation
: (i.e., at parties, coronations, parole hearings) we often refer to the
: MSB of a two's-comp number as the sign bit.  It's more accurate to
: call it a magnitude bit with a negative weight.  For example, the bits
: in a 4-bit, two's-comp number have weights (from MSB to LSB) of -8, 4,
: 2, and 1.  Looking at two's-comp this way removes a lot of the mystery
: from two's-comp arithmetic.

Nice explanation! Thanks
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 73416
Subject: Re: Understanding output width in signed multipliers
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 21 Sep 2004 10:46:57 -0700
Links: << >>  << T >>  << A >>
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
news:1po0l0lp9d7ujdk4gha1np9oqrog3a8nh2@4ax.com...
> Obligatory clarification for those who care: In casual conversation
> (i.e., at parties, coronations, parole hearings) we often refer to the
> MSB of a two's-comp number as the sign bit.  It's more accurate to
> call it a magnitude bit with a negative weight.  For example, the bits
> in a 4-bit, two's-comp number have weights (from MSB to LSB) of -8, 4,
> 2, and 1.  Looking at two's-comp this way removes a lot of the mystery
> from two's-comp arithmetic.
>
> Bob Perlman
> Cambrian Design Works
Absolutely, Bob. Once my parole officer explained this to me, designing
distributed arithmetic multipliers became a walk in the park!
Cheers, Syms.



Article: 73417
Subject: Re: Stratix II vs. Virtex 4 - availability & fab partnership
From: seannstifler69@hotmail.com (Stifler)
Date: 21 Sep 2004 10:50:23 -0700
Links: << >>  << T >>  << A >>
Obviously V4 has you on the defensive big time! Three long winded
posts in one day. Nice to see. It's back to the days of Virtex II vs.
Apex II. I'm sure you will enjoy it this time as much as you did back
then.

How hard is it to tape out a product family that has no new innovation
from the previous family? Stratix II is simply a copy and paste from
Stratix. Except for the ALM which is still only a partial copy of the
Xilinx CLB. Only a partial copy because you still don't have
distributed RAM or SRL 16 capability. Both very useful and commonly
used features. If your new ALM is so gosh darn awesome, why didn't you
put it into Cyclone II?

Spartan 3 yield issues are solved and Spartan 3 is simply dominating
out there. That's the truth. Now Virtex 4 is going to dominate as
well. It has tons of new innovation poured into it.

1 Gbps serdes on EVERY user I/O
78 ps delay adjust on EVERY user I/O
up to 17 I/O banks
EVERY I/O standard on EVERY user I/O
XCITE on chip termination (both serial and parallel)
.6 to 11 Gbps Rocket I/O
Built in FIFO logic
Built in 10/100/1000 EMAC
Power PC

My fingers are tired of typing now but the list goes on and on.



davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0409202028.232c526f@posting.google.com>...
> Responding to comments on device availability and fab partnership . .
> 
> Stratix II Availability:
> Altera has a track record of shipping devices on schedule.  We realize
> the importance of delivering products on schedule to minimize our
> customers' risk to deliver their end products.  Altera has worked with
> TSMC, worldwide foundry leader, on 90nm process technology since 2001
> and taped out >10 test chips prior to Stratix II.  As a result, we
> were able to ship our first 90nm Stratix II device, the EP2S60, 6
> weeks ahead of schedule. Stratix II development boards are available
> today. 4 additional Stratix II devices are on schedule to roll out
> before the end of the year and the final Stratix II device is on track
> for a Q1-05 introduction. And Stratix II devices are on boards at over
> 60 customers.
>  
> 90-nm Fab Partnership
> A key component of any architectural selection decision involves
> probability of success in rolling out the devices. I agree with the
> general assertion made by my colleague that past success does
> influence this probability. Past success is based on picking the right
> fab partner, investing heavily with that partner, and staying on
> primary process nodes with mainstream processes. Argument was made
> that success on a proven 90 nm partner UMC (with Spartan 3) explains
> why Virtex 4 is low-risk. The fact that Xilinx's technical
> spokesperson has repeatedly highlighted that all of Spartan-3's
> availability woes are "demand related" and not "supply related" is
> also relevant here.
> 
> Altera will continue to invest all process related resources with a
> single partner, TSMC. This partner continues to demonstrate process
> excellence at every leading node. By investing with a single fab
> partner rather than diluting investment across multiple partners,
> Altera will continue to stay ahead of the process curve.
> 
> Altera will stick with mainstream processes and release product on
> them when they are ready for mainstream production. All 90-nm products
> will include low-K; now that low-K is mainstream and provides
> significant upside in terms of power and performance, it is clearly an
> advantageous feature. Triple oxide deviates from standard processing
> which seems ill-advised.
> 
> Spartan-3 delivery problems are not a demand issue. Spartan 3 unit
> shipments are below Spartan 2 unit shipments (I base this on publicly
> highlighted numbers) - perhaps Xilinx could point out the specifics
> here. And Spartan 3 unit shipments are ~ 1/4th Cyclone unit shipments
> (both parts rolled out at the same time). Clearly high-volume families
> are architected to expand the FPGA market; claiming "best rollout
> ever" or "demand problem" just doesn't line up with the facts.
> 
> And even if Spartan-3 90-nm issues were suddenly solved, this UMC
> "success" would only be relevant if Virtex 4 used the exact same fab
> process and fab partner for production. Current rumors in the trade
> press highlight that Xilinx is evaluating other sources for their
> 90-nm products (no doubt based on the tremendous success with the
> Spartan-3 rollout). I look for Xilinx to comment on which fab will be
> used for producing Virtex 4 parts.
> 
> I would strongly prefer to leave this site to the technologists.
> Altera will continue to respond though with marketing oriented
> postings when the facts are not properly presented or when marketing
> questions arise.
> 
> Dave Greenfield
> Sr. Director of Product Marketing ? High Density FPGAs
> Altera Corporation

Article: 73418
Subject: Re: Altera Max II
From: Luc <lb.edc@pandora.be>
Date: Tue, 21 Sep 2004 17:55:52 GMT
Links: << >>  << T >>  << A >>
Paul,

March is also beginning of the year right? Are all package at the same
time available?

Regards,

Luc

On Mon, 20 Sep 2004 23:24:48 GMT, "Paul Leventis \(at home\)"
<paulleventis-news@yahoo.ca> wrote:

>Hi,
>
>> I wanted to know if Altera Max II was shipping. Altera's website says
>> it is shipping but do not know if the EPM570 is shipping.
>>
>> Any news about it?
>
>All is going well on the engineering front.  The EPM1270 is sampling now,
>and the remaining members (including the EPM570) are scheduled to begin
>sampling by the begining of 2005.  If more precise dates are required,
>please contact your Altera rep directly.
>
>Regards,
>
>Paul Leventis
>Altera Corp.
>


Article: 73419
Subject: Re: Mr. Greenfield, spare us the propaganda !
From: Luc <lb.edc@pandora.be>
Date: Tue, 21 Sep 2004 18:11:28 GMT
Links: << >>  << T >>  << A >>
Get rid of the spammer! Pls leave this ng to the technician and his
daily issues.
If Altera has to emphasise how bad the competition is, is perhaps one
way to disguise their own shortcomings.
And that will be the last comment to this discussion.

Luc

On Tue, 21 Sep 2004 10:36:49 -0700, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

>
>
>Peter Alfke wrote:
>
>> Yesterday, Altera rolled out its Sr. Marketing Attack Dog to 
> > poison this newsgroup with his marketing messages.
>
>I had to actually go read one of his messages to know how
>to answer this.   Being an unmoderated newsgroup, one has to
>be selective in what to read.  I always specifically read your
>posts, but many others I skim, maybe reading a few words.
>
>I do hope you will stay, and that Altera will learn the right
>and wrong way to make customers.   I do believe that many of
>the detail given are better stated on a web site, possibly
>referenced in the newsgroup.
>
>All newsgroups have a fair amount of noise, and just like in
>analog circuits it is something one learns to live with.
>Some other groups are much worse in noise, though maybe not
>in propaganda.
>
>Thanks for all the good advice over the years,
>
>-- glen


Article: 73420
Subject: Microblaze:ISE-EDK
From: madhurap@gmail.com (Madhura)
Date: 21 Sep 2004 11:19:20 -0700
Links: << >>  << T >>  << A >>
Hi, 

In my ISE project I have a microblaze processor. I can synthesise it,
but get error when I implement it. The error is "You havemore than one
instance of EDK module. This will not implement correctly."

I am not sure how to fix this. Any suggestion will be helpful. 

Thanks, 
Madhura

Article: 73421
Subject: From whence the MAC on an Altera NIOS devel kit board?
From: hpa@terminus.zytor.com (H. Peter Anvin)
Date: Tue, 21 Sep 2004 18:26:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi all,

I just noticed yesterday that according to the schematic there is no
configuration EEPROM for the NIC on the Altera Nios development kit
(Cyclone edition.)  Yet my board has a MAC which looks relatively
random (00:07:ed:0b:06:81).  00:07:ed is a prefix assigned to Altera.

So... where is this number stored or derived from, if there is no
EEPROM?  I'd like my own design to be compatible with the backup image
on the board, preferrably across multiple boards.

      -hpa

Article: 73422
Subject: Re: Twister + Lancelot
From: hpa@terminus.zytor.com (H. Peter Anvin)
Date: Tue, 21 Sep 2004 18:33:46 +0000 (UTC)
Links: << >>  << T >>  << A >>
Followup to:  <cic2p4$gct$1@news.netpower.no>
By author:    "David Brown" <david@no.westcontrol.spam.com>
In newsgroup: comp.arch.fpga
> 
> I've got a Lancelot connected to my Nios (Cyclone) development kit board.
> It works fine, although I ended up writing my own vga firmware which is a
> lot nicer (IMHO, of course :-) than the original demo code that came with
> the board (my code is vaguely based on newer Nios II application notes and
> examples).  The hardware is not worth copying either, since the video dac on
> the card is now considered obselete by TI.  However, the board does exactly
> what it says on the tin - it is an example card with example code to get you
> started, and worked fine for me in that sense.
> 
> Somebody started a mailing list for the Lancelot, but apart from a few
> initial posts, it's been dead quiet.  I can't even remember its address
> offhand, although I'm sure a google groups search would reveal it.
> 

http://www.zytor.com/mailman/listinfo/lancelot

Please join and liven up the place :)

	-hpa




Article: 73423
Subject: Re: question about types in VHDL
From: "kofeyok" <lomtik@gmail.com>
Date: Tue, 21 Sep 2004 14:34:32 -0400
Links: << >>  << T >>  << A >>
Thanks for the reply rickman.

That makes sence now.
I see that passing of values between modules is done using slv.. but you
can can convert (not cast) inside of each module. The signed port gives
non-synthesizable code. At least my simulator refuses to simulate.

Thanks


Article: 73424
Subject: Re: Mr. Greenfield, spare us the propaganda !
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 21 Sep 2004 11:38:31 -0700
Links: << >>  << T >>  << A >>

Luc wrote:

> Get rid of the spammer! Pls leave this ng to the technician and his
> daily issues.

Figure out how to get rid of spammers, and the whole world will
love you.  I get hundreds of spam e-mails a day, mostly real junk
although one today wants to sell me a Virtex 4 kit.

In this case we know where he works, and probably where he lives,
so we could do something about it.  (Legal, that is.)


-- glen




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