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Messages from 79100

Article: 79100
Subject: Re: 2 microblaze access same BRAM ?
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Mon, 14 Feb 2005 18:04:50 +0100
Links: << >>  << T >>  << A >>
Yes, Just have multiple bram blocks and bram controllers.

Göran

Elinore wrote:
> hi
> 
> It is good be feasible. I found that in XPS wizard we can set maximaly
> 64 KB for BRAM. Subsequent question is about the size. Can we make it
> bigger, for example 128KB or 256 KB ? 
> 
> Thankyou again
> 

Article: 79101
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: jeremy.webb@ieee.org
Date: 14 Feb 2005 09:06:31 -0800
Links: << >>  << T >>  << A >>
Hi.

Here's some code that I used to display digits/letters on the 7-seg
displays:

module set_7seg_displays (
	// *** Inputs ***
	input	wire		clk_50mhz,      // System clock. (50 MHz)
        input   wire            btn,    // Button 0. (Active High).

        // *** Outputs ***
        output	reg	[3:0]	digit,// 7-seg display enables. (Active Low).
        output	reg	[7:0]	seg  // 7-Segment display. (Active Low).

		);

// 7-Segment display. seg[7:0]={ca, cb, cc, cd, ce, cf, cg, dp}.
wire            rst_n;          // System Reset. (Active Low).
reg     [25:0]  slow_cnt_h;
reg             slow_clk_2h;
reg             slow_clk_h;
reg     [1:0]   cd;

// Assign reset to a button push.
assign rst_n = ~btn;

// *** Create a 2x 7-Seg display clock ***
always @(posedge clk_50mhz or negedge rst_n)
begin : CLK_GEN_2x_7SEG
        if (!rst_n)
        begin
                slow_clk_2h <= 1'b0;
                slow_cnt_h <= 26'b0;
        end
        else
        begin
                if (slow_cnt_h == 26'h001_86A0)
                begin
                        slow_clk_2h <= 1'b1;
                        slow_cnt_h <= 26'h0;
                end
                else
                begin
                        slow_clk_2h <= 1'b0;
                        slow_cnt_h <= slow_cnt_h + 1'b1;
                end
        end
end

// *** Create 1x 7-Seg Display clock ***
always @(posedge slow_clk_2h or negedge rst_n)
begin : CLK_GEN_1x_7SEG
        if (!rst_n)
                slow_clk_h <= 1'b0;
        else
                slow_clk_h <= ~slow_clk_h;
end

// *** Drive the 7-segment display ***
always @(posedge slow_clk_h or negedge rst_n)
begin : SET_7SEGDISPLAY
        if (!rst_n)
        begin
            seg <= 8'hFF;
	    digit <= 4'hF;
            cd <= 2'b00;
        end
        else
        begin
              // Cycle through all 4 7-segment displays.
              // Rolls over from 3 to 0. cnt sequence: 0,1,2,3,0,1,2,3
	        cd[1:0] <= cd[1:0] + 1'b1 ;
        	case (cd[1:0])
                    2'b00 : begin
                             seg <= 8'b0001_0001; // Letter: A (0x11)
                             digit <= 4'b0111;
                            end
                    2'b01 : begin
                             seg <= 8'b0100_1001; // Letter: S (0x49)
                             digit <= 4'b1011;
                            end
                    2'b10 : begin
                             seg <= 8'b0001_0001; // Letter: A (0x11)
                             digit <= 4'b1101;
                            end
                    2'b11 : begin
                             seg <= 8'b0011_0001; // Letter: P (0x31)
                             digit <= 4'b1110;
                            end
                  default : begin
                             seg <= 8'b0000_0010; // Number: 0 (0x02)
                             digit <= 4'b0111;
                            end
                endcase
        end
end

NOTE:  This code keeps the digits/letters continuously lit.

Hope this helps,

Jeremy

fpgawizz wrote:
> I am trying to understand the working of the multiplexed seven seg.
> displays on the xilinx spartan 3 board.the manual does not give me
> detailed info. I am trying to write a simple program where I switch a
> switch to the on position and it should display "0012" on the
displays.
> Any suggestions please?
> 
> thanks


Article: 79102
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: Tommy Thorn <foobar@nowhere.void>
Date: Mon, 14 Feb 2005 17:23:18 GMT
Links: << >>  << T >>  << A >>
Hi Jeremy,

since this _is_ tutorial stuff, I must point out that clocking from 
derived logic is a very very bad idea.  I'm sure you must have ignored 
tools warnings to get this to compile.

FPGAs have dedicated paths for the clocking lines separate from logic .. 
and the twine shall never meet.  There are so many reasons why this is a 
bad idea, but basically the tools have to contrain timing quite 
intensely to get this working at all and you might just have been lucky.

The correct way to derive a new clock is using a DLL, DCM, PLL, what 
have you.  In this simple case however, there's another simple fix you 
could use: Just calculate which cycle of the fast clock is safe to use.

...
wire [26:0] slow_cnt;
wire slow_ce = slow_cnt == 2*'h001_86A0;
always @(posedge clk_50MHz) begin
   slow_cnt <= slow_ce ? 0 : slow_cnt+1;
   if (slow_ce) begin
     cd <= cd + 1;
     case (cd)
     'b00 : begin
       seg <= 'b0001_0001; // Letter: A (0x11)
etc..

Tommy


jeremy.webb@ieee.org wrote:
> Hi.
> 
> Here's some code that I used to display digits/letters on the 7-seg
> displays:
> 
> module set_7seg_displays (
> 	// *** Inputs ***
> 	input	wire		clk_50mhz,      // System clock. (50 MHz)
>         input   wire            btn,    // Button 0. (Active High).
> 
>         // *** Outputs ***
>         output	reg	[3:0]	digit,// 7-seg display enables. (Active Low).
>         output	reg	[7:0]	seg  // 7-Segment display. (Active Low).
> 
> 		);
> 
> // 7-Segment display. seg[7:0]={ca, cb, cc, cd, ce, cf, cg, dp}.
> wire            rst_n;          // System Reset. (Active Low).
> reg     [25:0]  slow_cnt_h;
> reg             slow_clk_2h;
> reg             slow_clk_h;
> reg     [1:0]   cd;
> 
> // Assign reset to a button push.
> assign rst_n = ~btn;
> 
> // *** Create a 2x 7-Seg display clock ***
> always @(posedge clk_50mhz or negedge rst_n)
> begin : CLK_GEN_2x_7SEG
>         if (!rst_n)
>         begin
>                 slow_clk_2h <= 1'b0;
>                 slow_cnt_h <= 26'b0;
>         end
>         else
>         begin
>                 if (slow_cnt_h == 26'h001_86A0)
>                 begin
>                         slow_clk_2h <= 1'b1;
>                         slow_cnt_h <= 26'h0;
>                 end
>                 else
>                 begin
>                         slow_clk_2h <= 1'b0;
>                         slow_cnt_h <= slow_cnt_h + 1'b1;
>                 end
>         end
> end
> 
> // *** Create 1x 7-Seg Display clock ***
> always @(posedge slow_clk_2h or negedge rst_n)
> begin : CLK_GEN_1x_7SEG
>         if (!rst_n)
>                 slow_clk_h <= 1'b0;
>         else
>                 slow_clk_h <= ~slow_clk_h;
> end
> 
> // *** Drive the 7-segment display ***
> always @(posedge slow_clk_h or negedge rst_n)
> begin : SET_7SEGDISPLAY
>         if (!rst_n)
>         begin
>             seg <= 8'hFF;
> 	    digit <= 4'hF;
>             cd <= 2'b00;
>         end
>         else
>         begin
>               // Cycle through all 4 7-segment displays.
>               // Rolls over from 3 to 0. cnt sequence: 0,1,2,3,0,1,2,3
> 	        cd[1:0] <= cd[1:0] + 1'b1 ;
>         	case (cd[1:0])
>                     2'b00 : begin
>                              seg <= 8'b0001_0001; // Letter: A (0x11)
>                              digit <= 4'b0111;
>                             end
>                     2'b01 : begin
>                              seg <= 8'b0100_1001; // Letter: S (0x49)
>                              digit <= 4'b1011;
>                             end
>                     2'b10 : begin
>                              seg <= 8'b0001_0001; // Letter: A (0x11)
>                              digit <= 4'b1101;
>                             end
>                     2'b11 : begin
>                              seg <= 8'b0011_0001; // Letter: P (0x31)
>                              digit <= 4'b1110;
>                             end
>                   default : begin
>                              seg <= 8'b0000_0010; // Number: 0 (0x02)
>                              digit <= 4'b0111;
>                             end
>                 endcase
>         end
> end
> 
> NOTE:  This code keeps the digits/letters continuously lit.
> 
> Hope this helps,
> 
> Jeremy
> 
> fpgawizz wrote:
> 
>>I am trying to understand the working of the multiplexed seven seg.
>>displays on the xilinx spartan 3 board.the manual does not give me
>>detailed info. I am trying to write a simple program where I switch a
>>switch to the on position and it should display "0012" on the
> 
> displays.
> 
>>Any suggestions please?
>>
>>thanks
> 
> 

Article: 79103
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: nospam <nospam@nospam.invalid>
Date: Mon, 14 Feb 2005 17:46:23 +0000
Links: << >>  << T >>  << A >>
"fpgawizz" <bhaskarstays@yahoo.com> wrote:

>I am trying to understand the working of the multiplexed seven seg.
>displays on the xilinx spartan 3 board.

I think everyone who gets the starter kit must end up writing their own
driver for the 7 segment display.

Shame there isn't a bit more simple 'IP' provided with the kit.

Apart from the Xilinx examples I didn't find much in the way of resources
for the starter kit on the web. 

Would there be interest in a Yahoo group or something to share Spartan 3
starter kit related files? 




Article: 79104
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: Tommy Thorn <foobar@nowhere.void>
Date: Mon, 14 Feb 2005 17:54:08 GMT
Links: << >>  << T >>  << A >>
Grief, pre-coffee post.  Should know better.  Slight better code:

reg [26:0] slow_cnt;
always @(posedge clk_50MHz)
   if (slow_cnt)
     slow_cnt <= slow_cnt - 1;
   else begin // 50MHz / 20kHz = 2.5 kHz
     slow_cnt <= 200000;
     cd <= cd + 1;
     case (cd)
     'b00 : begin
       seg <= 'b0001_0001; // Letter: A (0x11)
etc..

Article: 79105
Subject: clock division / multiplication in xilinx cpld
From: matthewlawrencecohen@yahoo.com
Date: 14 Feb 2005 09:57:50 -0800
Links: << >>  << T >>  << A >>
I have a design using a xilinx xc9500xl cpld.  This project is a patch
to an existing project and so not all the signals I need are readily
available.  I have clk/2 and clk*2, but I need clk.  The desired
waveforms are:

clk*2: -.-.-.-.-.-.-.-.
clk:   --..--..--..--..
clk/2: ----....----....

My original, not-well-thought-out plan was to simply take clk*2 and
divide the frequency down simply by toggling an internal signal on
every rising edge of clk*2, and using that as clk.  Easy enough, but
unfortunately half the time this clk ends up out of phase with the
original clk.

clk*2: -.-.-.-.-.-.-.-.
clk:   ..--..--..--..--
clk/2: ----....----....

My next thought was that since I have clk/2 available, I could sync off
of that on the first transition, so that the first rising edge of clk
would occur off of clk/2, which would set an internal "sync" bit, which
would switch a MUX so that clk*2 controller clk as before, but now with
the proper phase.  This relied on having sync and clk internally
initialize to 0.  Xilinx claims this is possible, and simulation works,
but the device is still out of phase half the time.  Any ideas?

Matt


Article: 79106
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: "fpgawizz" <bhaskarstays@yahoo.com>
Date: Mon, 14 Feb 2005 13:28:00 -0500
Links: << >>  << T >>  << A >>
Yes. I would be interested in a usergroup for xilinx spartan 3 kit users.


Article: 79107
Subject: Re: clock division / multiplication in xilinx cpld
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 14 Feb 2005 19:33:01 +0100
Links: << >>  << T >>  << A >>
<matthewlawrencecohen@yahoo.com> schrieb im Newsbeitrag
news:1108403870.059404.13360@g14g2000cwa.googlegroups.com...

> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
>
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....
>
> My original, not-well-thought-out plan was to simply take clk*2 and
> divide the frequency down simply by toggling an internal signal on
> every rising edge of clk*2, and using that as clk.  Easy enough, but
> unfortunately half the time this clk ends up out of phase with the
> original clk.

;-)) Hehe, common pitfall.

> My next thought was that since I have clk/2 available, I could sync off
> of that on the first transition, so that the first rising edge of clk
> would occur off of clk/2, which would set an internal "sync" bit, which

Right way to go.

> would switch a MUX so that clk*2 controller clk as before, but now with
> the proper phase.  This relied on having sync and clk internally
> initialize to 0.  Xilinx claims this is possible, and simulation works,
> but the device is still out of phase half the time.  Any ideas?

Why does a SYNC bit relies on proper initialization?? Its called SYNC, so it
actually measures the signals and then decides what to do. So you need a
real SYNC (tm).
Tried N'Sync ??

;-))

Serious, you have to sample clk/2 using clk*2, maybe on the other edge to
avoid setup/hold problems. Then this sampled clk/2 can be used as a
synchronous reset for your clock divider (ok, its a simple FlipFlop here)

In VHDL it would look like this

process(clk_x2)
begin
  if rising edge(clk_x2) then
     clk_div_2_int <= clk_div2;                -- sample clk/2
     if clk_div_2_int='1' then
       my_divider <= '0';                            -- synchronous reset
     else
       my_divider <= not my_divider;        -- normal clock division
     end if;
  end if;
end process;

clk <= my_divider;

Regards
Falk




Article: 79108
Subject: Re: clock division / multiplication in xilinx cpld
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 14 Feb 2005 18:36:17 GMT
Links: << >>  << T >>  << A >>
<matthewlawrencecohen@yahoo.com> wrote in message
news:1108403870.059404.13360@g14g2000cwa.googlegroups.com...
> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
>
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....

<snip>

If your timing allows proper sampling of your clk/2 with your clk*2,
register the clk/2 and use the result to determine if you're in phase or
not.

If clkD2^reg_clkD2 (transition just happened) then clk must be 1 (rising
edge just happened)

clk <= ~(clk | (clkD2 ^ reg_clkD2));



Article: 79109
Subject: Weird Mircroblaze programm execution
From: "Philipp" <carlsberg@gmx.at>
Date: Mon, 14 Feb 2005 18:52:39 -0000
Links: << >>  << T >>  << A >>
Hello

I am really a little bit helpless at the moment. I have implemented an own 
IP which performs some special arithmetic instruction (multiplication, 
addition, root, substraktion and so on). I tested each module with thousands 
of testcases so we can be sure that thet are working properly.
Next I added this IP to the microblaze core with the FSL interface. I 
downloaded then the complete design on my ML300 board. I run an algorithm on 
my Microblaze core which calls my instructions 8000 times and at the end of 
the day I got the correct result. So I was sure that this design is 
"perfect". But now I added 400 more instructions for an inversion 
operations, and after 50 instruction something weird is happening:

If I use the following codefragment I get an incorrect result:
....
command(OP_MUL, REG14, REG14, REG17);
command(OP_MUL, REG12, REG13, REG18);
command(OP_MUL, REG13, REG14, REG19);
command(OP_MUL, REG12, REG14, REG20);
command(OP_ADD, REG18, REG17, REG21);
....


But if I insert a print statement within this fragement to read out one of 
my registers then it works:
....
command(OP_MUL, REG14, REG14, REG17);
command(OP_MUL, REG12, REG13, REG18);
command(OP_MUL, REG13, REG14, REG19);
command(OP_MUL, REG12, REG14, REG20);
print("--   Value of REG20 --... \n\r");
command(OP_RD, REG20, 0, 0);

 for (i=0;i<7;i++){
  microblaze_bread_datafsl(data_back_local_link[i],0);
        printf("Value :%u \n\r",data_back_local_link[i]);
 };
command(OP_ADD, REG18, REG17, REG21);
...

This really doesnt make sense! Without the print statement the value of 
REG20 is overwritten by the next instructions. If I insert the print 
statement I get the correct result. So has here anybody an idea whats going 
on? Because I executed 8000 instructions without any problems! This thing 
occured after 50 additional instrucion calls. My command is definied as 
follows:

void command(opcode, op1, op2, op3) {
 int com;
 com = opcode * 16777216 + op1 * 65536 + op2 * 256 + op3;
 microblaze_bwrite_datafsl(com,0);
}

I use EDK 6.2 for design and synthesising my core. Is it perhaps possible 
that the FIFO of my Micrblaze gets full, and ignores some of the 
instructions?  If yes, is there a way to prevent this?

I hope that some of you guys understand my problem and could give me a hint!

Thanks a lot
Philipp


. 



Article: 79110
Subject: Re: second flop in asyn reset distribution
From: "fpgabuilder" <fpgabuilder-news@yahoo.com>
Date: 14 Feb 2005 11:03:39 -0800
Links: << >>  << T >>  << A >>
Here is why I think, second ff will not enter the metastable state -

Assume a simple FF with Master-Slave latches constructed of CMOS Pass
transistor logic.  The CP input is used to gate the pass transistors.
The D input is fed to the first pass transistor, T1.  O/p of T1 is
gated with RESET input and subsequently fed to the second pass
transistor, T2.

Normally(or abnormally) a CMOS gate goes metastable if Voh = Vih =
Vm/2.  The probablity that T2 sees a condition Voh = Vm/2 will only
occur if its input changes with CP.  Since, D input does not change and
IS LOW, the o/p of the RESET & D also does not change, even when RESET
changes.  Hence, the latch o/p will not go metastable.  Therefore, the
slave latch will only hold a stable value at the o/p of the FF.

So, Hal, I think your point about runt pulses makes sense.    If the
ckt happens to enter metastability, then the gain of cmos gates, feed
each other and finally knock the o/p into a stable state which is what
I think you are saying Peter.  

Thanks once again all.


Article: 79111
Subject: opencore under edk 6.3i
From: "Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam>
Date: Mon, 14 Feb 2005 19:03:42 GMT
Links: << >>  << T >>  << A >>
Hi all,

I would like to use some opencore IPCOre in the edk interface like the opb 
one. I would likt to know what should i do to make it listed under the add/ 
core ?

I probably have to modify some file in the the hdl file.

I would like to use wishbone one. I know there is have a wrapper ipcore 
(www.ascic.ws) but i can't make it work.

if someone  have some infos on this i'll apreciated

Jonathan 



Article: 79112
Subject: Re: clock division / multiplication in xilinx cpld
From: Bertram Geiger <badnews_geiger@aon.at>
Date: Mon, 14 Feb 2005 20:11:06 +0100
Links: << >>  << T >>  << A >>
matthewlawrencecohen@yahoo.com wrote:
> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
> 
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....
> 

...

delay clk/2 using clk*2 with a D-FF by one cycle
Then EXOR the original clk/2 and the delayed clk/2
The result should be clk with predictable phase

regards bertram


Article: 79113
Subject: Re: Xilinx BRAM FIFO problems ModelSim Post Place and Route
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 14 Feb 2005 11:13:43 -0800
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:

> You say you don't use unisim which seems to be the xilinx primitive
> library. What are you using 

I use code templates to infer block ram/rom.
My previous posting had an example.

 > and why?

Simulation is simpler and faster and I
can target X, A or other devices.


       -- Mike Treseler

Article: 79114
Subject: Strange clock problem with Synthesized netlist in Quartus
From: "News" <news@redbandsystems.com>
Date: 14 Feb 2005 11:43:24 -0800
Links: << >>  << T >>  << A >>
Hi Folks,

I have a strange problem with the synthesized netlist. I use the
Verilog
module below to generate a clock. At RTL level, it works fine. When I
tried simulating the synthesized netlist, I noticed that both the
rising edge & the falling edge of the clock output "outclk" are red. I
am using Quartus v4.2 & ncsim for the simulations.

Thanks for your help
Arun

module CLKDIV (
    inclk,           //  Input data clock
	divby,           //  Divisor
	outclk,          //  Output Clock
	reset_l);

	output          outclk;
	input   [07:00] divby;

    input           inclk;
	input           reset_l;

// begin
   reg  [07:00] rCount;
   wire isEqual = (rCount == divby);

   always @(posedge inclk or negedge reset_l) begin
	  if (!reset_l) begin
	      rCount <= 8'b1;
	  end else begin
	      rCount <= isEqual ? 8'b1 : (rCount + 8'b1);
	  end
   end

   reg outclk;
   always @(posedge inclk or negedge reset_l) begin
       if (!reset_l) begin
           outclk <= 1'b0;
       end else begin
           outclk <= isEqual;
       end
   end
endmodule


Article: 79115
Subject: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Mon, 14 Feb 2005 11:59:17 -0800
Links: << >>  << T >>  << A >>

Hi,

> Apart from the Xilinx examples I didn't find much in
> the way of resources for the starter kit on the web.

Please check out http://www.engr.sjsu.edu/crabill for a set
of labs/experiments you can try with the Spartan-3 Starter
kit...  I have tried to touch on most of the resources with
the exception of the SRAM.

// opinion_on

This kit is well named, a "starter" kit.  If everything is
simply handed to you, you don't learn anything.  That's why
it makes such a great educational tool.

If a time multiplexed seven-segment display is challenging
enough for someone to make an appeal to this newsgroup, they
should go through the exercise of designing it themselves.
Maybe with a little help...  We are all learners, just at
different places on the path.  I think to include resources
like this with the kit itself (or posted to this newsgroup)
defeats its utility as a learning tool.

// opinion_off

Good luck!
Eric

Article: 79116
Subject: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
From: Yong Zhu <Yong.Zhu@xilinx.com>
Date: Mon, 14 Feb 2005 13:22:54 -0700
Links: << >>  << T >>  << A >>
Hi Sylvain,

To make your custom IP accessible in XPS, you'll need to create PSF 
conformed directory structure and interface files (PAO/MPD/BBD). The 
Create/Import Peripheral Wizard from EDK can help you on this.

Since you already have the netlist (.ngc) and a wrapper HDL, you 
shouldn't have problem to use the wizard's import flow to import your 
mac core. After importing, you can use your custom IPs like any other 
EDK cores bundled in the tool.

Let me know if you have any questions regarding the wizard.

thanks,
yong

Sylvain Munaut wrote:
> Hello,
> 
> I'm trying since yesterday to interconnect the opencore mac to a 
> microblaze design.
> After several problems solved, I'm stuck.
> 
> The "Generate netlist now works fine" but When I try to "Generate 
> bitstream",
> I have three errors from NgdBuild :
> 
> 
> ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 
> 'wb2opb' could
> not be resolved. A Pin name mispelling can cause this, a missing edif or 
> ngc
> file, or the mispelling of a type name. Symbol 'wb2opb' is not supported 
> in target
> 'spartan 3'.
> ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 
> 'opb2wb' could
> not be resolved. A Pin name mispelling can cause this, a missing edif or 
> ngc
> file, or the mispelling of a type name. Symbol 'opb2wb' is not supported 
> in target
> 'spartan 3'.
> ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' 
> with
> type 'eth_top' could not be resolved. A Pin name mispelling can cause 
> this, a
> missing edif or ngc file, or the mispelling of a type name. Symbol 
> 'eth_top' is
> not supported in target 'spartan 3'.
> 
> 
> For the wb_ethermac core, I've created a file that includes the eth_top 
> of the
> ethernet mac core on opencore and present the interface to the outside 
> world.
> I've done this as a ISE project then I synthetized it to have a .ngc 
> file (because
> I have both VHDL & Verilog there) then I created an IP from this netfile 
> and my vhdl top file.
> 
> Any one has a clue on what to do ? Has anyone make this work ? (I'm 
> using ISE/EDK 6.3)
> 
> 
> Thanks,
> 
>     Sylvain


Article: 79117
Subject: Re: opencore under edk 6.3i
From: Yong Zhu <Yong.Zhu@xilinx.com>
Date: Mon, 14 Feb 2005 13:28:27 -0700
Links: << >>  << T >>  << A >>
Hi Jonathan,

Use the Create/Import Peripheral Wizard (import flow) from EDK to import 
your cores. After ipmorting, you should see they're listed under 
Add/Edit Core dialog like any other EDK cores.

thanks,
yong

Jonathan Dumaresq wrote:

> Hi all,
> 
> I would like to use some opencore IPCOre in the edk interface like the opb 
> one. I would likt to know what should i do to make it listed under the add/ 
> core ?
> 
> I probably have to modify some file in the the hdl file.
> 
> I would like to use wishbone one. I know there is have a wrapper ipcore 
> (www.ascic.ws) but i can't make it work.
> 
> if someone  have some infos on this i'll apreciated
> 
> Jonathan 
> 
> 


Article: 79118
Subject: Updated Stratix II Power Specs & Explanation
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: 14 Feb 2005 13:02:58 -0800
Links: << >>  << T >>  << A >>
Hi,

Today we released our updated power specs for Stratix II.  Some
highlights of the updates found in the Stratix II Early Power Estimator
V2.1 tool:

(1) Reduced static power by up to 47%.  We've measured many units from
across the product family, and have the data to tighten the spec
compared to our previous conservative/estimated values.  The amount of
change varies from family member to family member, and is a function of
junction temperature and whether typical or worst-case silicon is
selected.

(2) Static current on the VccPD rail now reflected (it is tiny)

(3) There is no more in-rush Icc current.  The previous current
reflected a result measured on early units from one family member plus
some excessive guard-bands.  The underlying cause was rectified and all
Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush.

(4) We previously reported around 100 mA of static power per used MRAM
in the chip.  This turns out to have been a measurement error and now
there is no added static power.


See
http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html
for details on the updates and where to get the EPE.  Quartus 5.0 will
reflect these updated specs when it is released in Q2.


Paul Leventis
Altera Corp.


Article: 79119
Subject: Re: See the next high-wire act, this time on power consumption
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: 14 Feb 2005 13:21:13 -0800
Links: << >>  << T >>  << A >>
> We have finished our PPT slides and polished the presentation. It
will
> be tutorial and technical in nature, but will also not shy away from
> competitive issues.

Too bad the slides are done given that we've released updated power
specs.  I'm sure you will carefully caveat the comparison
appropriately...

BTW, I sincerely hope you will stop all this nonsense with in-rush
"power".  Your web site seems to trumpet a big advantage here, but
Stratix II does not have any in-rush current (as announced a few weeks
back).  Never mind that in-rush "power" is meaningless -- in chips that
do have an in-rush event, it is just a temporary spike in *current*
draw during power up and in no way relates to thermal dissipation or
energy requirements of the device.  All this spike affects is the
minimum supply size from a transient current perspective.

I personally think it was slimy to take what was a conservative minimum
power supply size spec and convert it into Watts and pretend it was a
power consumption.  But I guess that's marketing...  Anyway, it is moot
given there is no inrush in Stratix II.

Good luck tomorrow.  I'm looking forward to a very healthy debate
afterwards :-)

Paul Leventis
Altera Corp.


Article: 79120
Subject: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
From: "Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam>
Date: Mon, 14 Feb 2005 21:44:41 GMT
Links: << >>  << T >>  << A >>
could you give me what you have done to make it pass the netlist problem ?

here the result i have:

Managing hardware (BBD-specified) netlist files ...

opb2wb (opb2wb_0) - C:\EDK\project\test1\system.mhs:37 - Copying 
(BBD-specified)

netlist files.

ERROR:MDT - opb2wb (opb2wb_0) - C:\EDK\project\test1\system.mhs:37 - BBD

parameter is undefined in the MPD

ERROR:MDT - platgen failed with errors!

make: *** [implementation/opb2wb_0_wrapper.ngc] Error 2

Done.





regards

Jonathan

"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le 
message de news: 420fb7ae$0$22479$ba620e4c@news.skynet.be...

> Hello,
>
> I'm trying since yesterday to interconnect the opencore mac to a 
> microblaze design.
> After several problems solved, I'm stuck.
>
> The "Generate netlist now works fine" but When I try to "Generate 
> bitstream",
> I have three errors from NgdBuild :
>
>
> ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' 
> could
> not be resolved. A Pin name mispelling can cause this, a missing edif or 
> ngc
> file, or the mispelling of a type name. Symbol 'wb2opb' is not supported 
> in target
> 'spartan 3'.
> ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 'opb2wb' 
> could
> not be resolved. A Pin name mispelling can cause this, a missing edif or 
> ngc
> file, or the mispelling of a type name. Symbol 'opb2wb' is not supported 
> in target
> 'spartan 3'.
> ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' 
> with
> type 'eth_top' could not be resolved. A Pin name mispelling can cause 
> this, a
> missing edif or ngc file, or the mispelling of a type name. Symbol 
> 'eth_top' is
> not supported in target 'spartan 3'.
>
>
> For the wb_ethermac core, I've created a file that includes the eth_top of 
> the
> ethernet mac core on opencore and present the interface to the outside 
> world.
> I've done this as a ISE project then I synthetized it to have a .ngc file 
> (because
> I have both VHDL & Verilog there) then I created an IP from this netfile 
> and my vhdl top file.
>
> Any one has a clue on what to do ? Has anyone make this work ? (I'm using 
> ISE/EDK 6.3)
>
>
> Thanks,
>
> Sylvain 



Article: 79121
Subject: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Mon, 14 Feb 2005 22:47:17 +0100
Links: << >>  << T >>  << A >>
Hi

Jonathan Dumaresq wrote:

> I want to do exactly what you do. but i'm stuck to the netlist problem.

Glad to know I'm not alone ;)


> I use the wb2opb from ascic.ws and now i want to use some opencore ip to
> plug to my microblaze. so if you can send to this ng what you have done to
> make it work i'll apreciated

Well, finally I got a bitstream ! But ... it doesn't work as excpected so I'm
not sure that what I've done is good.

So finally I decided to try a smaller problem, just take
Microblaze + UART + opb2wb + opencore_simple_gpio and try to make this work.

Here's what I'm trying right now (writing this msg as I'm doing/testing it ;)
>From ground up :

* First step : Install the opb2wb
 --------------------------------

 - Extract the opb2wb_v1_00_a from the tar.gz and put it into your personnal pcore dir
 - Edit the bbd file and suppress the first column (C_FAMILY) to just leave the first line
   So you should have
 
<cut here>
Files
###########...#####
opb2wb_v1_00_a.edn
<end cut>

 - Edit the mpd file and rename the 'opb_rst' into 'rst' (only the lowercase one.
   leave the OPB_rst untouched ). 
 - Edit the netlist file (.edn) and change the creator program to "none"
   So you have (program "none") instead of (program "xilinx stuff ...")
   The ngcbuild don't like to work with edif netlist created by ngc2edit and tells
   you to use the original ngc instead but we don't have it ...
 

*** At this point, adding a opb2wb to an existing/working design and making all
    wb connections external works (I mean you can produce a bitstream. I don't
    know if the wrapper works or not ... ****


* Second step : Creating a wb_gpio_simple EDK-compatible core
 -------------------------------------------------------------

 - I've used the simple_gpio core as a base to create my own very simple gpio_core
   
... And I'm still at this step and won't finish tonight ;)
I already send this which may help you.




Note that some steps might be unecessary, I just wrote that as a collection of
all the things I made to make it generate a bitstream.

	Sylvain
 

Article: 79122
Subject: Re: Updated Stratix II Power Specs & Explanation
From: austin <austin@xilinx.com>
Date: Mon, 14 Feb 2005 13:49:26 -0800
Links: << >>  << T >>  << A >>
Paul,

I am delighted.

Not only is the static Iccint current > 7.568 amperes at 100C, but the 
device is clearly doing a thermal runaway (in Excel!).

How did you do that?  Does the device melt down just like the 
spreadsheet?  It looks as if the solution is iterative, and it keeps 
trying to converge with the formula for the Iccint being exponetial with 
T, and the T just getting hotter, and hotter ...)

Sure, when the worst case static current is less than the surge, then 
there is no "surge...."

Sure.  So if the worst case static is 6 ameres, what is the 'surge' at 
25C?  Less than 6 amperes, but still there?

Smoke and mirrors, mostly smoke?

You should really check your spreadsheets before posting.

EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 
power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes 
to ~85C.   Even a 1/2 degree more causes the Tj to pop to 100+.

Now, I admit this is a degenerate case, and people will ususally have 
some airflow, and maybe even a heatsink. Still ~ 6 amperes just for 
static current, but at least it won't melt down.

At least V4 won't thermally runaway when you turn it on.

Austin

Paul Leventis wrote:

> Hi,
> 
> Today we released our updated power specs for Stratix II.  Some
> highlights of the updates found in the Stratix II Early Power Estimator
> V2.1 tool:
> 
> (1) Reduced static power by up to 47%.  We've measured many units from
> across the product family, and have the data to tighten the spec
> compared to our previous conservative/estimated values.  The amount of
> change varies from family member to family member, and is a function of
> junction temperature and whether typical or worst-case silicon is
> selected.
> 
> (2) Static current on the VccPD rail now reflected (it is tiny)
> 
> (3) There is no more in-rush Icc current.  The previous current
> reflected a result measured on early units from one family member plus
> some excessive guard-bands.  The underlying cause was rectified and all
> Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush.
> 
> (4) We previously reported around 100 mA of static power per used MRAM
> in the chip.  This turns out to have been a measurement error and now
> there is no added static power.
> 
> 
> See
> http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html
> for details on the updates and where to get the EPE.  Quartus 5.0 will
> reflect these updated specs when it is released in Q2.
> 
> 
> Paul Leventis
> Altera Corp.
> 

Article: 79123
Subject: Re: See the next high-wire act, this time on power consumption
From: austin <austin@xilinx.com>
Date: Mon, 14 Feb 2005 13:56:01 -0800
Links: << >>  << T >>  << A >>
Paul,

In denial, huh?

No surge, just an insignificant little spike?

No power.

Yes, but do you need it to turn on?  If you do, the power vendors just 
love you, as they get to sell bigger power supplies.  You got a surge.

If the spike is an artifact, and it is only current that is consumed if 
available, and if and only if all the current that is required is the 
leakage to turn the device on, then you have no surge.

So, I am willing to grant you fixed it, as it can be fixed (like we did 
back with V2) as it is fixable.

But prove it.  Where is the scope shot?

But, you did not use a third oxide transistor, and the result is the 
huge static leakage with increasing temperature.

Enjoy,

Austin



Paul Leventis wrote:

>>We have finished our PPT slides and polished the presentation. It
> 
> will
> 
>>be tutorial and technical in nature, but will also not shy away from
>>competitive issues.
> 
> 
> Too bad the slides are done given that we've released updated power
> specs.  I'm sure you will carefully caveat the comparison
> appropriately...
> 
> BTW, I sincerely hope you will stop all this nonsense with in-rush
> "power".  Your web site seems to trumpet a big advantage here, but
> Stratix II does not have any in-rush current (as announced a few weeks
> back).  Never mind that in-rush "power" is meaningless -- in chips that
> do have an in-rush event, it is just a temporary spike in *current*
> draw during power up and in no way relates to thermal dissipation or
> energy requirements of the device.  All this spike affects is the
> minimum supply size from a transient current perspective.
> 
> I personally think it was slimy to take what was a conservative minimum
> power supply size spec and convert it into Watts and pretend it was a
> power consumption.  But I guess that's marketing...  Anyway, it is moot
> given there is no inrush in Stratix II.
> 
> Good luck tomorrow.  I'm looking forward to a very healthy debate
> afterwards :-)
> 
> Paul Leventis
> Altera Corp.
> 

Article: 79124
Subject: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
From: "Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam>
Date: Mon, 14 Feb 2005 21:57:04 GMT
Links: << >>  << T >>  << A >>
thank you ...

I will try that

this is what i tought just try a simple gpio with the wrapper

regards

jonathan
"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le 
message de news: 42111c81$0$321$ba620e4c@news.skynet.be...
> Hi
>
> Jonathan Dumaresq wrote:
>
>> I want to do exactly what you do. but i'm stuck to the netlist problem.
>
> Glad to know I'm not alone ;)
>
>
>> I use the wb2opb from ascic.ws and now i want to use some opencore ip to
>> plug to my microblaze. so if you can send to this ng what you have done 
>> to
>> make it work i'll apreciated
>
> Well, finally I got a bitstream ! But ... it doesn't work as excpected so 
> I'm
> not sure that what I've done is good.
>
> So finally I decided to try a smaller problem, just take
> Microblaze + UART + opb2wb + opencore_simple_gpio and try to make this 
> work.
>
> Here's what I'm trying right now (writing this msg as I'm doing/testing it 
> ;)
> From ground up :
>
> * First step : Install the opb2wb
> --------------------------------
>
> - Extract the opb2wb_v1_00_a from the tar.gz and put it into your 
> personnal pcore dir
> - Edit the bbd file and suppress the first column (C_FAMILY) to just leave 
> the first line
>   So you should have
>
> <cut here>
> Files
> ###########...#####
> opb2wb_v1_00_a.edn
> <end cut>
>
> - Edit the mpd file and rename the 'opb_rst' into 'rst' (only the 
> lowercase one.
>   leave the OPB_rst untouched ). - Edit the netlist file (.edn) and change 
> the creator program to "none"
>   So you have (program "none") instead of (program "xilinx stuff ...")
>   The ngcbuild don't like to work with edif netlist created by ngc2edit 
> and tells
>   you to use the original ngc instead but we don't have it ...
>
>
> *** At this point, adding a opb2wb to an existing/working design and 
> making all
>    wb connections external works (I mean you can produce a bitstream. I 
> don't
>    know if the wrapper works or not ... ****
>
>
> * Second step : Creating a wb_gpio_simple EDK-compatible core
> -------------------------------------------------------------
>
> - I've used the simple_gpio core as a base to create my own very simple 
> gpio_core
>   ... And I'm still at this step and won't finish tonight ;)
> I already send this which may help you.
>
>
>
>
> Note that some steps might be unecessary, I just wrote that as a 
> collection of
> all the things I made to make it generate a bitstream.
>
> Sylvain
> 





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