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On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > I wonder if anyone had any success using either DirectC 2.2 or SVF > files to program Actel PA3 devices. All my attempts are failing so > far. > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > 1 time success from 100 attempts to program the part > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > even get as far as checking jtag IDCODE > 3) custom SVF player also shows weird behaviour > > Antti Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to JTAG Cable). Amontec SVF Player support Trailer Header and infinite Scan Length. Note: if the IDCODE failed SOMETIMES this could mean you have a bad JTAG connection (between the Xilinx Cable III <-> target board). Make sure to not route the TCK parallel to the TDI or TDO, we have the experience that this could infer to the stability of the JTAG FSM even if you run JTAG at very low speed. You could try to add a 100R resistor on TCK close to Target. Almost sure your issue is not coming from the SVF file nor the Player, but from your JTAG signal integrity. Regards, Laurent http://www.amontec.comArticle: 130051
On 14 Mrz., 08:26, j...@amontec.com wrote: > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > Hi > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > files to program Actel PA3 devices. All my attempts are failing so > > far. > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > 1 time success from 100 attempts to program the part > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > even get as far as checking jtag IDCODE > > 3) custom SVF player also shows weird behaviour > > > Antti > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > JTAG Cable). > Amontec SVF Player support Trailer Header and infinite Scan Length. > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > JTAG connection (between the Xilinx Cable III <-> target board). > Make sure to not route the TCK parallel to the TDI or TDO, we have the > experience that this could infer to the stability of the JTAG FSM even > if you run JTAG at very low speed. > You could try to add a 100R resistor on TCK close to Target. > > Almost sure your issue is not coming from the SVF file nor the Player, > but from your JTAG signal integrity. > > Regards, > Laurenthttp://www.amontec.com Larry normally I would agree with you, but: it is not that the failures are some times or random: 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR 100% failure when trying with SVF file and impact 100% ok, when trying XSVF file and impact 100% failure when adding extra delay in RTI state (TCK IDLE NOT TOGGLING) in custom SVF player 100% ok when doing FAST playback in custom SVF player 3) DirectC a) once worked full programming cycle b) place of failure depends on the VC compile target (debug or release) the place of failure is constant, but rather soon in the file, ISP_entry command, after IDCODE check. the DirectC timing calibration value is dependant on the build target, so i assume some speed issue here hardware currently in use *) Amontec Chameleon with Xilinx JTAG fly-wire adapter *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for all connections I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to test with :( Please look above my observations, could you still assume it is signal integrity issue? The pass-fail depends on the time spent in RTI when TCK is not toggling, meaning there are no signal toggling at all! I am puzzled at least. AnttiArticle: 130052
I get the impression that Altera is in the lead when it comes to speed on DDR[3] interfaces. Can anyone confirm/deny this? Altera claims to be able to clock a 64/72bit wide DDR3 at 533Mhz on the StratixIII: http://www.altera.com/b/stratixiii-ddr3-video.html For Xilinx, the fastest reference design I can find is 32bit wide DDR3 at 400Mhz for the Virtex5. Can Virtex4 do better? So far, it looks to me like Altera did a KO on Xilinx when it comes to DDR3. Please tell me I'm wrong, Id hate to switch tools :p (and I need hard facts, not sales numbers)Article: 130053
On 14 Mrz., 09:28, "Morten Leikvoll" <mleik...@yajoo.nospam> wrote: > I get the impression that Altera is in the lead when it comes to speed on > DDR[3] interfaces. Can anyone confirm/deny this? > > Altera claims to be able to clock a 64/72bit wide DDR3 at 533Mhz on the > StratixIII:http://www.altera.com/b/stratixiii-ddr3-video.html > For Xilinx, the fastest reference design I can find is 32bit wide DDR3 at > 400Mhz for the Virtex5. Can Virtex4 do better? > > So far, it looks to me like Altera did a KO on Xilinx when it comes to DDR3. > Please tell me I'm wrong, Id hate to switch tools :p > (and I need hard facts, not sales numbers) no, V4 can not do better . KO? did you count 10? :) Antti PS even DDR2 designs at 200MHz is not trivial for V4/V5, I would be very careful before trying some Xilinx chip at memory clock above what Xilinx itself claims. It doesnt mean that is not doable of course. Already V4 slowest speed grade FPGA fabric can have signals as high as 1GHz (my own test measurements!) for very short distances, so 533 should not be impossible for V5 highest speed grade. But its not the fabric or I/O speed alone that is needed for the successful implementation. PPS Xilinx are you KO? 1,2,3... tick-tock clock is tickingArticle: 130054
Morten Leikvoll wrote: > I get the impression that Altera is in the lead when it comes to speed on > DDR[3] interfaces. Can anyone confirm/deny this? > > Altera claims to be able to clock a 64/72bit wide DDR3 at 533Mhz on the > StratixIII: http://www.altera.com/b/stratixiii-ddr3-video.html > For Xilinx, the fastest reference design I can find is 32bit wide DDR3 at > 400Mhz for the Virtex5. Can Virtex4 do better? Altera has dedicated logic for source synchronous clocking for memories, that might make the difference. But be aware that that dedicated logic also creates more restrictions to pin placement and can waste big amounts of pins if you use many IO-voltages. In Xilinx V4/V5 the pin placement is sometimes easier to do. IO-structure is always a compromise between speed and flexibility. --KimArticle: 130055
David Brown wrote: >> >> Nope. The Altera USB dongle is a FT245BL -> EPM3128ATC100. (The EPM >> does the FIFO to JTAG translation.) >> > > Do you have any idea why the do that instead of using an FT2232C and > skipping the EPM3128 entirely? The FT2232C has a fast synchronous > serial mode designed precisely for jtag programming and similar > situations. It costs a bit more than the FT245BL, but is a lot cheaper > than an EPM3128 - and it has a second USB-UART port included. > I'm almost sure the answer is "so that a programming cable can be sold at $300". For whatever reason both A and X decided to stop publishing simple programming designs like the old parallel port cables and charge ridiculous prices for the tools. I think it is down to $150 now and a clone is available for about $50. -Alex. From webmaster@nillakaes.de Fri Mar 14 02:23:16 2008 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!newsfeed.straub-nv.de!newsfeeder.dynfx.net!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <47da43e3$0$581$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: Problem with Spartan 3 StarterKit Newsgroups: comp.arch.fpga Date: Fri, 14 Mar 2008 10:23:16 +0100 References: <47d962a7$0$580$6e1ede2f@read.cnntp.org> <47d98d8e$0$580$6e1ede2f@read.cnntp.org> <rO-dndK3PeRLOUTanZ2dnUVZ_vyinZ2d@speakeasy.net> <rO-dnc23PeQYOETanZ2dnUVZ_vzinZ2d@speakeasy.net> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 11 Organization: CNNTP NNTP-Posting-Host: 850821df.read.cnntp.org X-Trace: DXC=^@X?oY1fP@d@an3;^ZB9PfWoT\PAgXa?aO>f1biSlT6g1P5d:S1^>6cdlT:^LKmYjjYk2b`lT@NVgXWdc^NffR?d X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:142406 > Also, don't forget to change the configuration mode back to master > serial after you have programmed the platform flash. Oh, you have to > either cycle power or press the 'FGPA program' switch (if this is one on > the board) before the FPGA will be loaded from the platform flash. I got it working now. I can leave the jumpers in "master serial" while I program the flash. The fpga boots automatically from the flash. Thanks for your help! -ThorstenArticle: 130056
ghelbig@lycos.com wrote: > On Mar 12, 8:53 pm, "Xilinx User" <anonym...@net.com> wrote: >> I thought Altera uses one of FTDI 's USB/RS-232 bridge-chips in their >> programming solution. >> > > Nope. The Altera USB dongle is a FT245BL -> EPM3128ATC100. (The EPM > does the FIFO to JTAG translation.) > Do you have any idea why the do that instead of using an FT2232C and skipping the EPM3128 entirely? The FT2232C has a fast synchronous serial mode designed precisely for jtag programming and similar situations. It costs a bit more than the FT245BL, but is a lot cheaper than an EPM3128 - and it has a second USB-UART port included. > The USB port the OP "found" is literally the Altera USB dongle without > the plastic case. > > G.Article: 130057
Hi All, I was looking at the Xilinx website today and saw the new Spartan 3 DSP EDK board. It seems like a pretty good deal, as the board by itself is 295, the usb JTAG cable is 199 and the EDK, well, I couldn't work out how much that normally costs ($130?!?) , but still thats at least $100 off the price assuming the EDK is free, which is extremely tempting. Am I missing something. Or is this just a good initial offering to get me "hooked" Thanks JoelArticle: 130058
On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 14 Mrz., 08:26, j...@amontec.com wrote: > > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Hi > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > > files to program Actel PA3 devices. All my attempts are failing so > > > far. > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > > 1 time success from 100 attempts to program the part > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > > even get as far as checking jtag IDCODE > > > 3) custom SVF player also shows weird behaviour > > > > Antti > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > > JTAG Cable). > > Amontec SVF Player support Trailer Header and infinite Scan Length. > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > > JTAG connection (between the Xilinx Cable III <-> target board). > > Make sure to not route the TCK parallel to the TDI or TDO, we have the > > experience that this could infer to the stability of the JTAG FSM even > > if you run JTAG at very low speed. > > You could try to add a 100R resistor on TCK close to Target. > > > Almost sure your issue is not coming from the SVF file nor the Player, > > but from your JTAG signal integrity. > > > Regards, > > Laurenthttp://www.amontec.com > > Larry > > normally I would agree with you, but: > > it is not that the failures are some times or random: > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR > > 100% failure when trying with SVF file and impact > 100% ok, when trying XSVF file and impact > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT > TOGGLING) in custom SVF player > 100% ok when doing FAST playback in custom SVF player > > 3) DirectC > a) once worked full programming cycle > b) place of failure depends on the VC compile target (debug or > release) the place of failure is constant, but rather soon in the > file, ISP_entry command, after IDCODE check. the DirectC timing > calibration value is dependant on the build target, so i assume some > speed issue here > > hardware currently in use > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for > all connections > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to > test with :( This could help. > > Please look above my observations, could you still assume it is signal > integrity issue? The pass-fail depends on the time spent in RTI when > TCK is not toggling, meaning there are no signal toggling at all! I am > puzzled at least. > > Antti What is your ENDIR and ENDDR ? Maybe try to add RUNTEST when in RTI. But if this help, there could be a bug in the Actel JTAG FSM! ... anyway, why do you not provide us a part of the SVF you are running for the IDCODE? Laurent http://www.amontec.comArticle: 130059
On 14 Mrz., 10:50, j...@amontec.com wrote: > On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 14 Mrz., 08:26, j...@amontec.com wrote: > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > Hi > > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > > > files to program Actel PA3 devices. All my attempts are failing so > > > > far. > > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > > > 1 time success from 100 attempts to program the part > > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > > > even get as far as checking jtag IDCODE > > > > 3) custom SVF player also shows weird behaviour > > > > > Antti > > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > > > JTAG Cable). > > > Amontec SVF Player support Trailer Header and infinite Scan Length. > > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > > > JTAG connection (between the Xilinx Cable III <-> target board). > > > Make sure to not route the TCK parallel to the TDI or TDO, we have the > > > experience that this could infer to the stability of the JTAG FSM even > > > if you run JTAG at very low speed. > > > You could try to add a 100R resistor on TCK close to Target. > > > > Almost sure your issue is not coming from the SVF file nor the Player, > > > but from your JTAG signal integrity. > > > > Regards, > > > Laurenthttp://www.amontec.com > > > Larry > > > normally I would agree with you, but: > > > it is not that the failures are some times or random: > > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! > > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR > > > 100% failure when trying with SVF file and impact > > 100% ok, when trying XSVF file and impact > > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT > > TOGGLING) in custom SVF player > > 100% ok when doing FAST playback in custom SVF player > > > 3) DirectC > > a) once worked full programming cycle > > b) place of failure depends on the VC compile target (debug or > > release) the place of failure is constant, but rather soon in the > > file, ISP_entry command, after IDCODE check. the DirectC timing > > calibration value is dependant on the build target, so i assume some > > speed issue here > > > hardware currently in use > > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter > > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for > > all connections > > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : > > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the > > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to > > test with :( > This could help. > > > Please look above my observations, could you still assume it is signal > > integrity issue? The pass-fail depends on the time spent in RTI when > > TCK is not toggling, meaning there are no signal toggling at all! I am > > puzzled at least. > > > Antti > > What is your ENDIR and ENDDR ? > > Maybe try to add RUNTEST when in RTI. But if this help, there could be > a bug in the Actel JTAG FSM! > > ... anyway, why do you not provide us a part of the SVF you are > running for the IDCODE? > > Laurenthttp://www.amontec.com == cutout from Actel libero 8.1 generated SVF == FREQUENCY 4E6 HZ; STATE RESET; RUNTEST IDLE 5 TCK; ENDIR IRPAUSE; ENDDR DRPAUSE; SIR 8 TDI(0F); SDR 32 TDI(00000000); STATE IDLE; RUNTEST IDLE 1 TCK; SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); === the above fails 100% with impact if played back as SVF the same or modified one converted to XSVF works 100% in my own code i tried ENDxR IDLE vs PAUSE but i did not work out any fully working solution AnttiArticle: 130060
On Mar 14, 11:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 14 Mrz., 10:50, j...@amontec.com wrote: > > > > > On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 14 Mrz., 08:26, j...@amontec.com wrote: > > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > Hi > > > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > > > > files to program Actel PA3 devices. All my attempts are failing so > > > > > far. > > > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > > > > 1 time success from 100 attempts to program the part > > > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > > > > even get as far as checking jtag IDCODE > > > > > 3) custom SVF player also shows weird behaviour > > > > > > Antti > > > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > > > > JTAG Cable). > > > > Amontec SVF Player support Trailer Header and infinite Scan Length. > > > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > > > > JTAG connection (between the Xilinx Cable III <-> target board). > > > > Make sure to not route the TCK parallel to the TDI or TDO, we have the > > > > experience that this could infer to the stability of the JTAG FSM even > > > > if you run JTAG at very low speed. > > > > You could try to add a 100R resistor on TCK close to Target. > > > > > Almost sure your issue is not coming from the SVF file nor the Player, > > > > but from your JTAG signal integrity. > > > > > Regards, > > > > Laurenthttp://www.amontec.com > > > > Larry > > > > normally I would agree with you, but: > > > > it is not that the failures are some times or random: > > > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! > > > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR > > > > 100% failure when trying with SVF file and impact > > > 100% ok, when trying XSVF file and impact > > > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT > > > TOGGLING) in custom SVF player > > > 100% ok when doing FAST playback in custom SVF player > > > > 3) DirectC > > > a) once worked full programming cycle > > > b) place of failure depends on the VC compile target (debug or > > > release) the place of failure is constant, but rather soon in the > > > file, ISP_entry command, after IDCODE check. the DirectC timing > > > calibration value is dependant on the build target, so i assume some > > > speed issue here > > > > hardware currently in use > > > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter > > > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for > > > all connections > > > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : > > > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the > > > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to > > > test with :( > > This could help. > > > > Please look above my observations, could you still assume it is signal > > > integrity issue? The pass-fail depends on the time spent in RTI when > > > TCK is not toggling, meaning there are no signal toggling at all! I am > > > puzzled at least. > > > > Antti > > > What is your ENDIR and ENDDR ? > > > Maybe try to add RUNTEST when in RTI. But if this help, there could be > > a bug in the Actel JTAG FSM! > > > ... anyway, why do you not provide us a part of the SVF you are > > running for the IDCODE? > > > Laurenthttp://www.amontec.com > > == cutout from Actel libero 8.1 generated SVF == > FREQUENCY 4E6 HZ; > STATE RESET; > RUNTEST IDLE 5 TCK; > ENDIR IRPAUSE; > ENDDR DRPAUSE; > SIR 8 TDI(0F); > SDR 32 TDI(00000000); > STATE IDLE; > RUNTEST IDLE 1 TCK; > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > === > > the above fails 100% with impact if played back as SVF > the same or modified one converted to XSVF works 100% > > in my own code i tried ENDxR IDLE vs PAUSE but i did not work out any > fully working solution > > Antti Try the two following one and let us know the result: == cutout from Actel libero 8.1 generated SVF == FREQUENCY 4E6 HZ; STATE RESET; RUNTEST IDLE 5 TCK; ENDIR IDLE; ENDDR IDLE; SIR 8 TDI(0F); SDR 32 TDI(00000000); // STATE IDLE; RUNTEST IDLE 1 TCK; SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); === == cutout from Actel libero 8.1 generated SVF == FREQUENCY 4E6 HZ; STATE RESET; STATE RESET; STATE RESET; STATE RESET; STATE RESET; RUNTEST RESET 5 TCK; ENDIR IDLE; ENDDR IDLE; SIR 8 TDI(0F); SDR 32 TDI(00000000); // STATE IDLE; RUNTEST IDLE 1 TCK; SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); === Laurent http://www.amontec.comArticle: 130061
Hi there, i have some problems while integrating a special dual port RAM core (generated in xillinx ISE) into a Xillinx EDK project. The ports of my DP-RAM are designed differently inorder to increase the rate of data exchange. The DP-RAM size is 1Kbytes. The access on the port A is byte-wise, so the resulting address length is 10 bits wide. On the port B the access is 4-byte-wise, so that the resulting address length is 8bits wide. Inorder to connect this dual port RAM to a microblaze, I used an ip_bram_controller which is a ready-made IP core in EDK.The ip_bram_controller serves as the interface between the microblaze and dual port RAM. This ip_bram_controller has an address length of 32bit on both sides. The signals of port A of my dual prot RAM are defined as external signals and assigned to pins on an external board(FPGA board). The signals of port B are then assigned to the signals of the corresponding port on the ip_bram_controller. This implies that the 8bit address bus of my dual port is assigned to the 32bit address bus of the ip_bram_controller.All this is done manually in EDK. Here is the problem: Inorder to generate a netlist for the components and consequent bitstream for the design there is this persistent error which says the address buses of 8bit and 32bit are not compartible. My question is, how can i connect my DP-RAM directly to the opb bus, without using a ip_bram_controller? I have this error when i use the bram controller: G:\Fohtung \DAP_Evaluation_Package\LLC\refBasic\ML403\microblaze\system.mhs line 318 - 32 bit-width connector does not match 8 bit-width port How can I get these two to match? I'll be grateful for an answer. Thanks in advance! Livia.Article: 130062
On 14 Mrz., 11:34, j...@amontec.com wrote: > On Mar 14, 11:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 14 Mrz., 10:50, j...@amontec.com wrote: > > > > On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 14 Mrz., 08:26, j...@amontec.com wrote: > > > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > Hi > > > > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > > > > > files to program Actel PA3 devices. All my attempts are failing so > > > > > > far. > > > > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > > > > > 1 time success from 100 attempts to program the part > > > > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > > > > > even get as far as checking jtag IDCODE > > > > > > 3) custom SVF player also shows weird behaviour > > > > > > > Antti > > > > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > > > > > JTAG Cable). > > > > > Amontec SVF Player support Trailer Header and infinite Scan Length. > > > > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > > > > > JTAG connection (between the Xilinx Cable III <-> target board). > > > > > Make sure to not route the TCK parallel to the TDI or TDO, we have the > > > > > experience that this could infer to the stability of the JTAG FSM even > > > > > if you run JTAG at very low speed. > > > > > You could try to add a 100R resistor on TCK close to Target. > > > > > > Almost sure your issue is not coming from the SVF file nor the Player, > > > > > but from your JTAG signal integrity. > > > > > > Regards, > > > > > Laurenthttp://www.amontec.com > > > > > Larry > > > > > normally I would agree with you, but: > > > > > it is not that the failures are some times or random: > > > > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! > > > > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR > > > > > 100% failure when trying with SVF file and impact > > > > 100% ok, when trying XSVF file and impact > > > > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT > > > > TOGGLING) in custom SVF player > > > > 100% ok when doing FAST playback in custom SVF player > > > > > 3) DirectC > > > > a) once worked full programming cycle > > > > b) place of failure depends on the VC compile target (debug or > > > > release) the place of failure is constant, but rather soon in the > > > > file, ISP_entry command, after IDCODE check. the DirectC timing > > > > calibration value is dependant on the build target, so i assume some > > > > speed issue here > > > > > hardware currently in use > > > > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter > > > > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for > > > > all connections > > > > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : > > > > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the > > > > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to > > > > test with :( > > > This could help. > > > > > Please look above my observations, could you still assume it is signal > > > > integrity issue? The pass-fail depends on the time spent in RTI when > > > > TCK is not toggling, meaning there are no signal toggling at all! I am > > > > puzzled at least. > > > > > Antti > > > > What is your ENDIR and ENDDR ? > > > > Maybe try to add RUNTEST when in RTI. But if this help, there could be > > > a bug in the Actel JTAG FSM! > > > > ... anyway, why do you not provide us a part of the SVF you are > > > running for the IDCODE? > > > > Laurenthttp://www.amontec.com > > > == cutout from Actel libero 8.1 generated SVF == > > FREQUENCY 4E6 HZ; > > STATE RESET; > > RUNTEST IDLE 5 TCK; > > ENDIR IRPAUSE; > > ENDDR DRPAUSE; > > SIR 8 TDI(0F); > > SDR 32 TDI(00000000); > > STATE IDLE; > > RUNTEST IDLE 1 TCK; > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > > === > > > the above fails 100% with impact if played back as SVF > > the same or modified one converted to XSVF works 100% > > > in my own code i tried ENDxR IDLE vs PAUSE but i did not work out any > > fully working solution > > > Antti > > Try the two following one and let us know the result: > > == cutout from Actel libero 8.1 generated SVF == > FREQUENCY 4E6 HZ; > STATE RESET; > RUNTEST IDLE 5 TCK; > ENDIR IDLE; > ENDDR IDLE; > SIR 8 TDI(0F); > SDR 32 TDI(00000000); > // STATE IDLE; > RUNTEST IDLE 1 TCK; > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > === > > == cutout from Actel libero 8.1 generated SVF == > FREQUENCY 4E6 HZ; > STATE RESET; > STATE RESET; > STATE RESET; > STATE RESET; > STATE RESET; > RUNTEST RESET 5 TCK; > ENDIR IDLE; > ENDDR IDLE; > SIR 8 TDI(0F); > SDR 32 TDI(00000000); > // STATE IDLE; > RUNTEST IDLE 1 TCK; > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > === > > Laurenthttp://www.amontec.com I tried some similar things, and many more, with not much luck AnttiArticle: 130063
joel.pigdon@gmail.com wrote: > Hi All, > I was looking at the Xilinx website today and saw the new Spartan 3 > DSP EDK board. > It seems like a pretty good deal, as the board by itself is 295, the > usb JTAG cable is 199 and the EDK, well, I couldn't work out how much > that normally costs ($130?!?) , but still thats at least $100 off the > price assuming the EDK is free, which is extremely tempting. > Am I missing something. Or is this just a good initial offering to get > me "hooked" It's a good deal. But beware, it has DDR2 ram, were I didn't find free ip to run Mico32... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130064
On Mar 14, 1:25 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 14 Mrz., 11:34, j...@amontec.com wrote: > > > > > On Mar 14, 11:03 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 14 Mrz., 10:50, j...@amontec.com wrote: > > > > > On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > On 14 Mrz., 08:26, j...@amontec.com wrote: > > > > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > > Hi > > > > > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF > > > > > > > files to program Actel PA3 devices. All my attempts are failing so > > > > > > > far. > > > > > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had > > > > > > > 1 time success from 100 attempts to program the part > > > > > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt > > > > > > > even get as far as checking jtag IDCODE > > > > > > > 3) custom SVF player also shows weird behaviour > > > > > > > > Antti > > > > > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to > > > > > > JTAG Cable). > > > > > > Amontec SVF Player support Trailer Header and infinite Scan Length. > > > > > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad > > > > > > JTAG connection (between the Xilinx Cable III <-> target board). > > > > > > Make sure to not route the TCK parallel to the TDI or TDO, we have the > > > > > > experience that this could infer to the stability of the JTAG FSM even > > > > > > if you run JTAG at very low speed. > > > > > > You could try to add a 100R resistor on TCK close to Target. > > > > > > > Almost sure your issue is not coming from the SVF file nor the Player, > > > > > > but from your JTAG signal integrity. > > > > > > > Regards, > > > > > > Laurenthttp://www.amontec.com > > > > > > Larry > > > > > > normally I would agree with you, but: > > > > > > it is not that the failures are some times or random: > > > > > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!! > > > > > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR > > > > > > 100% failure when trying with SVF file and impact > > > > > 100% ok, when trying XSVF file and impact > > > > > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT > > > > > TOGGLING) in custom SVF player > > > > > 100% ok when doing FAST playback in custom SVF player > > > > > > 3) DirectC > > > > > a) once worked full programming cycle > > > > > b) place of failure depends on the VC compile target (debug or > > > > > release) the place of failure is constant, but rather soon in the > > > > > file, ISP_entry command, after IDCODE check. the DirectC timing > > > > > calibration value is dependant on the build target, so i assume some > > > > > speed issue here > > > > > > hardware currently in use > > > > > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter > > > > > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for > > > > > all connections > > > > > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon : > > > > > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the > > > > > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to > > > > > test with :( > > > > This could help. > > > > > > Please look above my observations, could you still assume it is signal > > > > > integrity issue? The pass-fail depends on the time spent in RTI when > > > > > TCK is not toggling, meaning there are no signal toggling at all! I am > > > > > puzzled at least. > > > > > > Antti > > > > > What is your ENDIR and ENDDR ? > > > > > Maybe try to add RUNTEST when in RTI. But if this help, there could be > > > > a bug in the Actel JTAG FSM! > > > > > ... anyway, why do you not provide us a part of the SVF you are > > > > running for the IDCODE? > > > > > Laurenthttp://www.amontec.com > > > > == cutout from Actel libero 8.1 generated SVF == > > > FREQUENCY 4E6 HZ; > > > STATE RESET; > > > RUNTEST IDLE 5 TCK; > > > ENDIR IRPAUSE; > > > ENDDR DRPAUSE; > > > SIR 8 TDI(0F); > > > SDR 32 TDI(00000000); > > > STATE IDLE; > > > RUNTEST IDLE 1 TCK; > > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > > > === > > > > the above fails 100% with impact if played back as SVF > > > the same or modified one converted to XSVF works 100% > > > > in my own code i tried ENDxR IDLE vs PAUSE but i did not work out any > > > fully working solution > > > > Antti > > > Try the two following one and let us know the result: > > > == cutout from Actel libero 8.1 generated SVF == > > FREQUENCY 4E6 HZ; > > STATE RESET; > > RUNTEST IDLE 5 TCK; > > ENDIR IDLE; > > ENDDR IDLE; > > SIR 8 TDI(0F); > > SDR 32 TDI(00000000); > > // STATE IDLE; > > RUNTEST IDLE 1 TCK; > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > > === > > > == cutout from Actel libero 8.1 generated SVF == > > FREQUENCY 4E6 HZ; > > STATE RESET; > > STATE RESET; > > STATE RESET; > > STATE RESET; > > STATE RESET; > > RUNTEST RESET 5 TCK; > > ENDIR IDLE; > > ENDDR IDLE; > > SIR 8 TDI(0F); > > SDR 32 TDI(00000000); > > // STATE IDLE; > > RUNTEST IDLE 1 TCK; > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > > === > > > Laurenthttp://www.amontec.com > > I tried some similar things, and many more, with not much luck > > Antti Antti, But did you have try the two ones I gave you? similar or similar or maybe similar ? ;-) Laurent http://www.amontec.comArticle: 130065
On 14 Mrz., 13:34, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > joel.pig...@gmail.com wrote: > > Hi All, > > I was looking at the Xilinx website today and saw the new Spartan 3 > > DSP EDK board. > > It seems like a pretty good deal, as the board by itself is 295, the > > usb JTAG cable is 199 and the EDK, well, I couldn't work out how much > > that normally costs ($130?!?) , but still thats at least $100 off the > > price assuming the EDK is free, which is extremely tempting. > > Am I missing something. Or is this just a good initial offering to get > > me "hooked" > > It's a good deal. But beware, it has DDR2 ram, were I didn't find free ip to > run Mico32... > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe there is no free DDR2 for mico32. yet. Xilinx EDK based designs are most likely to be only ones that uses the DDR2. from that point of view some older S3 boards with SDRAM or DDR are better as there are more choices AnttiArticle: 130066
Hi, We think we have found the problem. Newlib(libc) functions which is reentrant uses the heap. Your design didn't have any heap allocated at all so when these function calls malloc it will grab memory which holds the interrupt vector. These addresses will be overwritten and the program gets corrupted. A very small heap size will fix the issue. Göran "Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:fqivp6$d371@cnn.xsj.xilinx.com... > Hi Rémy, > > Can you provide me with the MicroBlaze configuration settings (or the > whole .mhs file)? > It looks like you get a hardware exception but you don't have a exception > handler. > What hardware exceptions have you enabled on MicroBlaze? > > Göran > > "Rémy" <thomasrt2008@gmail.com> wrote in message > news:f6cbd175-5bc5-4a9a-9b64-5e8a1b386299@e6g2000prf.googlegroups.com... > Hi, > > I just try the patch http://www.xilinx.com/support/answers/30051.htm > and the bug steal occurs if I have a "rand" or "srand" function in my > code. > When i stop the CPU under XMD it returns me the same adress: > 0x820036a4 > > if i do "mb-objdump -x -D -S -t executable.elf > dump.out" to output a > dump file of my *.elf to see what there is at this address: > > .section .text > .align 2 > .ent _hw_exception_handler > _hw_exception_handler: > bri 0; > 820036a4: b8000000 bri 0 // 820036a4 > > so apparently the code is crashed because of an exeption like the > problem in "Answer Record #29784 (http://www.xilinx.com/support/ > answers/ > 29784.htm". Although i work on the last version of tools with the SP2 > and the last patch.... > > I have tried my code on a PowerPC architecture with the same IP on the > same Hardware and I don't have the bug. > > Rémy >Article: 130067
Morten, We chose different paths: Altera used hardened logic to get their speed, where we chose to stay general, and use any pins/any fabric/any standard. We have DDR3 designs that are also working at 533 MHz. Best to sit down and talk with your FAE on the subject. There are many other factors to consider (not he least of which is we are in full production on Virtex 5 LX, LXT, SXT, and they are just now in ES on on few parts, with S3 GX canceled completely). Even though Altera has some really mean, cool, and neat power point presentations, we basically have no competition whatsoever at 65nm at the high end (as you can't ship power point in your systems). AustinArticle: 130068
On Mar 13, 10:12 pm, John_H <newsgr...@johnhandwork.com> wrote: > Sue wrote: > > Does anyone know how can one enter FSM in Xilinx sysnthesis tool. > > I have a FSM in a text format called the kiss2 format. > > It looks something like this: > > > file input.kiss2 > > --------------------------------------------start of > > file--------------------------- > > .i 2 > > .o 2 > > .p 8 > > .s 4 > > 01 s0 s1 11 > > 11 so s3 00 > > 01 s1 s0 11 > > 11 s1 s2 00 > > 1- s2 s3 01 > > 0- s2 s1 10 > > 11 s3 s0 10 > > 10 s3 s2 11 > > --------------------------------------------end of > > file--------------------------------- > > i= # of inputs > > o= # of outputs > > p= # of transitions > > s= # of states > > 01 so s1 11 = this is read as for input 01 and current state s0 the > > output is 11 and next state is s1. > > '-' means don't care > > > Does anyone know a way in which I can convert this to a format such > > that it can be entered into the Xilinx synthesis tool and I can get > > the FSM synthesized for further use my implementation > Please find the answers below your questions. > Are you a software guy? Yes I am a SW guy > Do you use Verilog? No I don't > Do you use VHDL? Yes I do > Do you know what a state machine is? Yes > Do you know how the HDL generally maps to hardware? No I don't know how this maps > Do you understand what the file above is communicating? > Yes I know what the file is communicating > Answer us [sic] and we can answer you.Article: 130069
On Mar 14, 8:40=A0am, Sue <sudha...@gmail.com> wrote: > On Mar 13, 10:12 pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > Sue wrote: > > > Does anyone know how can =A0one enter FSM in Xilinx sysnthesis tool. > > > I have a FSM in a text format called the kiss2 format. > > > It looks something like this: > > > > file input.kiss2 > > > --------------------------------------------start of > > > file--------------------------- > > > .i 2 > > > .o 2 > > > .p 8 > > > .s 4 > > > 01 s0 s1 11 > > > 11 so s3 00 > > > 01 s1 s0 11 > > > 11 s1 s2 00 > > > 1- s2 s3 01 > > > 0- s2 s1 10 > > > 11 s3 s0 10 > > > 10 s3 s2 11 > > > --------------------------------------------end of > > > file--------------------------------- > > > i=3D # of inputs > > > o=3D # of outputs > > > p=3D # of transitions > > > s=3D # of states > > > 01 so s1 11 =3D this is read as for input 01 and current state s0 the > > > output is 11 and next state is s1. > > > =A0'-' means don't care > > > > Does anyone know a way in which I can convert this to a format such > > > that it can be entered into the Xilinx synthesis tool and I can get > > > the FSM synthesized for further use my implementation > > Please find the answers below your questions. > > Are you a software guy? > Yes I am a SW guy > > Do you use Verilog? > No I don't > > Do you use VHDL? > Yes I do > > Do you know what a state machine is? > Yes > > Do you know how the HDL generally maps to hardware? > > No I don't know how this maps > > > > > Do you understand what the file above is communicating? > > Yes I know what the file is communicating > > Answer us [sic] and we can answer you.- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Six questions. One answer. Go away.Article: 130070
On 14 Mrz., 16:24, austin <aus...@xilinx.com> wrote: > Morten, > > We chose different paths: Altera used hardened logic to get their > speed, where we chose to stay general, and use any pins/any fabric/any > standard. > > We have DDR3 designs that are also working at 533 MHz. > > Best to sit down and talk with your FAE on the subject. > > There are many other factors to consider (not he least of which is we > are in full production on Virtex 5 LX, LXT, SXT, and they are just now > in ES on on few parts, with S3 GX canceled completely). > > Even though Altera has some really mean, cool, and neat power point > presentations, we basically have no competition whatsoever at 65nm at > the high end (as you can't ship power point in your systems). > > Austin LOL, eh, think there is only one tool we need: "powerpoint to silicon compiler" ;) Antti PS 553 MHz DDR3 without hardened io and general purpose FPGA is nice achievmentArticle: 130071
On Mar 14, 9:47 am, John_H <newsgr...@johnhandwork.com> wrote: > On Mar 14, 8:40 am, Sue <sudha...@gmail.com> wrote: > > > > > On Mar 13, 10:12 pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > Sue wrote: > > > > Does anyone know how can one enter FSM in Xilinx sysnthesis tool. > > > > I have a FSM in a text format called the kiss2 format. > > > > It looks something like this: > > > > > file input.kiss2 > > > > --------------------------------------------start of > > > > file--------------------------- > > > > .i 2 > > > > .o 2 > > > > .p 8 > > > > .s 4 > > > > 01 s0 s1 11 > > > > 11 so s3 00 > > > > 01 s1 s0 11 > > > > 11 s1 s2 00 > > > > 1- s2 s3 01 > > > > 0- s2 s1 10 > > > > 11 s3 s0 10 > > > > 10 s3 s2 11 > > > > --------------------------------------------end of > > > > file--------------------------------- > > > > i= # of inputs > > > > o= # of outputs > > > > p= # of transitions > > > > s= # of states > > > > 01 so s1 11 = this is read as for input 01 and current state s0 the > > > > output is 11 and next state is s1. > > > > '-' means don't care > > > > > Does anyone know a way in which I can convert this to a format such > > > > that it can be entered into the Xilinx synthesis tool and I can get > > > > the FSM synthesized for further use my implementation > > > Please find the answers below your questions. > > > Are you a software guy? > > Yes I am a SW guy > > > Do you use Verilog? > > No I don't > > > Do you use VHDL? > > Yes I do > > > Do you know what a state machine is? > > Yes > > > Do you know how the HDL generally maps to hardware? > > > No I don't know how this maps > > > > Do you understand what the file above is communicating? > > > Yes I know what the file is communicating > > > Answer us [sic] and we can answer you.- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > > - Show quoted text - > > Six questions. > One answer. > Go away. Sorry I think something went wrong. I had answered all the questions you asked for. Let me answer it once again Please find the answers below your questions. > Are you a software guy? Yes I am a SW guy > Do you use Verilog? No I don't > Do you use VHDL? Yes I do > Do you know what a state machine is? Yes > Do you know how the HDL generally maps to hardware? No I don't know how this maps >Do you understand what the file above is communicating? Yes I doArticle: 130072
On Mar 14, 2:50=A0am, joel.pig...@gmail.com wrote: > Hi All, > I was looking at the Xilinx website today and saw the new Spartan 3 > DSP EDK board. > > It seems like a pretty good deal, as the board by itself is 295, the > usb JTAG cable is 199 and the EDK, well, I couldn't work out how much > that normally costs ($130?!?) , but still thats at least $100 off the > price assuming the EDK is free, which is extremely tempting. > > Am I missing something. Or is this just a good initial offering to get > me "hooked" > > Thanks > > Joel Where do you get the idea EDK is free or available for a very low price?Article: 130073
On Mar 14, 11:52=A0am, Sue <sudha...@gmail.com> wrote: > > Do you use VHDL? > Yes I do > > Do you know what a state machine is? > Yes > > Do you know how the HDL generally maps to hardware? > > No I don't know how this maps >>Do you understand what the file above is communicating? > > Yes I do Since you know what a state machine is, and you know what the particular state machine is that you're talking about and you know VHDL....why wouldn't you simply rewrite it in VHDL? KJArticle: 130074
On Mar 14, 10:00 am, KJ <kkjenni...@sbcglobal.net> wrote: > On Mar 14, 11:52 am, Sue <sudha...@gmail.com> wrote: > > > > Do you use VHDL? > > Yes I do > > > Do you know what a state machine is? > > Yes > > > Do you know how the HDL generally maps to hardware? > > > No I don't know how this maps > >>Do you understand what the file above is communicating? > > > Yes I do > > Since you know what a state machine is, and you know what the > particular state machine is that you're talking about and you know > VHDL....why wouldn't you simply rewrite it in VHDL? > > KJ I have very long and lenghty FSMs to work on. This is just a small example. Some of the benchmark circuits that I have to work on have 20 states and around 100 transitions so it is not feasible to hard code each FSM in VHDl. Instead if I can have a tool which takes FSM in a txt file format and converts it to a synthesizable format, it will be very useful. Any suggestions? -Sue
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