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David, Re the potential reset limitations of some FPGA's raised in your reply, surely this will never arise as the synthesis tool will simply stick in inverters (to the FF o/ps) where needed? regds Mike In article <2oq54.2168$as2.6940@news.iol.ie>, "David Murray" <dmurray@iol.ie> wrote: > Marc , > I'm not sure if you included all your State machine definitions in your > description below e.g. (EppInDataRead, EppWaiting) . > > Anyway, some things to be careful of when you synthesis your One hot encoded > FSM's. During reset, your state register should look something like "00001" > and some FPGAs (although rarer these days) can only have a single global set > or reset which means that a '1' hot encoded state machine cannot be > synthesized to these type of devices. > > - David Murray > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19326
On Tue, 14 Dec 1999 12:53:17 GMT, deroberts@my-deja.com wrote: >In article <38510b91.1083590@modem.mecalc>, > lourens@mecalc.co.za wrote: >> Hi >> >> We have a board with 8 Altera MAX7000 CPLD's in the JTAG chain. Most >> of them are MAX7128A's and MAX7064A's with one MAX7256A. The devices >> work fine and I can program them successfully using the ByteBlaster. >> However, approximately every 10'th time I reprogram the MAX7256, it >> dies. It actually programs successfully, but them fails during the >> VERIFY phase. >> >> After this the ByteBlaster software can not see the JTAG chain >> anymore. Also, the MAX7256 temperature rises within seconds so that it >> is too hot to touch. >> >> Has anybody ever came across this? Any suggestions? I've check the >> layout and power supply and decoupling, it seems fine. >> >Yes, I've seen this. The programming stream gets corrupted while >programming the 7256, and turns some inputs into outputs, the device >then fights other devices driving it and can burn out. I glued heatsinks >onto mine until I got things figured out. > >The single biggest problem is the drive capacity of the ByteBlaster. >Altera reccomend buffering the Byteblaster signals if your chain has >more than 3 or 4 devices, and certainly if your blaster or parallel port >cable is in any way extended. > >Beyond that, I could only suggest splitting your JTAG chain in two, or >contacting Altera for support (only don't hold your breath). > >Derek Roberts. >AT&T Labs Cambridge, UK > > >Sent via Deja.com http://www.deja.com/ >Before you buy. Derek I do actually buffer the ByteBlaster signals with an LVT541 and the parallel port cable is extended. My Altera FAE, however, recommends upgrading the MaxPlusII Programmer from 9.1 to 9.3. I have done that but I am still waiting for a new batch of 7256's to test with. The corrupt programming stream theory certainly makes sense. This 7256 communicates with another 7128 in the chain who has also in the past given problems. I hope the new programming software sorts this out. Regards, Lourens ================================================================ Lourens Geldenhuys Tel: +27 (0)12 665 1480 Project Engineer Fax: +27 (0)12 665 1495 Mecalc (Pty) Ltd e-mail: lourens@mecalc.co.za 86 Oak Avenue, Highveld Technopark, Centurion, South Africa ================================================================Article: 19327
Hi Micheal,
I would never say 'never' where synthesis is concerned :)!!. I'm
quoting from past experience where this problem was passed by synthesis and
led to a functional error. (As far as I remember it was with a Xilinx 52xx
device and this was a few years ago, so the synthesis may not have been as
robust) . I would assume that todays synthesis tools are more robust but
then again... never assume! Again, this may not be the problem with Marc's
design, but I would be interested in finding out what is.
Regard
David
<micheal_thompson@my-deja.com> wrote in message
news:835p4k$7r9$1@nnrp1.deja.com...
> David,
>
> Re the potential reset limitations of some FPGA's raised in your reply,
> surely this will never arise as the synthesis tool will simply stick in
> inverters (to the FF o/ps) where needed?
>
> regds
> Mike
>
> In article <2oq54.2168$as2.6940@news.iol.ie>,
> "David Murray" <dmurray@iol.ie> wrote:
> > Marc ,
> > I'm not sure if you included all your State machine definitions in
> your
> > description below e.g. (EppInDataRead, EppWaiting) .
> >
> > Anyway, some things to be careful of when you synthesis your One hot
> encoded
> > FSM's. During reset, your state register should look something like
> "00001"
> > and some FPGAs (although rarer these days) can only have a single
> global set
> > or reset which means that a '1' hot encoded state machine cannot be
> > synthesized to these type of devices.
> >
> > - David Murray
> >
> >
> >
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 19328On Mon, 13 Dec 1999 18:09:39 +0100, Nicolas Matringe <nicolas@dotcom.fr> wrote: >Hi >I tried to create a hard macro for Virtex with the FPGA editor. >I loaded the design and chose "Save as macro". It crashed, saying "too >many routes in macro" >I didn't find anything in the Xilinx Answer DataBase. >If someone has an idea to help me create this macro... >Thanks in advance >-- >Nicolas MATRINGE DotCom S.A. >Conception electronique 16 rue du Moulin des Bruyeres >Tel 00 33 1 46 67 51 11 92400 COURBEVOIE >Fax 00 33 1 46 67 51 01 FRANCE We've been doing a design recently with several hard macros in Virtex and had untold problems with the tools. Our findings were as follows. First of all make sure you are using the very latest tool versions, along with the newest service packs (M2.1i with SP3 at last count). The other thing we discovered is that putting routing in the hard macro was counterproductive in that it made the tools take much longer to do place and route if the macro included internal routing. Our macros were single CLB slices, so the amount of internal routing was quite small, and we just brought it out and did it in the VHDL after instantiation. In the end we gave up on hard macros, and reverted to instantiating primitives in the VHDl, and attaching RLOC and HBLKNM attributes to ensure that the right bits went in the right CLB slices. The net result was a massive speed up in place and route time (the hard macro MAP time was over an hour, the "soft" macro MAP time is a few minutes!), plus we avoid the flakiness of the software. Our conclusion....only use hard macros if you have no alternative. Nobody else seems to use them, so the software is relatively untested (by the masses). The best bet is to go for primitive instantiation in HDL or maybe better still schematics. Hope that helps! Best Regards Graeme Durant HELION Technology Limited Cambridge, UK ~~~~~~~~~~~~~~~~~~~ XILINX XPERT Consultancy.Article: 19329
I e-mailed Marc to check that the problem was what I thought it was, and he has confirmed that my suggested fix works. Here it is: "Oh for the joys of stupid synthesisers :o) I suggest that you define what happens when an if statement is not satisfied I.E. always have an "else". I suspect that a "safe" one-hot synthesis algorithm will default the one-hot state signal as low. " Actually, I would always include an "else" in an "if" statement. Otherwise some synthesiser, somewhere is going to get the wrong default, or infer a latch. Hope that helps Regards Chris Squires David Murray <dmurray@iol.ie> wrote > Hi Micheal, > I would never say 'never' where synthesis is concerned :)!!. I'm > quoting from past experience where this problem was passed by synthesis and > led to a functional error. (As far as I remember it was with a Xilinx 52xx > device and this was a few years ago, so the synthesis may not have been as > robust) . I would assume that todays synthesis tools are more robust but > then again... never assume! Again, this may not be the problem with Marc's > design, but I would be interested in finding out what is. > >Article: 19330
I wanted to make some more tests before posting back to the group but
Chris's "fix" works quite well.
I added "else" to every state in the state machine like this:
when InAddrRead =>
if nAddrStb = '1' then
State <= Waiting;
else
State <= InAddrRead;
end if;
It's quite sad that some synthesisers clear the current state when not asked
to.
Anyway thanks to Chris and the others that responded. This one was hard to
find...
Marc Battyani
Chris Squires <chris@highwater.co.uk> wrote in message
news:945189968.21220.0.nnrp-07.9e98383a@news.demon.co.uk...
> I e-mailed Marc to check that the problem was what I thought it was, and
he
> has confirmed that my suggested fix works. Here it is:
>
> "Oh for the joys of stupid synthesisers :o)
>
> I suggest that you define what happens when an if statement is not
> satisfied I.E. always have an "else". I suspect that a "safe" one-hot
> synthesis algorithm will default the one-hot state signal as low.
> "
>
> Actually, I would always include an "else" in an "if" statement. Otherwise
> some synthesiser, somewhere is going to get the wrong default, or infer a
> latch.
>
> Hope that helps
> Regards
> Chris Squires
Article: 19331
When I tried to do Verilog post-P&R timing simulation,
I found that the name of the internal buses has all been changed
into separate individual nets with numbers appended; unaccessable
to my original functional testbench. Locating all the nets and
grouping them into a bus in the testbench would be very time
consuming, is there a more effective way to probe the internal
signals? Thanks.
Oliver
Article: 19332In article <3853C64C.66C023B7@ids.net>, Ray Andraka <randraka@ids.net> wrote: > For the ultimate in security, you can use a battery backed an SRAM based FPGA > that is loaded during manufacture. There is no copy of the bitstream anywhere > in the product other than in the FPGA and if you remove power it is gone without > a trace. It works well for things like military gear that can be reloaded > periodically in a secure environment. > It seems me a great idea. But I looked up the Xilinx data book and I found no information about preventing the bitstream backread operation in SRAM-based FPGAs. It Is actually possible preventing this in some device? Luigi Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19333
Daryl Bradley <dwb105@nospam.ohm.york.ac.uk> wrote: [snip 3 VCC boards] : We have just ordered a PCI based XCV1000 board form embedded solutions - : have heard this is pretty good but no hands on experience yet Embedded Solutions' RC1000-PP board - suitable for Virtex: http://www.embeddedsol.com/tech_info_3.htm Embedded Solutions' "Special Offer to universities": http://www.embeddedsol.com/programs/academic/uni_offer.htm ``In partnership with the Xilinx University Program, Xilinx are supplying a limited number of the Virtex XCV1000 parts free of charge as a donation for suitable teaching/research projects. ESL is mounting these devices on the RC1000-PP reconfigurable computing PCI board enabling this top end version of the RC1000-PP to be offered at a very substantial discount on the standard university discounted price.'' -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com It is a miracle whenever curiosity survives a formal education.Article: 19334
Chameleon Systems is a well-funded privately held fabless
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markets. Headquartered in Silicon Valley, the company is developing the
industry's first reconfigurable communications processor platform - an
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high-performance embedded telecom and datacom applications. The
field-reconfigurable solution allows data and telecom equipment vendors
to create their own customized communications processors to more quickly
adapt to new requirements and standards, reduce time-to-market, lower
development costs and reduce risk.
We're looking for Systems Engineering candidates for the following
positions:
Member of Technical Staff - Communication System Design
System Engineering investigates the value of Chameleon technology in the
various
Communications marketplaces, and develops algorithmic intellectual
property for customers' use. You will interact with customers to
understand their requirements in signal processing and protocols,
supplementing your own
knowledge of communications hardware and algorithms. As part of a team,
you will map and guide implementation of key various DSP kernels in
Chameleon's technology, and evaluate the benefits of reconfigurable
communications processors over other technologies. The hardware and
software engineering teams will
benefit from your advice concerning tool and architecture evolution.
This position requires an in-depth knowledge of system and algorithm
requirements in one or more of the wireline and wireless communication
markets. Experience in hardware architectures with a DSP and/or FPGA
programming background is required. Excellent
interpersonal skills are necessary. Electrical engineering or computer
science Bachelors' degree plus five years' industrial or further
academic experience is required.
Member of Technical Staff - Intellectual Property Development
System engineering investigates the value of Chameleon technology in the
various Communications marketplaces, and develops algorithmic
intellectual property for customers' use. As part of a team, you will
build
Chameleon's intellectual property at various levels of algorithm
integration -- building blocks, signal processing kernels and
application-level functions. You will learn and use Chameleon's unique
design toolkit that translates C and HDL code to a bitstream that
configures the processor in software. The hardware and software
engineering
teams will benefit from your advice concerning tool and architecture
evolution. Familiarity with algorithms in one or more of the wireline
and wireless communication markets is preferred. Extensive experience
with DSP programming and/or FPGA design/emulation is required, at C,
Verilog/VHDL and/or assembly level. Electrical
engineering or computer science Bachelors' degree plus five years'
industrial or further academic experience is required.
TO APPLY
Email, fax or mail your resume to us.
Apply by Email:
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Chameleon Systems, Inc. is an equal
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employer.
Article: 19335You need to put the readback primitive in your design in order to read back the data. If you don't put it in, you can't read back. luigi_funes@my-deja.com wrote: > In article <3853C64C.66C023B7@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > For the ultimate in security, you can use a > battery backed an SRAM based FPGA > > that is loaded during manufacture. There is no > copy of the bitstream anywhere > > in the product other than in the FPGA and if > you remove power it is gone without > > a trace. It works well for things like > military gear that can be reloaded > > periodically in a secure environment. > > > > It seems me a great idea. But I looked up the > Xilinx > data book and I found no information about > preventing > the bitstream backread operation in SRAM-based > FPGAs. > It Is actually possible preventing this in some > device? > > Luigi > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19336
I was able to get a hold of a printed copy from our Avnet Representative. I don't have an electronic copy. Try contacting your Avnet FAE. In article <833r6v$96h$1@vixen.cso.uiuc.edu>, jeffrey j cook <jjcook@staff2.cso.uiuc.edu> wrote: > Does anyone know when the VirtexE series will be available? I haven't > been able to find any dates on their website. > > If they are already available, who has them (avnet doesn't)? > > Thanks. > -- > Jeffrey J. Cook > University of Illinois Computer Engineering Student > jjcook@uiuc.edu > > "Sometimes the easiest way to get something done is to be a little naïve > about it -- and just ship it." > Bill Joy, Sun Microsystems - Jini Engineer > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19337
Everbody in my company is using the NTEmacs with VHDL Mode. It's free, highly customizable, and has a lot of shortcuts built in. It's a little tough to set up at first, but once its going we love it. http://emacs.org/hdl/vhdl-mode.html http://www.cs.washington.edu/homes/voelker/ntemacs.html Joe Kulak In article <81ltfs$l59$1@sun27.hrz.tu-darmstadt.de>, "Ahmad A." <aa939788@oak.cats.ohiou.edu> wrote: > Hi.. > Can any one tell me where can I find Free, Student edition, or Shareware HDL > editor? > > Thank you in advanced. > Ahmad. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19338
We are running Foundation2.1i on a PC w/ service pack#3.
We coded the ROM in our VHDL as shown in XAPP-130.
This compiles and goes through place and route fine.
However, in the logic simulator(that comes w/ Foundation) , the
ROM always inits to all 0's( it does not get the init info from the
VHDL).
We have to enter the ROM contents by hand which works in the
simulator. But, if I knew the format of the MIF file I could generate
the file automatically.
Information on the MIF format is not on the Xilinx web page.
Does anyone know the format for MIF?
thanks,
Steve Martindell
s-martindell@_nospamm_ti.com
Article: 19339Depends on the device you are looking for. I believe the XCV2000E is sampling now. What device are you looking for? jeffrey j cook a écrit : > Does anyone know when the VirtexE series will be available? I haven't > been able to find any dates on their website. > > If they are already available, who has them (avnet doesn't)? > > Thanks. > -- > Jeffrey J. Cook > University of Illinois Computer Engineering Student > jjcook@uiuc.edu > > "Sometimes the easiest way to get something done is to be a little naïve > about it -- and just ship it." > Bill Joy, Sun Microsystems - Jini EngineerArticle: 19340
> > Anyway, some things to be careful of when you synthesis your One hot encoded > FSM's. During reset, your state register should look something like "00001" > and some FPGAs (although rarer these days) can only have a single global set > or reset which means that a '1' hot encoded state machine cannot be > synthesized to these type of devices. That's not true. You can use 'one hot encoding' in any device. The first state needs to be 'active', and you do this by making it active low.Article: 19341
> > when InAddrRead => > if nAddrStb = '1' then > State <= Waiting; > else > State <= InAddrRead; > end if; > > It's quite sad that some synthesisers clear the current state when not asked > to. I believe this 'else' is required by VHDL isn't it? Does someone know differently? Does the VHDL language state (clearly) that is will maintain state if no condition in the state is met? If so, any reference to that? I've been doing VHDL/Verilog/Abel for years, and never though NOT to be explicit about this...hum.Article: 19342
I've always used the "Current State," "Next State" methodology when doing
state machines in VHDL. I don't know what is more correct, but with this
example I might write something like:
<snip>
type State is (Waiting, StartDataRead, InDataRead);
signal CurrentState,NextState : State;
begin
NS : process (CurrentState,Reset,DataStb,Write)
begin
case CurrentState is
when Waiting =>
if DataStb = '0' then
if Write = '1' then
NextState <= StartDataRead;
else
NextState <= Waiting;
end if;
end if;
when StartDataRead =>
NextState <= InDataRead;
when InDataRead =>
if DataStb = '1' then
NextState <= Waiting;
else
NextState <= InDataRead;
end if;
when others =>
NextState <= Waiting;
end case;
end process NS;
CS : process (Clock, Reset)
begin
if (Reset = '1') then
CurrentState <= Waiting;
elsif (Clock'event and Clock='1') then
CurrentState <= NextState;
end if;
end process CS;
</snip>
I don't know really which is better (if either) ...
Another thing I've noticed between binary and one hot encoding is a problem
I had on a Xilinx Spartan part (xcs30vq100-3) ... I was encoding my state
machines one hot and in one particular state machine I wasn't explicitely
running in a reset to set the machine to some other state, but I did have an
else clause in my case statement which put me in my initial state... I was
using the fastest encoding and the kicker is that the synthesis tools were
synthesizing all my flops to reset ("0") which encoded one hot isn't a valid
state... furthermore, there was no transition out of this state eventhough
I provided an else clause in the case statement... my state machine would
just stick in the invalid state after startup and do nothing... ...took me
awhile to figure this out (especially since I was relatively new to VHDL at
the time) after compiling binary once and the damn thing working... The
solution was simple at the time and I always explicitely define a reset
state now...
l8r
m
Matt Billenstein
http://w3.one.net/~mbillens/
mbillens@one.net
"Marc Battyani" <Marc_Battyani@csi.com> wrote in message
news:062E9EEFDD659520.D67674846BD251B1.A017E921C8876561@lp.airnews.net...
| I don't understand why the following state machine is ok when I use binary
| state encoding (with safest mode) but oscillate when I use one hot
encoding
| (with safest mode also).
|
| type State is (Waiting, StartDataRead, InDataRead);
| signal S : State;
| begin
| SM : process (Clock, Reset)
| begin
| if (Reset = '1') then
| State <= Waiting;
| elsif rising_edge(Clock) then
| case State is
| when Waiting =>
| if DataStb = '0' then
| if Write = '1' then
| State <= StartDataRead;
| end if;
| end if;
| when StartDataRead =>
| State <= EppInDataRead;
| when InDataRead =>
| if DataStb = '1' then
| State <= Waiting;
| end if;
| when others =>
| State <= EppWaiting;
| end case;
| end if;
| end process SM;
|
| The compiler is VHDL express, for a Spartan xcs40.
| Any idea ?
|
| Thanks
| Marc Battyani
|
|
Article: 19343Just put a default "NextState <= PresentState" type of assignment before the case statement. Austin Franklin wrote: > > > > > when InAddrRead => > > if nAddrStb = '1' then > > State <= Waiting; > > else > > State <= InAddrRead; > > end if; > > > > It's quite sad that some synthesisers clear the current state when not > asked > > to. > > I believe this 'else' is required by VHDL isn't it? Does someone know > differently? Does the VHDL language state (clearly) that is will maintain > state if no condition in the state is met? If so, any reference to that? > > I've been doing VHDL/Verilog/Abel for years, and never though NOT to be > explicit about this...hum. -- -------------------------- -- -- Robert Sefton -- Senior Design Engineer -- -- CoSine Communications -- 1200 Bridge Parkway -- Redwood City, CA 94065 -- -- Direct: 650.637.2441 -- Main: 650.637.4777 -- Fax: 650.637.2412 -- --------------------------Article: 19344
Well I'm looking for the XCV50E,150E or 300E. This is simply for a small project and I only require about 24-48 of them. Isabelle Gonthier <igonthier@vif.com> wrote: : Depends on the device you are looking for. I believe the XCV2000E is : sampling now. What device are you looking for? : jeffrey j cook a écrit : :> Does anyone know when the VirtexE series will be available? I haven't :> been able to find any dates on their website. :> :> If they are already available, who has them (avnet doesn't)? :> :> Thanks. :> -- :> Jeffrey J. Cook :> University of Illinois Computer Engineering Student :> jjcook@uiuc.edu :> :> "Sometimes the easiest way to get something done is to be a little naïve :> about it -- and just ship it." :> Bill Joy, Sun Microsystems - Jini Engineer -- Jeffrey J. Cook University of Illinois Computer Engineering Student jjcook@uiuc.edu "Sometimes the easiest way to get something done is to be a little naïve about it -- and just ship it." Bill Joy, Sun Microsystems - Jini EngineerArticle: 19345
If you don't assign a new value to the signal, then it shouldn't change. Simulation and synthesis are suppose to match for this sort of thing. Austin Franklin wrote: > > > > when InAddrRead => > > if nAddrStb = '1' then > > State <= Waiting; > > else > > State <= InAddrRead; > > end if; > > > > It's quite sad that some synthesisers clear the current state when not > asked > > to. > > I believe this 'else' is required by VHDL isn't it? Does someone know > differently? Does the VHDL language state (clearly) that is will maintain > state if no condition in the state is met? If so, any reference to that? > > I've been doing VHDL/Verilog/Abel for years, and never though NOT to be > explicit about this...hum.Article: 19346
Steve Martindell wrote: > Information on the MIF format is not on the Xilinx web page. > Does anyone know the format for MIF? Hi I don't remember where I found the format but I found it somewhere in Xilinx doc... The MIF is just a text file with one value per line. You can write your values in hex or binary (watch out! COREgen only accepts binary. See a previous post) Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 19347
Austin Franklin wrote: > I believe this 'else' is required by VHDL isn't it? > Does someone know differently? No it isn't required by VHDL, and is fine when used in testbenches or non-synthesisable models. > Does the VHDL language state (clearly) that is will maintain > state if no condition in the state is met? If so, any reference to that? That's the difference between the requirements of VHDL, and the requirements of the synthesiser! My experience is that if you don't define what happens to ALL signals under ALL conditions of "if" "case" etc, some synthesiser, somewhere will produce something that you didn't intend. Thus, to ensure code portability, and possibly ease of maintenance, always define everything. I know that such synthesisers are, arguably, not fully compliant, but that's the real world for you! > I've been doing VHDL/Verilog/Abel for years, and never though NOT to be > explicit about this...hum. Same here, but I've had to maintain and reuse large chunks of code where assignments weren't all explicit. It wasn't nice :o) -- Regards Chris SquiresArticle: 19348
Nigel Orr wrote: > > Leon Heller wrote: >> >> Get the Xilinx starter kit. It comes with a JTAG programmer, >> a little CPLD evaluation board, and software that supports >> the CPLDs and the Spartan series of FPGAs, as well as the >> older devices. It's about $100. > > Is that the same one as: > <http://www.microcall.memec.com/xilinx/promo.htm> - £60 in the UK? > > I'm considering it as an FPGA starter kit- anyone had any > experience with it? Any time or feature limitations I should > be aware of? I know it doesn't have VHDL./Verilog. Note that the kit is for CPLDs (XC9500 series), not FPGAs. I'm not sure anybody does an FPGA starter kit? Mainly because the timing of FPGA designs is much more complex than for CPLDs, and most of the time you want/need a proper post-layout timing simulator tool. For the same reason, the place/route tools are more complex - unless they ignore timing constraints, in which case the design might not work! I think PLDs are a great introduction to programmable logic, and CPLDs are possibly the way into PLDs now that in-system programmability is the norm there (but not on PLDs like the 16V8 and 22V10). isp saves buying a programmer, and means you don't keep taking the chip out of your breadboard to re-program it. Increasingly, FPGAs are isp-capable, often using a JTAG port for the purpose. An alternative CPLD starter kit is the Vantis MACH one from Lattice <http://www.latticesemi.com/products/destools/mstarter.html>, this isn't the same as (nor is the software compatible with) the same company's Lattice ispGAL starter kit <http://www.latticesemi.com/products/destools/ispstarter.html>, although Vantis used to provide a free version of ABEL (the language used for the ispGAL kit) for their PLDs. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 19349
On 15 Dec 1999 02:39:31 GMT, in comp.lang.vhdl Austin Franklin <austin@da88rkroom.com> wrote in article <01bf46a5$8fb4eb50$207079c0@drt1>: >> when InAddrRead => >> if nAddrStb = '1' then >> State <= Waiting; >> else >> State <= InAddrRead; >> end if; >> >> It's quite sad that some synthesisers clear the current state when not > asked >> to. > I believe this 'else' is required by VHDL isn't it? Does someone > know differently? Does the VHDL language state (clearly) that is > will maintain state if no condition in the state is met? If so, any > reference to that? The "else" clause of if statements is optional; see the LRM for syntax and semantics. Paul -- Paul Menchini | mench@mench.com |"The last thing I want to do is Cadence Design Systems | www.orcad.com | spread fear, uncertainty and P.O. Box 71767 | 919-479-1670[v] | doubt in the users' minds." Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product Mgr
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