Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I am new to FPGA design and especially to Xilinx EDK. How does the HWICAP module (on Virtex-II and Virtex-II Pro) accesses its BRAM? Do I have to assign BRAM to my design (with EDK) or is the HWICAP module connected to a dedicated BRAM-block implicitly? Thanks for your help :) ChrisArticle: 82051
"Christoph Lauer" <eem@rommel.stw.uni-erlangen.de> schrieb im Newsbeitrag news:3bhpdjF6bav1kU1@news.dfncis.de... > Hi, > > I am new to FPGA design and especially to Xilinx EDK. How does the > HWICAP module (on Virtex-II and Virtex-II Pro) accesses its BRAM? Do I > have to assign BRAM to my design (with EDK) or is the HWICAP module > connected to a dedicated BRAM-block implicitly? > Thanks for your help :) > > Chris > none of the above (not directly) HWICAP provides the access to ICAP primitive that again allows full access to the configuration interface. Those you can read write the config bit (including BRAMs). There is no need (and no possible) to connect the BRAMs to HWICAP, the ICAP can access all the FPGA configuration data anyway. AnttiArticle: 82052
In article <1bhdikbazp.fsf@cs.nmsu.edu>, Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: |> "Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes: |> > |> > The basis of the patent is the "ARM Ltd discovery" that less code is better |> > than more code. |> > Code compression for RISC is mentioned already in the original RISC paper by |> > Katevenis. |> |> Original RISC paper by Katevenis? While I was able to find a 1983 |> paper by him, near as I can tell the original RISC paper is still the |> one by Patterson amd Ditzel in 1980. There were papers containing much of the technical content in the 1960s. Regards, Nick Maclaren.Article: 82053
Ulf Samuelsson <ulf@NOSPAMatmel.com> wrote: +--------------- | I happen to think that the ARM Thumb patent is a load of rubbish. +--------------- Yup. See my previous posting about the LINC/LINC-8/PDP-12 machines... -Rob ----- Rob Warnock <rpw3@rpw3.org> 627 26th Avenue <URL:http://rpw3.org/> San Mateo, CA 94403 (650)572-2607Article: 82054
On Tue, 05 Apr 2005 09:36:12 -0700, JJ wrote:
> I'd have to vote with John_H here but I know many won't.
>
> wire [3:0] row = 1<<address; // about as good as it gets
>
> When I see code that describes an obvious TTL nobrainer structure
> using more than a few lines of code I start to wonder, are we boosting
> line count or being succinct.
>
> If it can be done in a few chars or 1 line why use any more.
>
> Even more so giving every minor structure it own always begin .. end or
> assign {} when a lot of related assignments can be bumped into 1 larger
> always / assign cluster for the overall function. Same as putting tiny
> pieces of related logic on separate schematics sheets.
>
> We dont usually see C programs with a set of {} around each and every
> statement, only logically related code blocks. Same as over (())
> expressions, my C VC6 compiler always nags me because it assume I can't
> remember precedence rules for <<& bit extracting so I have to put in
> more () than I need to keep warnings down.
>
I'd say that a compiler that warns about unnecessary parenthesis in
expressions with bit manipulation is broken. It is far more helpful for
the compiler to warn about not having enough parenthesis to make the
meaning clear - gcc does this, with appropriate flags.
Code should be written to be easily read and easily understood - not to be
typed with the minimal number of characters. When C was first used,
minimal character count was a priority - and the results of that language
design decision have been felt ever since. Writing long-winded or
excessively commented code is just as bad as overly terse and compact
code, however.
Article: 82055Try this tutorial, it give you a Basic understand http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rg_cust_periphArticle: 82056
At first you imlement your Core to IPIF User Logic, then you must reimport you Core with Creat/Import Wizard. And by reimporting you must take no PAO file but a PRJ File from your IPIF Topdesign!Article: 82057
Good morning, I'm a beginner with FPGA. I've recently built a simple board with one Spartan 3 FPGA, no configuration PROM (I haven't it now), a power supply, and a JTAG connector. I've connected the FPGA for use only the JPAG port (M0-M1-M2=1-0-1). But when I start iMPACT for configure the FPGA, it see an "UNKNOWN" device. And if I try to get the device ID I get this error. Validating chain... Boundary-scan chain validated successfully. ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000100000000011 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011 I've checked the circuit and the connections, but all seems to be ok. Is this a common problem? What can be wrong??? Another question : if I put the device in JTAG configuration mode, how I must connect PROG_B and INIT_B? I think the first one must be connected to GND, and the other to +2.5V through a pull-up is it right? Thanks. EnzoArticle: 82058
"Enzo B." <enzo_br@virgilio.it> schrieb im Newsbeitrag news:efQ4e.742956$b5.33440532@news3.tin.it... > Good morning, I'm a beginner with FPGA. I've recently built a simple board > with one Spartan 3 FPGA, no configuration PROM (I haven't it now), a power > supply, and a JTAG connector. > I've connected the FPGA for use only the JPAG port (M0-M1-M2=1-0-1). > But when I start iMPACT for configure the FPGA, it see an "UNKNOWN" device. > And if I try to get the device ID I get this error. > > Validating chain... > Boundary-scan chain validated successfully. > ERROR:iMPACT:583 - '1': The idcode read from the device does not match the > idcode in the bsdl File. > INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000100000000011 > INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011 > > > I've checked the circuit and the connections, but all seems to be ok. Is > this a common problem? What can be wrong??? > > Another question : if I put the device in JTAG configuration mode, how I > must connect PROG_B and INIT_B? I think the first one must be connected to > GND, and the other to +2.5V through a pull-up is it right? > > Thanks. > > Enzo 1 the M0,M1,M2 no need to connect at all, the JTAG is enabled anyway 2 PROG_B doesnt matter as long as you try to identify the chain, however configuration over JTAG may fail if there is no pullup on PROG_B 3 INIT_B pullup everything else doesnt matter if you have xilinx cable III or IV then you can use http://gforge.openchip.org/projects/fpgafreqmeter/ to see if that application can detect the jtag correctly and there is JTAG chain debugger in the impact anttiArticle: 82059
nmm1@cus.cam.ac.uk (Nick Maclaren) writes: > In article <1bhdikbazp.fsf@cs.nmsu.edu>, > Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: > |> "Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes: > |> > > |> > The basis of the patent is the "ARM Ltd discovery" that less code is better > |> > than more code. > |> > Code compression for RISC is mentioned already in the original RISC paper by > |> > Katevenis. > |> > |> Original RISC paper by Katevenis? While I was able to find a 1983 > |> paper by him, near as I can tell the original RISC paper is still the > |> one by Patterson amd Ditzel in 1980. > > There were papers containing much of the technical content in the > 1960s. Of course. But the one that tied it all together in a single, coherent bundle was Patterson and Ditzel. -- Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605 Department of Computer Science FAX -- (505) 646-1002 New Mexico State University http://www.cs.nmsu.edu/~pfeifferArticle: 82060
On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio
<tauno.voipio@iki.fi.NOSPAM.invalid> wrote:
[...]
>
>There is a case of this years ago: The Zilog Z80
>used the Intel 8080/8085 instruction set and extended
>it, but used different mnemonics for nearly all
>instructions.
Similar case with the NEC V20/Intel 8088
Regards,
-=Dave
--
Change is inevitable, progress is not.
Article: 82061Mark & Dave - 1) INIT is not pulled low at the end - it does not indicate any error. It *does* wiggle as expected at the start of the programming sequence. 2) CS is pulled low, the WR signal is attached to a control signal and appears to be acting properly. 3) CCLK appears (using a scope) to be fine. D[7:0] show ample setup and hold time to BOTH edges of the clock. 4) I've tried sending extra 0xFF bytes at the end of the .bit stream, it doesn't help. I've also tried at the start of the stream. I'll keep debugging and let people know wht I find. I wonder if it's reasonably possible for an FPGA to die in a manner where JTAG download works, normal operation works, but Select Map download fails. Thanks for the help, I'll keep pulling my hair out. John PArticle: 82062
Please mention a tool that can accepts VHDL code and converts it into a circuit schematic(preferably at the register transfer level or gate level). Does ORCAD have such an option?Article: 82063
Hi All, I was wondering is there any way to synthesis a design of mine on an FPGA using the ISE tool so that I can get results for area speed, xpower and such. It is a partial prooduct summation tree that adds 13 12-bit numbers in a weighted manner. The tool tries to assign its input and output ports to pins and i get a worning to say that more than 100% of the device is used up even though it only uses 8% of the gates. I was wondering is there a way to unbond the ports from the pins. I was thinking just box it up and buffer it but not sure. Thanks KeithArticle: 82064
Brendan Cullen wrote:
>Hi,
>
>
>If you're targeting V4 then you are targeting one of our SX or LX devices
>and you are using 7.1.01i.
>
>
>
not necessarily. I'm targeting an SX55 and using 6.3sp3.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 82065
Martin Thompson wrote:
>Ray Andraka <ray@andraka.com> writes:
>
>
>
>>Karl wrote:
>>
>>
>>
>>>Here is a solution for your noise,
>>>
>>>http://www.zalman.co.kr/eng/product/view.asp?idx=151&code=020
>>>
>>>The cost could not be the issue if you start using Altera devices :-)
>>>
>>>
>>>
>>>
>>that doesn't address the disk drive noise. 15000 rpm SCSI drives are
>>pretty noisy.
>>
>>
>>
>
>Do you need a 15k rpm drive for this sort of work? If you're swapping
>you need more RAM, surely? The reading of files from the disk has not
>been a bottleneck in my experience, although I'm not targetting the
>very biggest devices out there...
>
>My Barracuda is almost silent, even in standard mountings - its the
>PSU fan that annoys me now!
>
>Cheers,
>Martin
>
>
>
I did when I bought that system. file I/O was a bottleneck at the time,
at least in simulation and PAR. I haven't evaluated it recently, but
will be later this year when I upgrade systems once again.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 82066In article <CvC4e.13846$Tn.9577@lakeread06>, Ray Andraka wrote: > > Right you are. Without the source, it is usually easier to start with a > clean sheet and design to the specifications. Having a device with the > original design in it but no source is only good for verifying the > design and perhaps for extracting the specification. I've been down > this road more than once, usually on legacy FPGA designs that no longer > have source and either need a "minor change" or need to be migrated to a > newer device family. If I had specifications, I'd not waste my time on trying to reverse engineer the ASIC. :-) -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 82067
Ulf Samuelsson wrote: > You protect an ISA by patenting some special thing which is required to > implement the ISA. > I happen to think that the ARM Thumb patent is a load of rubbish. > The basis of the patent is the "ARM Ltd discovery" that less code is better > than more code. > Code compression for RISC is mentioned already in the original RISC paper by > Katevenis. I note that the Itanium ISA is covered by a patent on its unique method of explicitly indicating parallelism. The more conventional way of indicating parallelism, by a 'parallel' bit on each instruction, was used on TI signal processing chips. I'm sad to hear that there is a patent on the ARM Thumb instruction set that extends to the general principle, because something like it is what the PowerPC architecture desperately needs - so that people can use it the way IBM wants, without compromising the architecture. John SavardArticle: 82068
Tauno Voipio wrote: > There is a case of this years ago: The Zilog Z80 > used the Intel 8080/8085 instruction set and extended > it, but used different mnemonics for nearly all > instructions. Note that this was because Intel *copyrighted* the mnemonics, rather than trademarking them, however. John SavardArticle: 82069
Hi Khansa, Mentor Graphics HDL designer has a code-to-graphics option (good for looking at the hierarchy), for gate level most synthesis tools (Synplify/Precision/Spectrum) have a RTL/Gatelevel schematic viewer. I am not sure about Orcad though, Hans. www.ht-lab.com "khansa" <khansaca@yahoo.co.in> wrote in message news:1f2e1ef.0504060739.597f1af3@posting.google.com... | Please mention a tool that can accepts VHDL code and converts it into | a circuit schematic(preferably at the register transfer level or gate | level). Does ORCAD have such an option?Article: 82070
Tobias Weingartner <weingart@cs.ualberta.ca> wrote: > In article <qhpsxanzti.fsf@ruckus.brouhaha.com>, Eric Smith wrote: > > > > But if there isn't a patent on an architecture, you don't need a license > > to implement it. The purpose of the license is to grant you a right that > > was taken away from the patent. If there's no patent, you haven't been > > denied the right. > > No, you are wrong. I do not need a patent on my IP in order for me to > license it to you. It's called copyright. > so precicely what do you claim is copyrightable in an ISA? instruction names? thats not even handled by the implementation. -- Sander +++ Out of cheese error +++Article: 82071
I add a library in my VHLD code(ISE 6.3) but the system tell me that "the library can't be found " ThanksArticle: 82072
Dave Hansen wrote: > On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio > <tauno.voipio@iki.fi.NOSPAM.invalid> wrote: > > [...] > >>There is a case of this years ago: The Zilog Z80 >>used the Intel 8080/8085 instruction set and extended >>it, but used different mnemonics for nearly all >>instructions. > > > Similar case with the NEC V20/Intel 8088 > Yep - the V20 contained the 8080 instruction set as well. I wrote a CP/M handler running on a PC/XT with V20. -- Tauno Voipio tauno voipio (at) iki fiArticle: 82073
Tauno Voipio <tauno.voipio@iki.fi.NOSPAM.invalid> writes: > Dan Koren wrote: > > "Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote > >> > >>Are ISA covered by patents or trademarks? Is it allowed to develop a > >>processor core for a popular ISA as long as no reference is made to any of > >>the original company trademarks? Many thanks for your comments. > > > > Trademarks cover only product *names*. > > > > ISA names can indeed be trademarked, > > hower that would not prevent anyone > > from copying/using the architecture. > > > > It would only prevent them from > > selling/promoting/advertising it > > under the same name as the original. > > There is a case of this years ago: The Zilog Z80 > used the Intel 8080/8085 instruction set and extended > it, but used different mnemonics for nearly all > instructions. It always puzzled me as to how Intel could get a copyright on instruction mnemonics. This struck me as being akin to someone copyrighting the Latin alphabet. An AND, is an AND, is an AND,...Article: 82074
Hi Neil, Thanx. We understood what ur suggesting but then the problem is both the JTAG ports are connected to the FPGA. We dont understnd the purpose of the 2nd JTAG port which is directly connected to the FPGA thro TMS, TCLK, TDI and TDO pins. Also the 1st JTAG port sends TMS, TCLK, TDI and TDO to the PROM and the PROM gives a Prog_b to the FPGA...which is what we are familiar with. Thanx again for ur reply and if u can think of some reason why there might be 2 JTAG ports shoot me a email. Regards, - Shailesh Neil Glenn Jacobson wrote: > I am not exactly sure what you are suggesting. Are you proposing that > there is one boundary-scan TAP connection that goes through the PROM to > the FPGA and another that goes directly to the FPGA without involving > the PROM? > > If that this the case, since there is in actuality only one physical TAP > on the FPGA, that means there will only be one set of TMS and TCK > connections which means that if you are trying to access the FPGA-only > TAP you will have the PROM traversing through its state machine and when > you try to shift data into the FPGA the PROM TDO will be active and > shifting, as well. > > I suppose you could add some extra control logic to guarantee safe > operation of the two TAPs but in the end, why would you? > > If you have a single chain of a PROM followed by an FPGA you can address > either device by BYPASSing the other. You can program the FPGA with a > bitstream file with the PROM in BYPASS or program the PROM with an mcs > or exo file with the FPGA in BYPASS. > > Does that help? > > > fpgavhdl@gmail.com wrote: > > Can an FPGA have two JTAG ports for programming an FPGA chip? > > > > One is conected thro XCf02s to the FPGA and the other is directly > > connected to the FPGA (XC3S400). > > > > What is the significance of having two ports? > > > > What files are used for programming this FPGA thro each of those ports? > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z