Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi group I'm redisigning a board containing a Altera Flex 10K device. As I'm adding other functions to the board, I am adding another FPGA. It would be convinient, to include the functions of the Flex into this newer, more powerfull device (probably an Altera Cyclone). Unfortunately I don't have the source code, but only the contents of the configuration prom. Have anyone in this group tried to reverse-assemble Flex-code to VHDL? Which tools did you use? KrestenArticle: 52601
HI everyone oes somebody can give me where I can found details on end-around-carry function which is recommended for modulo (2^n)-1 conversion ? thanks for your inputs jacky -- Ce message a ete poste via la plateforme Web club-Internet.fr This message has been posted by the Web platform club-Internet.fr http://forums.club-internet.fr/Article: 52602
Wow... I havent seen or heard from Star Bridge in four years. Well, they're on slashdot, again. Will we ever see anything from them? Probably not. At 26 million dollars a pop, its not like we could afford it anyways. Still, some groovy technology. http://slashdot.org/articles/03/02/15/1629237.shtml?tid=126 FPGA systems designed to be reconfigured on the fly. Interesting, if vaporware. MattArticle: 52603
Hi, Im using a Virtex-E 600 FPGA, with an output connected to a DAC (working on straight binary) and an input connected to a ADC (using 2's complement). Thus, I get 2's complement data and I have to sent straight binary. I do the conversion allright,but my question is: What is the codification that I can use to operate data within the FPGA? Also I need to divide 2 variables (12bits) regularly, I used the divider in Coregen,but the PC hangs when I try it. Do you know any algorithm or another solution? Many thanks in advance.Article: 52605
doug_miller@spectrumsignal.com (DougMiller) wrote in message news:<c53f2641.0302140558.511e2b61@posting.google.com>... > Anyone have experience with using the Xilinx CORDIC v1.0 in atan mode? > Following is the behavior I've seen when using it. There is a newer > version (V1.1) which would require me to upgrade to newer (ISE 5.1) > software. So far, I haven't been able to get a confirmation that the > new version is fixed. Anyone know for sure?: > > CORDIC core version 1.0 has some unexplained behavior when used as an > atan function. For the following discussion, assume 16 bit > (rectangular) inputs and (phase - scaled radian) output, where each > number is given first as a decimal number followed by its binary > floating point representation in 1QN or 2QN format: > > X_IN Y_IN PHASE_OUT > -4100 (-0.25) 3900 (0.238) 30785 (3.75) > -4000 (-0.25) 4000 (0.244) 18432 (2.25) > 11900 (0.726) 12100 (0.739) 14358 (1.75) > 12000 (0.732) 12000 (0.732) 2048 (2.611) > > Ignoring the fact that the outputs often are greater than 1 (which can > easily be fixed by discarding the whole number part), it is obvious > that there are large discontinuities at certain points. I've found > that the following workaround equation gives a useful output: > > phase_out <= raw_phase_out(15) & > raw_phase_out(15) & > raw_phase_out(15) & > raw_phase_out(14) & > raw_phase_out(11 downto 0); > > While sign extending over bits 14 and 13 makes sense since these two > bits are the whole number part of the 2QN output format, replacing bit > 12 with bit 14 makes no sense at all. Is this a known problem in the > core? Will this workaround work for all inputs? > > Thanks, > Doug Miller Doug, I don't know about the Xilinx Cordic Core, but wanted to point out that there is also a free Cordic IP Core available through OpenCores and my company. It includes documentation and full source code. Best Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 52606
Hi, I downloaded Xilinx (ISE-WebPACK) on Win NT.But when i tried to install the package i got a message saying that it is not a file type supported by windows.I am a newbie to FPGA and i wanted to implement a few VHDl designs using Xilinx. Also is there any other free software that lets me do the same thing?Could anyone plz help me abt this? thanxArticle: 52607
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3E4A6E30.A13B2D8@xilinx.com>... > Rudy, > > It is sure amusing to read all of the conjectures..... Austin, please elaborate which part of my message where "conjectures" ? Sure I generalized things a bit and left out some details, but my description of interconnects is correct for at least one family of FPGAs (I was the architect for them). I have no doubt in my mind that your 12th generation FPGAs and all the experience your company has are state of the art devices. Never the less, you still have to follow basic rules of physics, and are more or less faced with the same trade offs I was faced some 15 years ago. Actually with the shrinking feature sizes your job today is probably much harder. Anyway, perhaps you can address the actual discussion at hand and explain why todays FPGA architectures would or would not be good targets for context switching. Your statement that they are already "million+" gates doesn't hold, as we, the users (following Micro$ofts trend) will use all the gates you will give us and make sure our designs are so complex that even the fastest FPGA looks like an old Z80 ! ;*) Cheers ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV ---- > Now that we are designing our 12th generation FPGA, we are able to control current quite well, > thank you. > > Note: that is 12 successful FPGA designs. You get pretty good at something when you work on > it for that long (and do some experimentation along the way). > > Virtex II and Virtex II Pro have no current surge on power ON, as we found what causes that, > and addressed it. > > As for multi-context FPGAs, they were simply killed by FPGAs with million+ "gates" (who needs > to switch?). As well, with partial reconfiguration in Virtex II and II Pro, you can at any > time reconfigure parts and pieces (with no current issue). > > Austin >Article: 52608
Hi, "Laura Faus" <laura.faus@uv.es> wrote in message news:<b2mcmo$tud$1@peque.uv.es>... > Hi, > > Im using a Virtex-E 600 FPGA, with an output connected to a DAC (working on > straight binary) and an input connected to a ADC (using 2's complement). > > Thus, I get 2's complement data and I have to sent straight binary. I do > the conversion allright,but my question is: > What is the codification that I can use to operate data within the FPGA? Whether it makes sense to use 2's complement or raw binary depends on what you wish to do with the data - you will need to specify that. > > Also I need to divide 2 variables (12bits) regularly, I used the divider in > Coregen,but the PC hangs when I try it. Do you know any algorithm or another > solution? An alternative is to use the divider core from Opencores (www.opencores.org) - you may need to modify it to make it suitable for Xilinx though. > > Many thanks in advance. cheers, ChrisArticle: 52609
Kiran <kpkiran@lycos.com> wrote: : Hi, : I downloaded Xilinx (ISE-WebPACK) on Win NT.But when i tried to : install the package i got a message saying that it is not a file type : supported by windows.I am a newbie to FPGA and i wanted to implement a : few VHDl designs using Xilinx. Also is there any other free software : that lets me do the same thing?Could anyone plz help me abt this? What's the exact error message? Do you use a recent wine? Did you follow the advice about native stdole*.tlb? Do a deja search about those subjects, if those problems don't tell you something at the moment. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52610
Hello, I want to compile the VHDL model of a IDT fifo memory (I found it on www.eda.org/fmf), but the Xilinx WebPack 5.1 produces only the following messages: ERROR:HDLParsers:3014 - L:/Sonstiges/Entwicklung/FPGA/FreeModelFoundry/Fifo/WebPack/idt/../../VHDL-Code/library_fmf/gen_utils.vhd Line 22. Library unit vital_primitives is not available in library ieee. Is there a possibility to compile such vhdl module? Thank you for your answer bye martin sauerArticle: 52611
Hello, I would like to use USER1/USER2 JTAG mechanism to communicate with my FPGA project, once configured for debugging or data loading. As it is a Xilinx Spartan II, I understand that I can use the BSCAN_SPARTAN2 component , refer to Xilinx appnotes 058/138/139. Then I should create an SVF file (cf appnote 503) and play it with Xilinx' playxsvf.exe. The mystery is even darker for the RDBK component that allows to view the state of a configured device... I have dug a lot on this newsgroup and on the Internet, and I found a lot of interesting information, but... no concrete examples showing an SVF file using USER1 instruction and a simple FPGA design instantiating BSCAN_SPARTAN2, and how to get the data back and forth. I am sure I am not the first newbie to ask the question. Could anyone please give me suggestions and/or examples? Thank you in advance for your help -- Frederic Bastenaire (fba@free.fr)Article: 52612
In article <c53f2641.0302140558.511e2b61@posting.google.com>,
DougMiller <doug_miller@spectrumsignal.com> wrote:
>Anyone have experience with using the Xilinx CORDIC v1.0 in atan mode?
>
We saw that the angles were wrong when using scaled radians (BAMS) mode.
In normal radians I think they were right (somebody else was working the
issues). That was fixed in 1.1. We were using X/Y to phase and magnitude
mode.
One of the other functions also gave strange results but we aren't using
it anymore so don't know if it was fixed.
If you are using the test bench software we found it almost unusable in
5.1 due to excessive memory usage (1GB).
If you wish to email me a project with testbench I should be able to run it
for you to see if it is fixed (if you don't get an answer before that).
With the snow I can't say when the roads will be clear enough to let me get
in to work.
David Gesswein
http://www.pdp8.net/ -- Run an old computer with blinkenlights
Have any PDP-8 stuff you're willing to part with?
Article: 52613If you downloaded ISE_WebPack 5.1, Xilinx web site claims it only supports Windows 2000 and XP. Jim "Kiran" <kpkiran@lycos.com> wrote in message news:a5f276e9.0302151939.691bed30@posting.google.com... > Hi, > I downloaded Xilinx (ISE-WebPACK) on Win NT.But when i tried to > install the package i got a message saying that it is not a file type > supported by windows.I am a newbie to FPGA and i wanted to implement a > few VHDl designs using Xilinx. Also is there any other free software > that lets me do the same thing?Could anyone plz help me abt this? > > thanxArticle: 52614
Jim <jimwu88NOOOSPAM@yahoo.com> wrote: : If you downloaded ISE_WebPack 5.1, Xilinx web site claims it only supports : Windows 2000 and XP. Wine supports the "Windows 2000 and XP" incarnation of the Win32 Api so much, that I have ISE_WebPack 5.1 running... Impact can't access the hardware however due to th D*ma*d windrv.sys VXD. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52617
If you only use the IDT fifo model for simulation, use ModelSim XE instead. Jim "Martin Sauer" <msauer@gmx.net> wrote in message news:3E4F84E9.9030008@gmx.net... > Hello, > > I want to compile the VHDL model of a IDT fifo memory (I found it on > www.eda.org/fmf), but the Xilinx WebPack 5.1 produces only the following > messages: > > ERROR:HDLParsers:3014 - > L:/Sonstiges/Entwicklung/FPGA/FreeModelFoundry/Fifo/WebPack/idt/../../VHDL-C ode/library_fmf/gen_utils.vhd > Line 22. Library unit vital_primitives is not available in library ieee. > > Is there a possibility to compile such vhdl module? > > Thank you for your answer > > bye > > martin sauer >Article: 52618
Hi there, I have a general question about programming FPGAs. I'm in the very early planning phase of a design. The system that I've been planning would basically connect a few small PCBs together through an Ethernet interface (on each PCB). Each PCB would also have an FPGA on it. Some of my early prototype designs have used CPLDs (which retain their configuration after power loss), and to program them, I manually connected my boards to a JTAG interface. (They were prototypes :) Now, with the amount and size of my logic, FPGAs are starting to make more sense, so I'm thinking of replacing the CPLDs with FPGAs. I really like the idea of having my boards automatically download bitfiles from a central server (over the ethernet connection) at device power-on. This would make bug fixes and feature enhancements a breeze. Has anyone here tried to setup their boards to automatically program over a network, and can you share any experiences? Any specific FPGAs, CPLDs, controllers, app notes, etc. that greatly simplified your life when you tried this? [I realize that there are a few immediate problems with my idea (e.g., I'd need to have a TCP/IP stack, etc), so I was thinking that I could use a ROM to "bootstrap" my FPGA, install an initial TCP/IP stack, have the FPGA seek the bitfile over the network, download the bitfile, and have external logic reprogram the device. This seems a little excessive, and was thinking that there must be a cleaner/faster/better/cheaper way ...] Regards, -krisArticle: 52619
I'm new to all this..... I've built my own parallel port to jtag interface using the Xilinx cct, and it appears to work OK. Using chain debug I can see signals going out on TCK, TDI, and TMS. But never anything coming back on TDO. WebPack 4.2 SP3 crashes on my system (kernel32.dll) so I got jtag programmer 3.3WP8.x. Now I get the following error msg on any function, Loading Boundary-Scan Description Language (BSDL) file 'xc9572.bsd'.....completed successfully. Checking boundary-scan chain integrity...done. Verifying device positions in boundary-scan chain... Verification completed. Boundary-scan chain validated successfully. ERROR:JTag - The boundary-scan based 'program' operation is not supported by the download software on the instance 'PLD2(Device1)'. These operations are currently supported only on Xilinx CPLD and FPGA devices. 'PLD2(Device1)': Programming terminated due to error. PLD2(.jed) is the file I'm trying to program into the device. Any help or pointers greatly appreciated as I'm really stuck. AmandaArticle: 52620
I am using XILINX ISE in implementing my VHDL design in FPGA and I simulate my design in Modelsim. The problem is the post map simulation is correct but the post PAR simulation is wrong. I really have no idea on how to remedy this problem. Please help. Thank you!Article: 52621
"Kris Vorwerk" <no@one.here.org> wrote in message news:<itT3a.236$sv3.87671@news20.bellglobal.com>... > Hi there, > > I have a general question about programming FPGAs. > > I'm in the very early planning phase of a design. The system that I've been > planning would basically connect a few small PCBs together through an > Ethernet interface (on each PCB). Each PCB would also have an FPGA on it. > Some of my early prototype designs have used CPLDs (which retain their > configuration after power loss), and to program them, I manually connected > my boards to a JTAG interface. (They were prototypes :) > > Now, with the amount and size of my logic, FPGAs are starting to make more > sense, so I'm thinking of replacing the CPLDs with FPGAs. I really like the > idea of having my boards automatically download bitfiles from a central > server (over the ethernet connection) at device power-on. This would make > bug fixes and feature enhancements a breeze. > > Has anyone here tried to setup their boards to automatically program over a > network, and can you share any experiences? Any specific FPGAs, CPLDs, > controllers, app notes, etc. that greatly simplified your life when you > tried this? > > [I realize that there are a few immediate problems with my idea (e.g., I'd > need to have a TCP/IP stack, etc), so I was thinking that I could use a ROM > to "bootstrap" my FPGA, install an initial TCP/IP stack, have the FPGA seek > the bitfile over the network, download the bitfile, and have external logic > reprogram the device. This seems a little excessive, and was thinking that > there must be a cleaner/faster/better/cheaper way ...] > > Regards, > -kris If your board has an independent CPU, you can use it to program the FPGA from a bitfile in boot ROM; of course, your CPU should be able to run, at least a little, without the FPGA (DON'T put your ROM CS logic in the FPGA - been there, done that, had to kick myself in the butt). After everything had been configured, the CPU can check the server for a newer version of the FPGA bitfile and save it in its ROM (flash, of course) for the next time. It can also reload the FPGA immediately if required (fix for a big bug). If your board doesn't have an independent CPU (for example, your CPU is inside the FPGA), you must use an automatic loader. The simplest loader is a serial-ROM chip designed specifically for your FPGA (each RAM-based FPGA has one; sadly, they are specific to each manufacturer, sometimes to one FPGA family). This is the easiest solution, but they are very expensive chips (flash-based are hideously expensive; OTP are merely expensive, and must be socketed). If you are converting from CPLDs, you probably won't like using a 20$ ROM (IIRC, those were the prices for a flash-based ROM) for a 3$ FPGA. Another solution is to use a standard parallel flash-ROM and a small CPLD to load the bitfile to the chip; both Altera and Xilix have app notes about how to do it. It requires more design effort and board space, but will probably be cheaper on the long run.Article: 52622
On Mon, 16 Feb 2003, ron wrote: > I am using XILINX ISE in implementing my VHDL design in FPGA and I > simulate my design in Modelsim. The problem is the post map simulation > is correct but the post PAR simulation is wrong. I really have no idea > on how to remedy this problem. Please help. Thank you! Does your design met the timing constraints after the place and route ? It may be that you get wrong results due to timing problems. However ModelSim should give you at least a warning. Greetings, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52623
Hi all I have a problem with the design of an SoC peripheral cell to be used in an SoC with AHB interface .I am new to this area.Any resource or advices regarding the design of an SoC peripheral Thanks in Advance Regards GeekoArticle: 52624
Hello, i'm drawing some waveforms to test my implementation. I need to draw within Xilinx HDL Bench an input signal that start AFTER a little time respect rising edge of the clock and not BEFORE rising edge. How can i set the program to do that ? Thanks a lot -- Stefano Mora email: stefano.mora@*libero.it (remove *)
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z