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Messages from 136550

Article: 136550
Subject: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
From: Eric Smith <eric@brouhaha.com>
Date: Fri, 21 Nov 2008 12:07:46 -0800
Links: << >>  << T >>  << A >>
Eric wrote:
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell? 
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.

It's very hard to tell, as there isn't any simple conversion factor
you can use.  You need one macrocell for each flip-flop, but if there
were a lot of "logic cells" being used for combinatorial logic, they
might take fewer macrocells because CPLD macrocells can implement
wider functions.  On the other hand, CPLDs tend to be less efficient
for combinatorial functions that have many terms when flattened into
sum-of-products form.

Article: 136551
Subject: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Fri, 21 Nov 2008 21:14:16 +0100
Links: << >>  << T >>  << A >>
Hi,

I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like 
to generate a sample rate that is not a integer of this clock and drive a 
DAC with this sample rate.

Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz.

This sample rate must be brought to the speed of the clock of DAC to 
generate it, by interpolating.

How to achieve ? It is possible ?

Thanks.

Kappa. 



Article: 136552
Subject: Accessing bottom MGT of Virtex II Pro FPGA
From: HSeldon <hseldon37@gmail.com>
Date: Fri, 21 Nov 2008 12:44:29 -0800 (PST)
Links: << >>  << T >>  << A >>
I'm working with a FF672 Virtex II Pro chip. I'm outputting a sequence
succesfully from one of the top RocketIO MGTs. To access this MGT, my
system.ucf code has the folowing line:

INST myip_plb_0/myip_plb_0/USER_LOGIC_I/GT_CUSTOM_INST     LOC =
GT_X1Y1;

NET BREF_CLK_P_pin     LOC = B14;    # BREFCLK (OSC)
NET BREF_CLK_N_pin     LOC = C14;    # BREFCLK (OSC)

To access the bottom MGT, I make the following changes to the code

INST myip_plb_0/myip_plb_0/USER_LOGIC_I/GT_CUSTOM_INST     LOC =
GT_X1Y0;

NET BREF_CLK_P_pin     LOC = AD14;    # BREFCLK (OSC)
NET BREF_CLK_N_pin     LOC = AE14;    # BREFCLK (OSC)

Everything else is the same, but after making these changes, I get no
output from the bottom RocketIO MGT. The DC level changes after
loading the bitstream onto the FPGA. Any ideas what I should should
look into to figure out why it doesn't work? Do I need to make any
other changes to access the bottom MGT?

I'm using a Virtex II Pro Evaluation Board Rev 3 by Memec/Avnet.

Article: 136553
Subject: Re: Generate sample rate ...
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Fri, 21 Nov 2008 14:56:03 -0600
Links: << >>  << T >>  << A >>
>I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like
>to generate a sample rate that is not a integer of this clock and drive a
>DAC with this sample rate.

>Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz.

>This sample rate must be brought to the speed of the clock of DAC to
>generate it, by interpolating.

>How to achieve ? It is possible ?

How much do you care about the quality of the signal your DAC
is generating?

If you want a clean signal, your best bet is to run the DAC off
a low jitter osc package.

You can make a signal that's close to 9.4 MHz, but it will have
some jitter.  Google for dds.  If you get close enough the
error in your source clock will be the major source of error.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136554
Subject: Re: Generate sample rate ...
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 21 Nov 2008 20:58:11 +0000
Links: << >>  << T >>  << A >>
On Fri, 21 Nov 2008 21:14:16 +0100, "Kappa" wrote:

>I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like 
>to generate a sample rate that is not a integer of this clock and drive a 
>DAC with this sample rate.
>
>Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz.
>
>This sample rate must be brought to the speed of the clock of DAC to 
>generate it, by interpolating.

Which FPGA?  Does it have PLLs or (Xilinx) DCMs?  If so
you can multiply your clock by M/N where M and N are integers;
of course there are limits both on the values of M and N,
and on the possible range of output frequencies, but with a
little creativity you can probably do what you need.
It's all in the data books, or alternatively you can 
learn a lot simply by running the IP-generator wizard.

Another choice is to find out about DDFS (Direct Digital 
Frequency Synthesis).  With this technique you can generate 
an output frequency with arbitrarily good precision, but 
the output will suffer jitter of up to one period of the 
input clock (140MHz, so about 7ns of jitter).

More advanced techniques for getting both high resolution
and low jitter have been discussed here at length in the past.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 136555
Subject: Re: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Fri, 21 Nov 2008 22:06:22 +0100
Links: << >>  << T >>  << A >>

Hi Hall Murray

> How much do you care about the quality of the signal your DAC
> is generating?

The signal must be good SFDR 60 dB or more.

> If you want a clean signal, your best bet is to run the DAC off
> a low jitter osc package.

Yes, 140 MHz is a OSC with low jitter.

> You can make a signal that's close to 9.4 MHz, but it will have
> some jitter.  Google for dds.  If you get close enough the
> error in your source clock will be the major source of error.

I should not generate an output signal of 9.4 MHz, are able to do this with 
a DDS, but clocking data at this speed.

Kappa.



Article: 136556
Subject: Re: Generate sample rate ...
From: Gabor <gabor@alacron.com>
Date: Fri, 21 Nov 2008 13:15:43 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 3:58=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 21 Nov 2008 21:14:16 +0100, "Kappa" wrote:
> >I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would li=
ke
> >to generate a sample rate that is not a integer of this clock and drive =
a
> >DAC with this sample rate.
>
> >Example: Clock 140 MHz --> Sample rate "66Mhz / 7" =3D 9.428571429 MHz.
>
> >This sample rate must be brought to the speed of the clock of DAC to
> >generate it, by interpolating.
>
> Which FPGA? =A0Does it have PLLs or (Xilinx) DCMs? =A0If so
> you can multiply your clock by M/N where M and N are integers;
> of course there are limits both on the values of M and N,
> and on the possible range of output frequencies, but with a
> little creativity you can probably do what you need.
> It's all in the data books, or alternatively you can
> learn a lot simply by running the IP-generator wizard.
>
> Another choice is to find out about DDFS (Direct Digital
> Frequency Synthesis). =A0With this technique you can generate
> an output frequency with arbitrarily good precision, but
> the output will suffer jitter of up to one period of the
> input clock (140MHz, so about 7ns of jitter).
>

If you have DDR output registers it's easy enough to
make a DDFS with 1/2 cycle jitter or 3.5ns

> More advanced techniques for getting both high resolution
> and low jitter have been discussed here at length in the past.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Article: 136557
Subject: Re: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Fri, 21 Nov 2008 22:21:24 +0100
Links: << >>  << T >>  << A >>
Hi Jonathan Bromkey,

> Which FPGA?

Xilinx FPGA Virtex-4 SX35

> Does it have PLLs or (Xilinx) DCMs ?

I have some DCM.

> If so you can multiply your clock by M/N where M and N are integers;
> of course there are limits both on the values of M and N,
> and on the possible range of output frequencies, but with a
> little creativity you can probably do what you need.
> It's all in the data books, or alternatively you can
> learn a lot simply by running the IP-generator wizard.

I am okay. But if I place a two DCM for example:

synthesis attribute CLKFX_MULTIPLY of DCM0 is 2
synthesis attribute CLKFX_DIVIDE of DCM0 is 11
synthesis attribute CLKFX_MULTIPLY of DCM1 is 10
synthesis attribute CLKFX_DIVIDE of DCM1 is 27

actual frequency generated is: 9.427609 MHz (Not exactly frequency)

This is OK.

Now I have to interpolate order to bring the data to the DAC but how ?

> Another choice is to find out about DDFS (Direct Digital
> Frequency Synthesis).  With this technique you can generate
> an output frequency with arbitrarily good precision, but
> the output will suffer jitter of up to one period of the
> input clock (140MHz, so about 7ns of jitter).

I am okay. But the signal is SQUARE WAVE ?

> More advanced techniques for getting both high resolution
> and low jitter have been discussed here at length in the past.

Perhaps I explained badly.

                                     Output
                                         |
                                         |
OSC (140 Mhz) --x--> DAC  <-- Sample rate data 9.4.... MHz <--FPGA
                              | 
|
                              | 
|
                              -----------------------------------------------------

The Sample Rate of 9.4.... MHz is a clock o data. If I put this data to DAC, 
what I get ? Not the signal that I expect.

Kappa.



Article: 136558
Subject: Small adders in XST?
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 21 Nov 2008 13:53:44 -0800 (PST)
Links: << >>  << T >>  << A >>
A bigger question for Jan Bruns may be:

  How does one coerce XST to use carry chains in small adders?

The simple carry-in adder assignment (x + C + ci)

  wire [4:0] sum = lastVal[4:0] + (down ? 5'h1f : 5'h0) + up;

Implements with several LUTs rather than one convenient carry chain.

Why?  More important, how does one synthesize around this to get the
carry chain?  The USE_CARRY_CHAIN attribute is worthless.

- John_H

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From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: Re: Generate sample rate ...
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On Fri, 21 Nov 2008 21:14:16 +0100
"Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM> wrote:

> Hi,
> 
> I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would
> like to generate a sample rate that is not a integer of this clock
> and drive a DAC with this sample rate.
> 
> Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz.
> 
> This sample rate must be brought to the speed of the clock of DAC to 
> generate it, by interpolating.
> 
> How to achieve ? It is possible ?
> 
> Thanks.
> 
> Kappa. 
> 
> 

Not to ask what may be a stupid question, but why exactly do you want
to generate this precise sample rate?
 
-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 136559
Subject: Re: Generate sample rate ...
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Fri, 21 Nov 2008 14:46:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On 21 Nov., 22:21, "Kappa" <NO_SPAM_78kapp...@virgilio.it_NO_SPAM>
wrote:

> Perhaps I explained badly.

Yes, I think so.
Your DAC ist running at 140MHz?
So probably you should run your signal processing and the data
transfer between FPGA and DAC also at 140MHz.
Do you want to sent arbitrary PCM coded signals that arrive at
9.4...MHz to the DAC at 140MHz?
(google "sample rate conversion", specifically "non integer
upsampling")
or do you want to use your DAC to output a 9.4...MHz Signal, for
example a 9.4MHz sine wave?
In that case google "DDS" or "Direct Digital Synthesis" or  look for
some posts by Peter Alfke in this newgroup.

Kolja Sulimma

Article: 136560
Subject: Re: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Sat, 22 Nov 2008 00:21:04 +0100
Links: << >>  << T >>  << A >>

Hi Kolja Sulimma,

> Your DAC ist running at 140MHz?

Yes.

> So probably you should run your signal processing and the data
> transfer between FPGA and DAC also at 140MHz.

Yes. My DAC and FPGA works at 140 MHz.

> Do you want to sent arbitrary PCM coded signals that arrive at
> 9.4...MHz to the DAC at 140MHz?

Yes. My data is at 9.4 MHz Sample Rate.

> or do you want to use your DAC to output a 9.4...MHz Signal, for
> example a 9.4MHz sine wave?
> In that case google "DDS" or "Direct Digital Synthesis" or  look for
> some posts by Peter Alfke in this newgroup.

No this simple for me ...

Thanks.

Kappa.



Article: 136561
Subject: Re: Student FPGAs
From: John Adair <g1@enterpoint.co.uk>
Date: Sat, 22 Nov 2008 02:50:14 -0800 (PST)
Links: << >>  << T >>  << A >>
We run a university program http://www.enterpoint.co.uk/uap/uap.html
but this is aimed at the universities and colleges themselves and not
really at individual students. At the moment we aren't shipping a V5
board.

Xilinx has a support program too but again you need to get your
institution involved to get free or cheap boards and that's usually on
a project merit as well.

Digilent do have a cheap student price V2 board. I'm not sure if they
have a V5 board yet.

You have not specified if your request for a V5 and why you need such
a powerful beast. Some more information may help the group at pointing
you at doing whatever other ways.


John Adair
Enterpoint Ltd.

On 21 Nov, 16:05, Philipp <Phil...@gmx.at> wrote:
> Hi
>
> I am just wondering if there are any other companies out there that
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be
> interesting to explore.
>
> Cheers,
> Philipp


Article: 136562
Subject: Re: Generate sample rate ...
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Sat, 22 Nov 2008 05:14:47 -0600
Links: << >>  << T >>  << A >>

>> How much do you care about the quality of the signal your DAC
>> is generating?
>
>The signal must be good SFDR 60 dB or more.

60 dB isn't a lot, but my math skills are good enough
to translate that to/from clock jitter.

>> If you want a clean signal, your best bet is to run the DAC off
>> a low jitter osc package.
>
>Yes, 140 MHz is a OSC with low jitter.

There are two sources of jitter that seem important in this
discussion.

If you run the clock thrugh the FPGA, that will add some jitter,
more if you use the DCM.  This comes from things like noise on the
power supply rails.

If you use something like a DDS to make another clock you can get
lots of "interesting" spurs that may or may not be a problem for
your application.


>> You can make a signal that's close to 9.4 MHz, but it will have
>> some jitter.  Google for dds.  If you get close enough the
>> error in your source clock will be the major source of error.
>
>I should not generate an output signal of 9.4 MHz, are able to do this with 
>a DDS, but clocking data at this speed.

I can't figure out what that means.


-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136563
Subject: Re: Generate sample rate ...
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Sat, 22 Nov 2008 05:32:40 -0600
Links: << >>  << T >>  << A >>

>Yes. My DAC and FPGA works at 140 MHz.
>
>> Do you want to sent arbitrary PCM coded signals that arrive at
>> 9.4...MHz to the DAC at 140MHz?
>
>Yes. My data is at 9.4 MHz Sample Rate.

(Assuming I understand what you are doing...)

If you were doing it with pencil and paper, you would
interpolate between your 9.4 MHz data points to find
the appropriate values to send to your 140 MHz DAC.

I think that is something like a filter, but I'm not
fluent in this area.  You might ask in the dsp newsgroup.


-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136564
Subject: Re: Generate sample rate ...
From: secureasm@gmail.com
Date: Sat, 22 Nov 2008 05:13:03 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi Hal Murray,

Thanks for your support ...

> >Yes. My data is at 9.4 MHz Sample Rate.
>
> (Assuming I understand what you are doing...)

I'm happy ...

> If you were doing it with pencil and paper, you would
> interpolate between your 9.4 MHz data points to find
> the appropriate values to send to your 140 MHz DAC.

The value is not exactly 9.4 MHz but "66Mhz / 7" =3D 9.428571429 MHz.

This "Sample Time" clocking data to be brought to the sample rate of
140 MHz and then be sent to the DAC.

On that we agree ?

In theory the data should be interpolated to "140 MHz / (66Mhz / 7)" =3D
"(140 MHz * 7) / 66MHz" =3D "980 MHz / 66 MHz" =3D "14,8484...."

How is this possible ? I can not imagine a possibility of
realization.

How to make a SQUARE WAVE CLOCK of "66MHz / 7" from 140 MHz to
clocking data ?

I am frustrated :-( ....

> I think that is something like a filter, but I'm not
> fluent in this area. =A0You might ask in the dsp newsgroup.

I'am try ...

Thanks.

Kappa.

Article: 136565
Subject: Re: Student FPGAs
From: Lorenz Kolb <lorenz.kolb@uni-ulm.de>
Date: Sat, 22 Nov 2008 14:57:52 +0100
Links: << >>  << T >>  << A >>
Philipp wrote:
> Hi
> 
> I am just wondering if there are any other companies out there that 
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be 
> interesting to explore.
> 
> Cheers,
> Philipp

Well it's not a student-board, though in terms of cost (compared to 
typical costs) Avnet has a Virtex-5FXT Evaluation board for "only" 395$.

That's quite cheap for that sort of board.

Regards,

Lorenz

Article: 136566
Subject: Re: Small adders in XST?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 22 Nov 2008 14:11:23 +0000
Links: << >>  << T >>  << A >>
On Fri, 21 Nov 2008 13:53:44 -0800 (PST), John_H wrote:

>  How does one coerce XST to use carry chains in small adders?

One trick we've used is to make the carry look like
another LSB:

  wire [4:0] sum;
  wire junk_lsb;
  assign {sum, junk_lsb} = {A[4:0], ci} + {B[4:0], 1'b1};

Now you get the correct result at the cost of an additional
LSB, but with any luck the compiler will see that the LSB's
sum output (a) is exactly ~ci, (b) goes nowhere, and will
optimize it away - leaving you with exactly ci fed to the
carry-in of the remaining bits.  Worth a try, anyhow.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 136567
Subject: Re: Small adders in XST?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 22 Nov 2008 14:46:39 +0000
Links: << >>  << T >>  << A >>
On Sat, 22 Nov 2008 14:11:23 +0000, Jonathan Bromley wrote:

>>  How does one coerce XST to use carry chains in small adders?
>
>  wire [4:0] sum;
>  wire junk_lsb;
>  assign {sum, junk_lsb} = {A[4:0], ci} + {B[4:0], 1'b1};
>
>Now you get the correct result at the cost of an additional
>LSB, but with any luck the compiler will see that the LSB's
>sum output (a) is exactly ~ci, (b) goes nowhere, and will
>optimize it away - leaving you with exactly ci fed to the
>carry-in of the remaining bits.  Worth a try, anyhow.

so, I tried it - in ISE 8.2, sorry, haven't upgraded yet -
and got a nice 5-bit adder with a carry chain, but an 
unexpected sixth LUT to invert "ci".  No idea why.

So I tried this version - functionally equivalent 
except that the junk_lsb output is always zero:

 assign {sum, junk_lsb} = {A[4:0], ci} + {B[4:0], ci};

and got exactly what I wanted, a 5-bit adder with a carry in.

Sometimes this stuff hurts my head quite badly ;-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 136568
Subject: Re: Small adders in XST?
From: "Jan Bruns" <testzugang_janbruns@arcor.de>
Date: Sat, 22 Nov 2008 16:00:54 +0100
Links: << >>  << T >>  << A >>

"John_H":
>A bigger question for Jan Bruns may be:
> 
>  How does one coerce XST to use carry chains in small adders?
> 
> The simple carry-in adder assignment (x + C + ci)
> 
>  wire [4:0] sum = lastVal[4:0] + (down ? 5'h1f : 5'h0) + up;
> 
> Implements with several LUTs rather than one convenient carry chain.
> 
> Why?  More important, how does one synthesize around this to get the
> carry chain?  The USE_CARRY_CHAIN attribute is worthless.


Thanks.  I guess this has to do with the delay introduced
by entering/leving the carry chain (I don't really understand, why this 
is so expensive, maybe it's just to be safe with larger adders?).
Looks like this carry-visit adds up to 1 or 2 ns (equivalent
to the delay of 2 or 3 levels of LUT, without routing).

Gruss

Jan Bruns




Article: 136569
Subject: Re: Generate sample rate ...
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Sat, 22 Nov 2008 09:06:35 -0600
Links: << >>  << T >>  << A >>
>Hi Hal Murray,
>
>Thanks for your support ...
>
>> >Yes. My data is at 9.4 MHz Sample Rate.
>>
>> (Assuming I understand what you are doing...)
>
>I'm happy ...
>
>> If you were doing it with pencil and paper, you would
>> interpolate between your 9.4 MHz data points to find
>> the appropriate values to send to your 140 MHz DAC.
>
>The value is not exactly 9.4 MHz but "66Mhz / 7" =3D 9.428571429 MHz.
>
>This "Sample Time" clocking data to be brought to the sample rate of
>140 MHz and then be sent to the DAC.
>
>On that we agree ?
>
>In theory the data should be interpolated to "140 MHz / (66Mhz / 7)" =3D
>"(140 MHz * 7) / 66MHz" =3D "980 MHz / 66 MHz" =3D "14,8484...."
>
>How is this possible ? I can not imagine a possibility of
>realization.
>
>How to make a SQUARE WAVE CLOCK of "66MHz / 7" from 140 MHz to
>clocking data ?
>
>I am frustrated :-( ....
>
>> I think that is something like a filter, but I'm not
>> fluent in this area. =A0You might ask in the dsp newsgroup.
>
>I'am try ...
>
>Thanks.
>
>Kappa.
Hi Kappa,

If you want to upsample your signal by 66/7 then this should be possible
using one FIR filter that implements fractional(rational)interpolation(one
filter for FPGAs is attractive, DSP people may use more filters).

The idea is a bit difficult but depends on using one Filter only and let
it do an interpolatin of 66 followed by decimation of 7. I have more
details on this if you are interested.  

Kadhiem


Article: 136570
Subject: Re: Small adders in XST?
From: "Jan Bruns" <testzugang_janbruns@arcor.de>
Date: Sat, 22 Nov 2008 16:46:16 +0100
Links: << >>  << T >>  << A >>

"Jan Bruns":
> Thanks.  I guess this has to do with the delay introduced
> by entering/leving the carry chain (I don't really understand, why this 
> is so expensive, maybe it's just to be safe with larger adders?).
> Looks like this carry-visit adds up to 1 or 2 ns (equivalent
> to the delay of 2 or 3 levels of LUT, without routing).

Or maybe, MUXCY is really that slow (from sel to out). At least
it's surely optimized to minimize capacitance on the carry forward path.
Maybe capacitance on that path is also the reason for routing
out of the chain somewhere is also relatively expensive in terms
of delay.

Gruss

Jan Bruns


Article: 136571
Subject: Re: Generate sample rate ...
From: "Richard Head" <rich.head@richoshay.com>
Date: Sat, 22 Nov 2008 16:11:20 -0000
Links: << >>  << T >>  << A >>

"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> wrote in message 
news:P5ednRI63olmgrXURVn_vwA@giganews.com...

>
> If you want to upsample your signal by 66/7 then this should be possible
> using one FIR filter that implements fractional(rational)interpolation(one
> filter for FPGAs is attractive, DSP people may use more filters).
>
> The idea is a bit difficult but depends on using one Filter only and let
> it do an interpolatin of 66 followed by decimation of 7. I have more
> details on this if you are interested.
>
> Kadhiem
>


..... and this works in a time sampled system .. or is the FIR unclocked? 
(!) 



Article: 136572
Subject: Re: Generate sample rate ...
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Sat, 22 Nov 2008 10:30:29 -0600
Links: << >>  << T >>  << A >>
>..... and this works in a time sampled system .. or is the FIR unclocked?

>(!) 

Hi,

Any FIR filter works as a sampling system and needs a clock. It will work
at 140MHz clock but will clock data in at any lower rate.

I am still not clear what you actually want to do.
I know your DAC is at 140MHz.
You also say that your FPGA runs at 140MHz(but possibly not your data)
What is your FPGA data sampling frequency then(effective clk if enable
used)? 

kadhiem

Article: 136573
Subject: Re: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Sat, 22 Nov 2008 17:40:28 +0100
Links: << >>  << T >>  << A >>

Hi kadhiem_ayob

> The idea is a bit difficult but depends on using one Filter only and let
> it do an interpolatin of 66 followed by decimation of 7. I have more
> details on this if you are interested.

I'm interested, but why interpolate for 66 ? I do not understand.

Kappa. 



Article: 136574
Subject: Re: Generate sample rate ...
From: "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM>
Date: Sat, 22 Nov 2008 17:42:52 +0100
Links: << >>  << T >>  << A >>

Hi kadhiem_ayob,

> Any FIR filter works as a sampling system and needs a clock. It will work
> at 140MHz clock but will clock data in at any lower rate.

Ok.

> I am still not clear what you actually want to do.
> I know your DAC is at 140MHz.
> You also say that your FPGA runs at 140MHz(but possibly not your data)
> What is your FPGA data sampling frequency then(effective clk if enable
> used)?

DAC = 140 MHz
FPGA = 140 MHz

Sample time : 66MHz / 7

Kappa. 





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