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Jay, Thanks, Austin Jay wrote: > Read below... > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC57702.2620F2DB@xilinx.com>... > > Jay, > > > > How much RAM is enough? > > About 8Mbits are required. > > > Is the 405PPC core in Virtex II Pro fast enough (>300 MHz)? > > Its completely the wrong processor, besides, thats a hardwired ASIC > macro on your FPGA die, so thats why it's reasonably fast. > > > How much random logic is required? > > About twice as much as your largest shipping part. And its way too > slow for prime time. The part complexity was scaled to use the > available gates/ram in the current semiconductor process technology. > If we could have made it bigger at a reasonable yield, we would have, > and taken the performance. > > > EasyPath will be there for Virtex II Pro. We are looking to the future, and answers to these > > questions will help us decide future family members. More data points the better. > > Glad to help. > > > Thanks for your comments, > > > > AustinArticle: 42476
Jeremy D. Grotte wrote: > > I don't even know if I'm in the right news group or not. Yes, you are. > I haven't messed with PAL's/GAL's/FPGA's at all...yet. But I > think I have a need for them now. > Basically, I've got a project where I've got to move data > around very quickly, from a USB port to a hard drive. Right > now, my MCU (PIC16F877) strobes a USB interface chip for > data (high byte), moves that data to a latch, strobes the > USB chip again, hold that data on the lines (low byte), then > strobe the drive's WRite lines, then releases everything, > pauses for one cycle and repeats the process 256 times (one > sector at a time dontcha know). So, that's all fine and > dandy, it works and it works well, but it's slow, even with > a 20Mhz clock rate, I can only transfer about 40K/second > using nice tight code that doesn't do anything else inside > the loops except move data around. I want faster!!! (who > doesn't?) > So, I'm wondering if some sort of PAL/GAL/FPGA chip might be > the correct way to go to handle this at nice fast speeds. > A chip of this type would have to have a 8 bit counter (to > keep a running count of 256 words), 2 8-bit latches (one for > each low and high byte), 6 output signals to control the > drive (A0-A2, RD*, WR*, ChipSelect) and a few pins for CPU > control and status (BuSY/ReaDY status, a CPU strobed START > pin, a line to the USB chip for ReaD-ReaDY and ReaD-Byte). > The CPU would pulse the START pin, which would start the > FPGA (or whatever) chip doing it's thing. The FPGA (or > whatever) would pull the BuSY/ReaDY low (or high, whatever), > then would starting counting each word transferred, it would > check the USB pin for see if it has data available, if it > is, it would pull the RD low and strobe in a byte, shift > that byte up to the upper byte latch, re-check the USB pin > for more data, strobe that data and hold it on the data > lines, then strobe the hard drives control lines > accordingly. A CPLD will do this well, and you may be able to avoid latch of LOW byte with carefull strobes : Write to IDE as you read the 2nd byte. That's 8 buried registers for counter, 8 Pin registers for Hi Byte, 8 Pins for Main 8 bit BUS and a handfull for state machine and signaling. Code it so you have uC soft access to all HW lines as well, then for the odd transaction that is not covered by the burst mover, you can still have full control. If this is a 5V system, look at Atmel ATF1504 - 64 macrocells in PLCC44 or TQFP44, with 36 io. If it's high volume, the ATF1502 may squeeze it in. Also, take a look at Atmel T89C51SND1, which has USB + IDE + 64K Flash uC all in one chip :-) -jgArticle: 42477
Hi everyone. I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success with tying the Spartan directly to the bus, it is just not reliable and gives me sporadic values when reading from the Spartan. Since I have no trouble writing to the Spartan I'm assuming it has something to do with the 3.3V just basically not making it over the wires to the bus (because all my errors appear to be 1's that are being interpreted as lows). Anyway, to rectify this problem I'm attempting to use a 74HCT245 transciever to pull the Spartan outputs to a full 5V. I'm tying the IOread signal to the direction pin of the transciever, but I can't get the PC to boot when the setup is attached to the ISA data bus. I've decided this is probably because the transciever needs to be in isolation mode at the appropriate time. However, I can't think of a way to do this during boot. It would be easy enough to control this once the Spartan is programmed because I'd have my ISA port code and I could just output a few signals to tell the 74HCT to go into isolation. This obviously isn't possible before the chip is programmed though, and so I'm stuck with a PC that won't boot with the spartan (via the transciever) attached to the data bus. The "enable" signal is active low. So when it is high the chip goes into isolation, which is what I would want at boot-up. Has anyone else used this chip in this fashion and can tell me how they solved this problem, or does anyone have any ideas on how to solve this problem? Thanks. SeanArticle: 42478
Isn't the IOread signal for all IO mapped accesses such that an IOread to a different PC card or peripheral on the motherboard would result in a bus contention? If you qualify your IOread by decoding an address (or peripheral select? It's been a while) in the Spartan-II to drive the 74HCT245 OE - designed so before configuration the OE is inactive - you should have a well behaved interface device. Sean A Laughter wrote: > Hi everyone. > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > with tying the Spartan directly to the bus, it is just not reliable and > gives me sporadic values when reading from the Spartan. Since I have no > trouble writing to the Spartan I'm assuming it has something to do with > the 3.3V just basically not making it over the wires to the bus (because > all my errors appear to be 1's that are being interpreted as lows). > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > transciever to pull the Spartan outputs to a full 5V. I'm tying the > IOread signal to the direction pin of the transciever, but I can't get the > PC to boot when the setup is attached to the ISA data bus. > > I've decided this is probably because the transciever needs to be in > isolation mode at the appropriate time. However, I can't think of a way > to do this during boot. It would be easy enough to control this once the > Spartan is programmed because I'd have my ISA port code and I could just > output a few signals to tell the 74HCT to go into isolation. This > obviously isn't possible before the chip is programmed though, and so I'm > stuck with a PC that won't boot with the spartan (via the transciever) > attached to the data bus. The "enable" signal is active low. So when it > is high the chip goes into isolation, which is what I would want at > boot-up. > > Has anyone else used this chip in this fashion and can tell me how they > solved this problem, or does anyone have any ideas on how to solve this > problem? Thanks. > > SeanArticle: 42479
The Spartan-II has enough kick for the real slow ISA bus - does it work OK in simulation? For your HCT245 (slow and old!) drive the '245 CE# from a spartan pin and set the spartan M2/M1/M0 as 'pins pulled-up until configured' Sean A Laughter wrote > Hi everyone. > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > with tying the Spartan directly to the bus, it is just not reliable and > gives me sporadic values when reading from the Spartan. Since I have no > trouble writing to the Spartan I'm assuming it has something to do with > the 3.3V just basically not making it over the wires to the bus (because > all my errors appear to be 1's that are being interpreted as lows). > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > transciever to pull the Spartan outputs to a full 5V. I'm tying the > IOread signal to the direction pin of the transciever, but I can't get the > PC to boot when the setup is attached to the ISA data bus. > > I've decided this is probably because the transciever needs to be in > isolation mode at the appropriate time. However, I can't think of a way > to do this during boot. It would be easy enough to control this once the > Spartan is programmed because I'd have my ISA port code and I could just > output a few signals to tell the 74HCT to go into isolation. This > obviously isn't possible before the chip is programmed though, and so I'm > stuck with a PC that won't boot with the spartan (via the transciever) > attached to the data bus. The "enable" signal is active low. So when it > is high the chip goes into isolation, which is what I would want at > boot-up. > > Has anyone else used this chip in this fashion and can tell me how they > solved this problem, or does anyone have any ideas on how to solve this > problem? Thanks.Article: 42480
Sean A Laughter <s2salaug@mail2.vcu.edu> writes: > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > transciever to pull the Spartan outputs to a full 5V. I'm tying the > IOread signal to the direction pin of the transciever, but I can't get the > PC to boot when the setup is attached to the ISA data bus. [...] > The "enable" signal is active low. So when it > is high the chip goes into isolation, which is what I would want at > boot-up. > > Has anyone else used this chip in this fashion and can tell me how they > solved this problem, or does anyone have any ideas on how to solve this > problem? Thanks. Pullup resistor on the '245 enable input?Article: 42481
I'm looking for someone to develop a counter application right away. If interested mail me back for details. k.h.Article: 42482
You can find all the answers here:
http://www.xilinx.com/partinfo/databook.htm#spartan
Pawe=B3 J. Rajda <pjrajda@uci.agh.edu.pl> wrote in message news:3CC690B0.114551AA@uci.agh.edu.pl...
I am making a small (XC2S30) project and have a few questions:
1. DLL's
Is the usage of DLLs obligatory or not? I am shifting data to the Spartan
synchronously with external 4,096MHz clock. Another clock in my project
is about 11MHz. Do such clocks need DLLs?
2. I/Os
I have to interface to 5V devices. Which I/O standard should I use: LVTTL
or PCI_33_5? In what they differs (both are 5V tolerant)? Only in current
sink/source capabilities?
3. Configuration
I will use Master Serial mode. What is the Preconfiguration Pull-ups option?
Should I turn it on or off?
--
Regards,
Pawel J. Rajda
Article: 42483Hi everyone again. I think I solved my problem, but I did it by completely getting rid of the transciever and simply putting 4.7k ohm pullup (to 5V) resistors to the bus outputs. It seems to work fine, aside from some single glitches on a few occasions. In any case it's much more reliable now that it was. I'm not doing something foolish by using pullup resistors on the bus though am I? It doesn't seem to cause any harm or impede the operation of the PC in any way, at least visibly. Sean A Laughter <s2salaug@mail2.vcu.edu> wrote in message news:<Pine.SGI.4.33.0204241846190.308721-100000@neptune.vcu.edu>... > Hi everyone. > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > with tying the Spartan directly to the bus, it is just not reliable and > gives me sporadic values when reading from the Spartan. Since I have no > trouble writing to the Spartan I'm assuming it has something to do with > the 3.3V just basically not making it over the wires to the bus (because > all my errors appear to be 1's that are being interpreted as lows). > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > transciever to pull the Spartan outputs to a full 5V. I'm tying the > IOread signal to the direction pin of the transciever, but I can't get the > PC to boot when the setup is attached to the ISA data bus. > > I've decided this is probably because the transciever needs to be in > isolation mode at the appropriate time. However, I can't think of a way > to do this during boot. It would be easy enough to control this once the > Spartan is programmed because I'd have my ISA port code and I could just > output a few signals to tell the 74HCT to go into isolation. This > obviously isn't possible before the chip is programmed though, and so I'm > stuck with a PC that won't boot with the spartan (via the transciever) > attached to the data bus. The "enable" signal is active low. So when it > is high the chip goes into isolation, which is what I would want at > boot-up. > > Has anyone else used this chip in this fashion and can tell me how they > solved this problem, or does anyone have any ideas on how to solve this > problem? Thanks. > > SeanArticle: 42484
Hi! Does anyone know how to include SpartanXL element OSC4 in VHDL code, and where can I found it, I mean in which library? thanks, sashArticle: 42485
I want to manipulate the bitstream file for an AT40k and need to know, how I can get more information, where the window addresses come from and how the 4 byte data block is set, so that I can manipulate the muxer in the logic cells. Thanks. Greetings. Michael KleinkesArticle: 42486
I suppose maybe I should've been a bit clearer. If I am correct in saying, a DDFS will generate digital values for a synthesised waveform, to be used as input into a DAC. What I need is to generated a square wave output at a given frequency, using the 5MHz signal as a reference... ideally i am trying to generate a 32MHz signal. Noddy > Noddy, > > Use a DDFS (direct digital frequency Synthesizer). > > Austin > > Noddy wrote: > > > Hi, > > > > I am trying to design a high precision (30 bit) frequency synthesiser inside > > a Spartan II. Of course, normal way to do this is with a charge pump, > > voltage controlled oscillator and a phase lock loop. > > > > Can anyone point me to some good references? I have a very high precision > > 5Mhz which is generated from a hydrogen maser and will be used as the input > > clock signal. > > > > thanks > > adrian >Article: 42487
Hi Michael,
Sounds to me like someone else has got bitten by the CPU building
bug.... I've just purchased a D2E board from Nu-Horizens (1) for
that purpose - it's got a Spartan-IIE (200) on it, and also bought
the associated DIO2 board.
The pair of boards are really not expensive, and are supported by the free
versions of the Xilinx tools - which raises one reason why you and your
friend might not wish to buy a Virtex 2 board - you will not only need to
by the hardware, but also the development tools, the cost of which is
likely to be higher. Also, it'll look neat to chain multiple boards
together, and it's cheaper to do that with spartans ;-)
A -200 virtex/spartan2 chip should provide many more resources than you
need for designing CPU's, at least whilst you are getting started - there
is more embedded RAM in them than Elite used to use (!) You will probably
be able to use the embeded RAM for all the testing of components and
processors, and for running reasonably sized programs. If / when you find
an architecture you like and decide to scale it up, the blockrams can then
transition to being caches.
I plan to connect an external SRAM to my Spartan IIE later on, possibly a
flash chip as well, via a CPLD. This would be necessary for a VGA
interface, unless you use a character generator.
A friend and I have a cunning plan about VGA however - I'm thinking
about building an external ISA bus (use a CPLD to spruce things up,
give some less brain dead interrupts etc, and maybe insert a RAM based
address map to allow different brain damaged cards to share addresses
/ IRQs etc.) - this way old and loved graphics cards and the like can
be used, and many ISA cards have documented drivers written for Open
Source OS'. The current thinking is to design a PCB for a CPLD, Flash,
SRAM, ISA and populate it with goodies as needs call. The soldering
shouldn't be a stumbling block for people without access to a really
decent iron either.
I am wondering about the possibility of having individual coprocessors in
the FPGA for different cards, to abstract them from the FPGA CPU, a bit
like the Amigas graphics coprocessor - imagine for instance a coproc that
interfaces a 10Mbit eth card to the FPGA, providing access at either the
TCP or UDP level. Should be a boost for performance.
There are a plethora of useful ISA cards floating about either for free
scavenging, or very cheaply at computer fairs.
A possible extension of the plan is to implement an FPGA design that acts
as a pass through from the external ISA bus to a PC, so that a CPU
simulator / virtual machine running under BSD (or Linux etc.) can access
the bus identically to an FPGA implementation. Neat, and good for
debugging.
Getting carried away, I'm wondering if it would be possible to hack such a
bridge into Dosemu or WINE under Linux, and have it map selected IO access
to the external bus, allowing old cards and software to be rehabilitated.
I think this plan was induced by the number of 'legacy free' motherboards
coming out lately with no ISA, ps2, serial, parallel ports. Ug.
One of the most useful things you could possibly buy for this sort of work
is a dual parallel port PCI card, the ability to hook up an 8/16 bit
signal to an FPGA for debugging, or to talk to a debug processor in the
device, is almost beyond value.
Regards, and have fun!
Chris Saunter
(1)
http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIEBoard.html
H
Michael (mikenet@freewebemail.com) wrote:
: For a long time I've found CPU design interesting, but never had the
: resources to go out and test any of my ideas.(strange memories of
: arguing with my friends about CPU architecture at sushi restaurants
: come to mind) Recently, I've been looking at FPGA boards, and would
: like input. I'm a hobbyist(highschool student) and therefore have very
: little funds.
: Although I've been looking at doing very simple designs, I'd like
: to have a larger device available if I need it(or try to do a system
: with simple I/O, and maybe a VGA framebuffer), and a few megabytes of
: RAM(this is where most low cost boards fall short). I've been
: considering the following boards:
<big snip>
: Can anyone comment, correct, recommend, etc?
<see above... ;->
: Thanks in advance,
: Michael <mikenetaim-removethis@attbi.com-removethis> (please respond
: directly to usenet group if possible)
Article: 42488Cool. I really didn't expect any responses, much less a couple here and a half a dozen e-mails in one day... I did some thinking about the circuit, and I really don't need the latches. The circuit I've designed already has the latches, I just need a high speed method of controlling them. But on that same note, I am going to check out the T89C51SND1 chip. The only thing that chip doesn't have on it is an MP3 decoder, which is easily done by a VS1001K. Thanks for the info......Off to the Datasheets!!!! -- Jeremy D. Grotte www.geocities.com/Skimask87 > > A CPLD will do this well, and you may be able to avoid latch of > LOW byte with carefull strobes : Write to IDE as you read the 2nd byte. > That's 8 buried registers for counter, 8 Pin registers for Hi Byte, > 8 Pins for Main 8 bit BUS and a handfull for state machine and > signaling. > > Code it so you have uC soft access to all HW lines as well, then for > the odd transaction that is not covered by the burst mover, you can > still have full control. > > If this is a 5V system, look at Atmel ATF1504 - 64 macrocells in > PLCC44 or TQFP44, with 36 io. > If it's high volume, the ATF1502 may squeeze it in. > > Also, take a look at Atmel T89C51SND1, which has USB + IDE + 64K Flash > uC > all in one chip :-) > > -jgArticle: 42489
Sean, I don't suppose you would consider doing IBIS simulations to discover what your problem really is? If you open a case on the hotline, and request them to run a simulation for you, they will. Might lead to some insight into what is really happening, rather that groping about in the dark. Austin Sean wrote: > Hi everyone again. > > I think I solved my problem, but I did it by completely getting rid of > the transciever and simply putting 4.7k ohm pullup (to 5V) resistors > to the bus outputs. It seems to work fine, aside from some single > glitches on a few occasions. In any case it's much more reliable now > that it was. I'm not doing something foolish by using pullup > resistors on the bus though am I? It doesn't seem to cause any harm > or impede the operation of the PC in any way, at least visibly. > > Sean A Laughter <s2salaug@mail2.vcu.edu> wrote in message news:<Pine.SGI.4.33.0204241846190.308721-100000@neptune.vcu.edu>... > > Hi everyone. > > > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > > with tying the Spartan directly to the bus, it is just not reliable and > > gives me sporadic values when reading from the Spartan. Since I have no > > trouble writing to the Spartan I'm assuming it has something to do with > > the 3.3V just basically not making it over the wires to the bus (because > > all my errors appear to be 1's that are being interpreted as lows). > > > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > > transciever to pull the Spartan outputs to a full 5V. I'm tying the > > IOread signal to the direction pin of the transciever, but I can't get the > > PC to boot when the setup is attached to the ISA data bus. > > > > I've decided this is probably because the transciever needs to be in > > isolation mode at the appropriate time. However, I can't think of a way > > to do this during boot. It would be easy enough to control this once the > > Spartan is programmed because I'd have my ISA port code and I could just > > output a few signals to tell the 74HCT to go into isolation. This > > obviously isn't possible before the chip is programmed though, and so I'm > > stuck with a PC that won't boot with the spartan (via the transciever) > > attached to the data bus. The "enable" signal is active low. So when it > > is high the chip goes into isolation, which is what I would want at > > boot-up. > > > > Has anyone else used this chip in this fashion and can tell me how they > > solved this problem, or does anyone have any ideas on how to solve this > > problem? Thanks. > > > > SeanArticle: 42490
Actually, you are violating the max Vih spec for these chips. Spartan II devices are not 5 volt tolerant and should not be used in this application. We are doing the same thing with the same chip and we are using a CoolRunner part as a large buffer chip to isolate the ISA bus from the Spartan II chip. If you are just designing an IO mapped, 8 bit peripheral, then you only need 8 data bits plus 10 address bits and 3 or so control lines. You can interface all this with three 245 chips. But as another poster said, you have to decode the address inside the FPGA to generate the enable to the 245 data buffer chip. If you are enabling it on just IORD, then you are responding when any IO device is being read and corrupting that data. This is why your PC won't boot. So add the decoding to the SpartanII, use a pullup on the enable to the data bus 245, enable the address and control line 245s at all times with the direction fixed to input from the bus and your design should start to work. Sean wrote: > > Hi everyone again. > > I think I solved my problem, but I did it by completely getting rid of > the transciever and simply putting 4.7k ohm pullup (to 5V) resistors > to the bus outputs. It seems to work fine, aside from some single > glitches on a few occasions. In any case it's much more reliable now > that it was. I'm not doing something foolish by using pullup > resistors on the bus though am I? It doesn't seem to cause any harm > or impede the operation of the PC in any way, at least visibly. > > Sean A Laughter <s2salaug@mail2.vcu.edu> wrote in message news:<Pine.SGI.4.33.0204241846190.308721-100000@neptune.vcu.edu>... > > Hi everyone. > > > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > > with tying the Spartan directly to the bus, it is just not reliable and > > gives me sporadic values when reading from the Spartan. Since I have no > > trouble writing to the Spartan I'm assuming it has something to do with > > the 3.3V just basically not making it over the wires to the bus (because > > all my errors appear to be 1's that are being interpreted as lows). > > > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > > transciever to pull the Spartan outputs to a full 5V. I'm tying the > > IOread signal to the direction pin of the transciever, but I can't get the > > PC to boot when the setup is attached to the ISA data bus. > > > > I've decided this is probably because the transciever needs to be in > > isolation mode at the appropriate time. However, I can't think of a way > > to do this during boot. It would be easy enough to control this once the > > Spartan is programmed because I'd have my ISA port code and I could just > > output a few signals to tell the 74HCT to go into isolation. This > > obviously isn't possible before the chip is programmed though, and so I'm > > stuck with a PC that won't boot with the spartan (via the transciever) > > attached to the data bus. The "enable" signal is active low. So when it > > is high the chip goes into isolation, which is what I would want at > > boot-up. > > > > Has anyone else used this chip in this fashion and can tell me how they > > solved this problem, or does anyone have any ideas on how to solve this > > problem? Thanks. > > > > Sean -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42491
This is a primitive so just instantiate it as a black box and ngdbuild will
parse the primitive fine.
component OSC4
port( F8M : out std_ulogic ;
F500K : out std_ulogic ;
F16K : out std_ulogic ;
F490 : out std_ulogic ;
F15 : out std_ulogic );
end component;
Best regards,
Chris Dunlap
Sasa Bremec wrote:
> Hi!
>
> Does anyone know how to include SpartanXL element OSC4 in VHDL code, and
> where can I found it, I mean in which library?
>
> thanks, sash
Article: 42492Noddy, To use a DDFS, you need 2 X the highest output frequency as the input frequency. I would take the 5 MHz maser, multiply it up externally with a PLL to > 100 MHz, and then run the DDFS with that. You also may have to filter the 1/CLK jitter from the DDFS output, and another PLL that is 1:1 will do that fine. Or, you can synthesize a 2 MHz output with your 5 MHz clock, and run it to a PLL that is 1:16 to get your 32 MHz AND filter the jitter at the same time. For ultra low jitter and stability, I would use a VCXO as part of the PLL doing the filtering. I designed GPS Stratum 1 clock sources for 12 years, and that is how I did it. Note I have the patent on the techniques, so be sure to read the patent and do it differently (not hard to do), or license it from my former employers. Austin Noddy wrote: > I suppose maybe I should've been a bit clearer. If I am correct in saying, a > DDFS will generate digital values for a synthesised waveform, to be used as > input into a DAC. What I need is to generated a square wave output at a > given frequency, using the 5MHz signal as a reference... ideally i am trying > to generate a 32MHz signal. > > Noddy > > > Noddy, > > > > Use a DDFS (direct digital frequency Synthesizer). > > > > Austin > > > > Noddy wrote: > > > > > Hi, > > > > > > I am trying to design a high precision (30 bit) frequency synthesiser > inside > > > a Spartan II. Of course, normal way to do this is with a charge pump, > > > voltage controlled oscillator and a phase lock loop. > > > > > > Can anyone point me to some good references? I have a very high > precision > > > 5Mhz which is generated from a hydrogen maser and will be used as the > input > > > clock signal. > > > > > > thanks > > > adrian > >Article: 42493
Austin, I think you need to read the original post more carefully. He is not working with a 1 MHz clock, it is an 11 MHz clock. The other clock is either 4 MHz or 4 GHz depending on if he is using the comma as a decimal point or as a thousands marker. I find that whole comma vs. period thing very confusing. How did we get to a state where half the technical world uses an opposite notation from the other half? But even if he is working with a 1 MHz clock, how does that eliminate the need for clock deskewing? If he has a minimum hold time that is not met without the clock deskewing, then he will need to use it. I think he was asking for a little more info on how DLLs work, what they accomplish and in which situations you would want to use them. I personally would like to understand SpartanII clocking better. I need six clocks in my design and I am not sure what pins to use to assure that they are routed using low skew paths inside the chip. Only two of these clocks need the DLLs for deskewing inside vs. outside the chip. Austin Lesea wrote: > > Pawel, > > Some answers, below. > > Austin > > "Paweł J. Rajda" wrote: > > > I am making a small (XC2S30) project and have a few questions: > > > > 1. DLL's > > Is the usage of DLLs obligatory or not? I am shifting data to the > > Spartan > > synchronously with external 4,096MHz clock. Another clock in my > > project > > is about 11MHz. Do such clocks need DLLs? > > No. They do not. DLLs deskew clocks for high speed applications > where even 100's of ps are important to keep track of. At 1 MHz, > deskew is not an issue, as the clock period is 1000 ns! > > > > > 2. I/Os > > I have to interface to 5V devices. Which I/O standard should I > > use: LVTTL > > or PCI_33_5? In what they differs (both are 5V tolerant)? Only in > > current > > sink/source capabilities? > > Run IBIS simualtions to choose the best IO standard. > > > > > 3. Configuration > > I will use Master Serial mode. What is the Preconfiguration > > Pull-ups option? > > Should I turn it on or off? > > One can have the IOs pull up while configuring, or not (remain > tristate). > > > > > > > -- > > Regards, > > Pawel J. Rajda > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42494
rickman <spamgoeshere4@yahoo.com> writes: > Actually, you are violating the max Vih spec for these chips. Spartan > II devices are not 5 volt tolerant and should not be used in this > application. That's wrong. The Vih(max) for LVTTL (and other standards) on Spartan-II is 5.5V Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 42495
Muzaffer Kal wrote: > > hi, > I need to connect an SDRAM to a processor and a VirtexII so that both > can access it with VirtexII having the priority. The processor has an > SDRAM controller on it. I am thinking about daisy chaining all the > signals (everything going from CPU through VirtexII to SDRAM) and > implementing an SDRAM controller in VirtexII too. This doesn't have to > be very fast. 60 MB/s throughput would be enough. Does this make > sense? Any other simpler/easier solutions ? Anyone has done anything > similar ? > > thanks, > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations I have done a similar design and it will not work unless you have a way to hold off the processor. Just running the processor bus through the FPGA will not solve the priortity issue. If you can't tell the processor to hold off, it will continue with its access and the data will go into the bit bucket (or from the bit bucket). If the processor has a way to hold off accesses, then it most likely can tristate the bus and you don't need to daisy chain the access. We put both on the same bus and let the tristating share it for us. Don't forget to use pullups on the control signals. But you will need an SDRAM controller in the FPGA regardless. You will also have to make sure that the processor finishes all accesses cleanly with pages closed, etc. Otherwise your FPGA must track the operations of the processor and know when to precharge, etc. Read the SDRAM data sheet VERY carefully. And keep in touch. We will be doing another, very similar design in about three weeks. BTW, what is your processor? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42496
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3CC81CD4.77D0D197@yahoo.com... > Austin, > > thing very confusing. How did we get to a state where half the > technical world uses an opposite notation from the other half? Indeed. > the need for clock deskewing? If he has a minimum hold time that is not > met without the clock deskewing, then he will need to use it. He can output the data on the opposite clock edge to guarantee hold time. > I personally would like to understand SpartanII clocking better. I need Me too. -- MfG FalkArticle: 42497
"Stefano M" <stefano.mora@antispam.libero.it> schrieb im Newsbeitrag news:meBx8.5640$W9.122542@twister2.libero.it... > During Mapping i have following error: > ERROR:MapLib:93 - Illegal LOC on symbol "p_strobe_n" (pad signal=p_strobe_n) or > BUFGP symbol "p_strobe_n_BUFGP" (output signal=d6_OBUF), IPAD-IBUFG should > only be LOCed to GCLKIOB site. > > I don't understand why p_strobe_n signal is considerated > as a clock (but it is NOT a clock) and p_init_n is OK. > They have similar code ..... They are both clocks, since everything with signalname'event is a clock. The problem is not that htey are clocks, the problem is, that you tried to playe one of these clock inputs to a general purpose IO. The software (XST, the VHDL compiler) by default identifies clock signlas and uses global clock inputs and buffers for them. If you now assign these pins to normal IOS (inside the UCF), the mapper will fail. 1) Solution. Place Clock inputs allways to global clock inputs (strongly recommended) 2) Force the compiler to use normal input buffers (Only for expirienced users). To do so place the two lines below in your source code between architecture ... and begin ... (the same place as the signal declarations) attribute clock_buffer: string; attribute clock_buffer of signal_name: signal is"ibuf"; -- MfG FalkArticle: 42498
Have you ever considerated that you may be related to George Bush? Just doing my part to waste bandwidth :) <clip> > I don't understand why p_strobe_n signal is considerated > as a clock (but it is NOT a clock) and p_init_n is OK. > They have similar code ..... > <clip>Article: 42499
Rick, See below, Austin rickman wrote: > Austin, > > I think you need to read the original post more carefully. He is not > working with a 1 MHz clock, it is an 11 MHz clock. OK. Still no reason for a DLL. > The other clock is > either 4 MHz or 4 GHz depending on if he is using the comma as a decimal > point or as a thousands marker. I find that whole comma vs. period > thing very confusing. How did we get to a state where half the > technical world uses an opposite notation from the other half? And how many miles per gallon does your car get? If it is 4 GHz, then I can't help at all. If it is 4 MHz, it is no different that 1 or 11 MHz. > > > But even if he is working with a 1 MHz clock, how does that eliminate > the need for clock deskewing? If he has a minimum hold time that is not > met without the clock deskewing, then he will need to use it. Well, he can use the time honored techiques of using the falling edge of the clock to sample, or some other technique that was used for thirty years before the DLL came into being. > > > I think he was asking for a little more info on how DLLs work, what they > accomplish and in which situations you would want to use them. For that, I recommend the website, and the original Virtex DLL app note. > > I personally would like to understand SpartanII clocking better. I need > six clocks in my design and I am not sure what pins to use to assure > that they are routed using low skew paths inside the chip. Only two of > these clocks need the DLLs for deskewing inside vs. outside the chip. Well, there are only four clock resources in the chip, so two of them are going to have be very carefully placed, perhaps even by hand. I would put the highest frequency ones on the internal BUFG resources, and then tightly constrain the slowest two, and then verify the results. I would use the DLLs are requried for deskew of the highest speed clocks. Why six clocks? Anyway to use fewer clocks and use clock enables? I once had a design that had 10 clocks, and I had a consultant come in who reduced that to two global clocks. All of the others went away through the use of the clock enables on the FF's in the design. I know sometimes it is not possible, but this experience really opened my eyes (E1 <> E2 asynchronous multiplexer/demultiplexer).
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