Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 77625

Article: 77625
Subject: General Question - Which FPGAs can support partial run-tim reconfiguration?
From: "nickel" <nickelyg@gmail.com>
Date: 12 Jan 2005 12:29:48 -0800
Links: << >>  << T >>  << A >>
Hi,

As far as I know, only Xilinx (XC6200, Virtex, Virtex-E, Virtex II,
Virtex 4) and Atmel (FPSLIC - AT94Kxx)support partial run-time
(dynamic) reconfiguration.

Is there any other FPGA vendor being able to support partial run-time
reconfiguration? What are they and what are the families?
Thanks 
Regards
Nickel


Article: 77626
Subject: Re: Starting with xilinix and Linux
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 12 Jan 2005 12:44:05 -0800
Links: << >>  << T >>  << A >>
Duane Clark <junkmail@junkmail.com> writes:
> Supposedly 6.3 includes a Linux version of Chipscope. One of these
> days I'll get around to installing that version and trying it out. 6.3
> also officially supports RHEL.

Only the tools to install the analyzer cores.  You still need Windows
(or an Agilent logic analyzer with suitable probe) to act as the
front end.

Article: 77627
Subject: Re: Looking for low-cost protoboards.
From: pm940@yahoo.com
Date: 12 Jan 2005 12:56:06 -0800
Links: << >>  << T >>  << A >>

lomtik wrote:
> Hi,
> I was looking for some low-cost FGPA board for a home project.

http://www.digilent.us/ make nice Xilinx boards and peripherals for
very low cost.


Article: 77628
Subject: Re: Programming and copyright
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Wed, 12 Jan 2005 21:55:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <sc1bu09h67f7pcn6vcjd8chudvrej6g13v@4ax.com>,
Nick  <char-DONTBUGME-les@YY.iiedotcnam.france> wrote:
>I'm developing a software on a Cyclone FPGA. However now we are think
>about the security of the device : i mean, the code is stored on a
>flash extern to the Cyclone. What can prevent someone from copying the
>data on this flash and clone the product we are doing ?
>
>In Quartus there is a security bit that made me fell confortable,
>however it works only with a Max device.
>
>What solution do I have to protect our software ?

      You sue the bastards who copy it.  Seriously.

      If you want a technical solution, you are going to have to you a
Xilinx Virtex II/IIpro/4 or an Altera Stratix II, which have encrypted
bitfile loaders.

	Digretion: I prefer the approach of the Xilinx parts (volatile
vs nonvolatile key store), but that's just the paranoid in me.  Both
will probably fail against a $100k adversary, both will undoubtedly
fail against a $1M adversary, while the altera one will probably fail
to a $10k adversary while the Xilinx one will probably resist a $10k
adversary until after a $100k adversary shows how to do it.

       But really, the legal approach is probably the least cost,
least hastle, and still reasonably effective way.
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Article: 77629
Subject: Re: Programming and copyright
From: Rene Tschaggelar <none@none.net>
Date: Wed, 12 Jan 2005 22:57:38 +0100
Links: << >>  << T >>  << A >>
Nick wrote:

> Hello everybody,
> 
> I'm developing a software on a Cyclone FPGA. However now we are think
> about the security of the device : i mean, the code is stored on a
> flash extern to the Cyclone. What can prevent someone from copying the
> data on this flash and clone the product we are doing ?
> 
> In Quartus there is a security bit that made me fell confortable,
> however it works only with a Max device.
> 
> What solution do I have to protect our software ?

Wait for the Cyclone2 with built in Flash, if I'm right.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 77630
Subject: Re: Programming and copyright
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 12 Jan 2005 14:32:34 -0800
Links: << >>  << T >>  << A >>
Rene Tschaggelar wrote:
>
> Wait for the Cyclone2 with built in Flash, if I'm right.
>
> Rene

Hmmm... Does this mean that Spartan parts with embedded Flash are also
around the corner? That would really make by wet dreams complete ;)

--
PabloBleyerKocik /"I believed that people would become programmers
pbleyer        / and not need companies as much. You can see how
@embedded.cl / laughable that was." -- Steve Wozniak


Article: 77631
Subject: Re: Signaltap - Finding Nodes - FSM state register
From: "Subroto Datta" <sdatta@altera.com>
Date: 12 Jan 2005 17:10:03 -0800
Links: << >>  << T >>  << A >>

Nicolas Matringe wrote:

> Look at the compilation report, in the "analysis & synthesis/state
> machines" section. There you'll find how your states are encoded and
the
> associated FF names


To add to Nicolas's reply here are the details.

The Analysis & Synthesis report has a section on state machines that
lists the encoding chosen for each state machine and the names of the
FFs that implement the state machine. In Quartus II 4.1 the state
machine bits will be named based on the name of the state register in
the VHDL design, with a suffix ~<num> for each bit. For example, you
might have a VHDL state machine coded using an enumerated type such as
this:

TYPE STATE_TYPE IS (s0, s1, s2);
SIGNAL state   : STATE_TYPE;

The Analysis & Synthesis report from your design (the .map.rpt file)
will look something like this:

+-------------------------------------------+
; State Machine - state                     ;
+----------+----------+----------+----------+
; Name     ; state~18 ; state~17 ; state~16 ;
+----------+----------+----------+----------+
; state.s0 ; 0        ; 0        ; 0        ;
; state.s1 ; 0        ; 1        ; 1        ;
; state.s2 ; 1        ; 0        ; 1        ;
+----------+----------+----------+----------+

This tells you that the state machine has been implemented with three
FFs, state~18, state~17 and state~16, and the state machine is in state
s0 when (state~18, state~17, state~16) has the value (0,0,0). Another
way of explaining this is that the state machine is implemented using a
one-hot encoding with the reset bit inverted: the state machine is in
state s0 when state~16 is 0; in state s1 when state~17 is high, and in
state s2 when state~18 is high.

The suffix numbers (~18, ~17, ~16) can change when other logic in your
design changes, which can cause SignalTap to lose the connection to the
states. In Quartus II 4.2 the state names are improved for one-hot
state machines: the state name will be used as a suffix. So Quartus II
4.2 would name the same FFs state.s2, state.s1, state.s0, with the
state machine being in state s0 when FF state.s0 is low.
Hope this helps,

Subroto Datta
Altera Corp.


Article: 77632
Subject: Re: General Question - Which FPGAs can support partial run-tim reconfiguration?
From: "Peter Alfke" <peter@xilinx.com>
Date: 12 Jan 2005 17:29:47 -0800
Links: << >>  << T >>  << A >>
Your list is correct, but XC6200 is a dead family ( neither physically
available nor supported by Xilinx)
All Virtex family members are partially reconfigurable. You can
reconfigure these parts on a Frame by Frame basis. Before Virtex-4, a
frame stretched "vertically" across the chip, with 22 frames per column
of CLBs.(Different frame length for different chips)
In Virtex-4, the frames are shorter, giving you a finer granularity of
dynamic reconfiguration.
In all Virtex devices, a frame is changed instantly (the shift-in
operation is transparent), but when multiple frames are reconfigured,
that is a sequential operation, and the user must take care of the
in-between situations.
Hope this helps.
Peter Alfke, Xilinx Applications.


Article: 77633
Subject: Re: Programming and copyright
From: "Peter Alfke" <peter@xilinx.com>
Date: 12 Jan 2005 17:40:08 -0800
Links: << >>  << T >>  << A >>
As Nick Weaver explained, you have to assess the budget that your enemy
can expend on his nasty effort. Fuses, antifuses, and EEPROM bits offer
limited protection.  Volatile storage ( with battery back-up) gives
much stronger protection, as everybody "in the know" would agree.
Finally, against the resources of the former KGB or present CIA, or
their counterparts, there may be no complete security. But I hope that
is not your real concern.  ;-)
Peter Alfke


Article: 77634
Subject: Re: Programming and copyright
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 13 Jan 2005 15:08:04 +1300
Links: << >>  << T >>  << A >>
Nick wrote:
> Hello everybody,
> 
> I'm developing a software on a Cyclone FPGA. However now we are think
> about the security of the device : i mean, the code is stored on a
> flash extern to the Cyclone. What can prevent someone from copying the
> data on this flash and clone the product we are doing ?
> 
> In Quartus there is a security bit that made me fell confortable,
> however it works only with a Max device.
> 
> What solution do I have to protect our software ?

Depends on the area of risk, and the product's operation.

  If you are worried about production creep/midnight runs at
an offshore manufacturer, then you need some portion that
you program in house, and supply.

  If you are worried about a 'knock off clone', then you need to
protect up to the cost of them duplicate-engineering, as opposed
to reverse engineering.
  You can include a small uC, or a CPLD, to decrypt the bitstream,
and also provide some co-processing to the FPGA : you then
increase the skill level considerably, way above simple chip-copying.

  You can get FLASH FPGAs from ACTEL, plus there are the MAX II CPLDs
and there are FLASH devices from Lattice, with more imminent, so there
are a number of choices to secure the product, (all of which will
probably need more than one device).

-jg


Article: 77635
Subject: Re: Programming and copyright
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 12 Jan 2005 19:19:44 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> As Nick Weaver explained, you have to assess the budget that your enemy
> can expend on his nasty effort. Fuses, antifuses, and EEPROM bits offer
> limited protection.  Volatile storage ( with battery back-up) gives
> much stronger protection, as everybody "in the know" would agree.
> Finally, against the resources of the former KGB or present CIA, or
> their counterparts, there may be no complete security. But I hope that
> is not your real concern.  ;-)

Wasn't there a story about some TLA (three letter agency)
putting taps on fiber optic cables on the bottom of the ocean?
(Without either end noticing.)

How does that compare to reading battery backed FPGA's?

-- glen


Article: 77636
Subject: Re: Exportability of EDA industry from North America?
From: Richard Griffith <rgriffith@istop.com>
Date: Wed, 12 Jan 2005 23:00:04 -0500
Links: << >>  << T >>  << A >>
EDA wannabe wrote:
> Some colleagues and I were discussing the situation with the high tech
> industry, with jobs moving out of North America.  This has hit circuit
> designers hard, especially those in digital.  Can EDA tool development
> be expected to follow suit, is has it already happened?  If not, what
> are the factors that differentiate it from design work to make it less
> exportable?  Comments are also welcome for automatation of methodologies
> for programmable system-on-chip e.g. reconfigurable processor arrays.
> 

I would say it is time for the EDA industry to flip to open source code.
All the fabless startups are just killed by the tool expenditures they 
need to make.

1. OpenSource simulator:
	analog -> spice
	digital->?
	mixed->?
2. Schematic capture
3. Netlister/code capture. I don't think even the professional EDA tools 
have this right. Why does multiplier.sch or multipler.c have only 1 
view. Why not version control/views built into the editor where the 
netlister can be set to grab different versions or the editor highlight 
the delta's. A configuration view that sees all views from system level 
to extracted with all their associated versions and tags.
4. Layout editor/GDS viewer. How many polygons does a video game push?
5. Schematic/Layout/System viewers that allow properties to attach. 
Wires colored by current, sized by voltage. Visualization tools.

I think the industry needs open source tools.



Article: 77637
Subject: Re: (d)ram interface
From: "Jan Gray" <jsgray@acm.org>
Date: Thu, 13 Jan 2005 05:31:50 GMT
Links: << >>  << T >>  << A >>
One can build a nice 24Rx64C text VGA controller including a 96 character 
5x8 (out of 6x10) pixel character generator ROM in a single18 kbit BRAM; or 
 >40Rx80C + char gen ROM in two BRAMs -- and a few tens of LUTs.  This makes 
a great SoC debugging aid yet consumes as few as 3 I/Os (hsync_n, vsync_n, 
pixel).

Jan Gray



Article: 77638
Subject: Re: Programming and copyright
From: Nick <char-DONTBUGME-les@YY.iiedotcnam.france>
Date: Thu, 13 Jan 2005 06:50:31 +0100
Links: << >>  << T >>  << A >>
On Thu, 13 Jan 2005 15:08:04 +1300, Jim Granville
<no.spam@designtools.co.nz> wrote:

>Depends on the area of risk, and the product's operation.
>
>  If you are worried about production creep/midnight runs at
>an offshore manufacturer, then you need some portion that
>you program in house, and supply.
>
>  If you are worried about a 'knock off clone', then you need to
>protect up to the cost of them duplicate-engineering, as opposed
>to reverse engineering.
>  You can include a small uC, or a CPLD, to decrypt the bitstream,
>and also provide some co-processing to the FPGA : you then
>increase the skill level considerably, way above simple chip-copying.
>
>  You can get FLASH FPGAs from ACTEL, plus there are the MAX II CPLDs
>and there are FLASH devices from Lattice, with more imminent, so there
>are a number of choices to secure the product, (all of which will
>probably need more than one device).


The problem is the cost of developpement is realy high, and the price
we sell our product is high as well. So the engineering cost for the
clone won't be high compared to the selling price.

Having read some documentation about it on the newsgroups, it seems
that nothing can really protect the design, and even the biggest
security can be break. That's bad.

Using a volatile sram + battery to keep the code scares me because i
need to be sure that the product work in more than 10 years. 
I think I'll settle for an external prom chip and a special hanshake.

Thank you for all your answers.

Nick

Article: 77639
Subject: Re: Modelsim Aliases
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 12 Jan 2005 23:15:24 -0800
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> I would like to spilt up information on a memory data bus into its
> components.  Some text have suggested aliases as a way of doing it. Is it
> the best way?

Consider declaring each vector part separately.

> Modelsim doesn't seem to show the aliases that I define

That's the way it is.


   -- Mike Treseler

Article: 77640
Subject: Constraints to partial modules,modular design
From: "fire" <xk_ch@163.com>
Date: 12 Jan 2005 23:21:09 -0800
Links: << >>  << T >>  << A >>
Hi,

Supposing a top-level design was comprised of module A,module B,module
C & module D. Now I wanna apply modular design method to the design.
In the top-level design synthesis process,only module A & module B
synthesized as black boxes and module C & module D expanded.Then apply
the modular design flow.Is this modular design method fasible?
Thanks,

fire


Article: 77641
Subject: Re: Configuration devices
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 12 Jan 2005 23:58:07 -0800
Links: << >>  << T >>  << A >>
The problem has been solved by the use of a compact flash memory card
on the board which is going to be used to hold the configuration data
and the results from the signal processing which can both be transfered
by tcp/ip.
So thanks for all the advice but the solutuion we are going with is a
good one and its easy to implement some  simple ide driver code for the
8052.


Article: 77642
Subject: Re: Starting with xilinix and Linux
From: Michael Schuster <schusterSoccer@enertex.de>
Date: Thu, 13 Jan 2005 09:52:59 +0100
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:

> Michael Schuster <schusterSoccer@enertex.de> wrote:
> You don't give basic information:
> - Does your wine installation run basic programs ( e.g. notepad) ?
>   That's a sign that it is at least somehow configured sensible.
> - Does it run more challenhing programs
> - What version is it?
> - And most important: What exactly doesn't work when you install Webpack?
>   Does it unpack the installation files?
>   If not, unzip manual like
> xilinx-download> unzip  6_3_02i_pc.exe
>   best in its own directory
>   Can you start setup.exe in that directory
>   ...
> 
> Bye
I've SuSE 9.2 prof. 
Yes, with wine notepad runs.  
$ wine --version
Wine 20050111

Well webpack is extracted and installed via wine directly from the exe-file.
I had a debug message which I can't interprete. After runing wine ise I had
to install mfc42.dll and msvcp60.dll, cause wine didi't find these.  

If I now run 
$ wine ise 

I now get a hundred 

 fixme:heap:RtlWalkHeap not fully compatible 

and then 

 fixme:seh:EXC_RtlRaiseException call (from 0x4102f9ba) to unimplemented 
function MFC42.DLL.6571
 wine: Unhandled exception (thread 000b), starting debugger...
 WineDbg starting on pid 0xa
 Unhandled exception: unimplemented function MFC42.DLL.6571 called in 32-bit 
code (0x401c18d8).
 In 32 bit mode.
 Register dump:
 CS:0073 SS:007b DS:007b ES:007b FS:003b GS:0033
 EIP:401c18d8 ESP:406efc08 EBP:406efc60 EFLAGS:00000202(   - 00      - - I1)
 EAX:000019ab EBX:401f1b8c ECX:11d2e944 EDX:600012b4
 ESI:406efc08 EDI:40def129
 Stack dump:
 0x406efc08:  80000100 00000001 00000000 4102f9ba
 0x406efc18:  00000002 410727d2 000019ab 406efc34
 0x406efc28:  404f3bcd 41160000 411ca158 406efc64
 0x406efc38:  41174b83 41160000 411ca158 406efc54
 0x406efc48:  411b8247 411ca158 00000002 42660010
 0x406efc58:  40de9620 41079020 406efca0 4102f9ba
 Backtrace:
 =>1 0x401c18d8 stub_entry_point+0x58 in ntdll (0x406efc60)
   2 0x4102f9ba 1920+0x9a in libstg_foundation (0x406efca0)
   3 0x410624d6 in libstg_foundation (+0x424d6) (0x406efccc)
   4 0x401c0ee2 call_dll_entry_point+0x12 in ntdll (0x406efce4)
   5 0x401c4093 MODULE_InitDLL+0x233 in ntdll (0x406efd7c)
   6 0x401c42fb process_attach+0x11b in ntdll (0x406efdb4)
   7 0x401c424e process_attach+0x6e in ntdll (0x406efdec)
   8 0x401c424e process_attach+0x6e in ntdll (0x406efe24)
   9 0x401c424e process_attach+0x6e in ntdll (0x406efe5c)
   10 0x401c4c39 LdrInitializeThunk+0x389 in ntdll (0x406eff20)
   11 0x4050522b start_process+0xbb in kernel32 (0x406efff4)
   12 0x4003fde1 wine_switch_to_stack+0x11 in libwine.so.1 (0x00000000)
 0x401c18d8 stub_entry_point+0x58 in ntdll: subl $4,%esp
 Wine-dbg>WineDbg terminated on pid 0xa
 wine client error:b: write: Ungültiger Dateideskriptor



Also I have crossover (2.1.0) with msoffice97 installed. But here I didn't
get it running, either. I downloaded the latest demo from codeweavers and
tried to install with this. But it didn't work. 

Thanks for more hints

Michael 

-- 
Remove the sport from my address to obtain email
www.enertex.de - Innovative Systemlösungen der Energie- und Elektrotechnik

Article: 77643
Subject: Re: Starting with xilinix and Linux
From: Michael Schuster <schusterSoccer@enertex.de>
Date: Thu, 13 Jan 2005 09:58:42 +0100
Links: << >>  << T >>  << A >>
B. Joshua Rosen wrote:
> I have a page that provides information on running Xilinx tools on Linux
> with wine. I stopped maintaining it when Xilinx started offering native
> Linux tools. However you should fine it helpfulfor running webpack undre
> wine.
> 
> http://www.polybus.com/xilinx_on_linux.html
Thanks for your reply. 

The hint here with 
[version]
 "windows" = "win2k"
didn't make this runnig better. 

We think of buying the tools. But they told us: You can buy, but for SuSE
you won't get a guarantee that it'll work. But for this and the money
reason with still give wine a chance. 

Michael 
-- 
Remove the sport from my address to obtain email
www.enertex.de - Innovative Systemlösungen der Energie- und Elektrotechnik

Article: 77644
Subject: Re: Starting with xilinix and Linux
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 13 Jan 2005 09:02:14 +0000 (UTC)
Links: << >>  << T >>  << A >>
Michael Schuster <schusterSoccer@enertex.de> wrote:
> Uwe Bonnes wrote:


>  fixme:seh:EXC_RtlRaiseException call (from 0x4102f9ba) to unimplemented 
> function MFC42.DLL.6571

Those damned *d**ts building the webpack distribution forgot to include the
mfc library, also it is redistributable. Try to get a recent mfc42.dll and
copy tom the wine system directory.

Hope this helps
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 77645
Subject: Re: Starting with xilinix and Linux
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 13 Jan 2005 09:08:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
Michael Schuster <schusterSoccer@enertex.de> wrote:
> B. Joshua Rosen wrote:
> > I have a page that provides information on running Xilinx tools on Linux
> > with wine. I stopped maintaining it when Xilinx started offering native
> > Linux tools. However you should fine it helpfulfor running webpack undre
> > wine.
> > 
> > http://www.polybus.com/xilinx_on_linux.html
> Thanks for your reply. 

> The hint here with 
> [version]
>  "windows" = "win2k"
> didn't make this runnig better. 

> We think of buying the tools. But they told us: You can buy, but for SuSE
> you won't get a guarantee that it'll work. But for this and the money
> reason with still give wine a chance. 

So get the 60 day demo first and test on Linux. Here Foundation ( as a
europractice site license) worked fine with
with Suse 9.0, a short test now shows that this d*mn*d 
Wind/U X-toolkit produces an Error: wuDisplay: Can't open display

with 6.3.02

Downloading the the 03 service pack in the moment and investigating deeper.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 77646
Subject: Re: Programming and copyright
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Thu, 13 Jan 2005 09:31:09 GMT
Links: << >>  << T >>  << A >>
Hi Nick,

> Hello everybody,
> 
> I'm developing a software on a Cyclone FPGA. However now we are think
> about the security of the device : i mean, the code is stored on a
> flash extern to the Cyclone. What can prevent someone from copying the
> data on this flash and clone the product we are doing ?
> 
> In Quartus there is a security bit that made me fell confortable,
> however it works only with a Max device.
> 
> What solution do I have to protect our software ?
> 
> Best regards
> Nick

I suggest you read the following article:

http://www.altera.com/literature/wp/wp_m2dsgn.pdf

This uses a MAX II as a 'dongle'. The MAX II is - let's say - non-volatile
and generates a continuous stream of bits. The same algorithm runs in the
FPGA, and if there's a mismatch, the FPGA quits working.

I also have an unofficial whitepaper plus reference design that uses a MAX3
device to do something similar, albeit with a less cryptologically sound
algorithm. Contact me on bentw at chello dot nl if you want it. The gmail
address is a spam trap.

Best regards,


Ben


Article: 77647
Subject: Re: Starting with xilinix and Linux
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 13 Jan 2005 09:35:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

> Downloading the the 03 service pack in the moment and investigating deeper.

Didn't help, but the second proposal from Answer Record #20172:
"To work around this issue, try setting the $DISPLAY variable to either 
	<hostname>:0.0 or :0"

Setting to :0 let ISE start.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 77648
Subject: Re: Starting with xilinix and Linux
From: Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid>
Date: Thu, 13 Jan 2005 11:46:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2005-01-13, Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:
> So get the 60 day demo first and test on Linux. Here Foundation ( as a

Last time I tried, there wasn't a demo version for Linux (windoze only).
We nevertheless purchased ISE Alliance 6.3i. I'm using Debian Sarge
and I think it works in it as well as any distro including the officially
supported RedHat. That is, GUI is pretty slow (especially startup-time)
but usable. I succeeded crashing some less important GUI program
(xinfo probably) but going through the (windows) tutorial, the system
worked pretty much as expected.

Biggest problem was finding which program to run to get started;
I guess the answer is buried somewhere in the manual, but at least
"ise" command seems to start the Project Navigator.

Unfortunately as we haven't yet received the hardware (from another company)
I haven't yet used the ISE much.

> Wind/U X-toolkit produces an Error: wuDisplay: Can't open display

It doesn't support dot in the DISPLAY environment variable. I saw
somewhere the solution, which is
	 export DISPLAY=:0

> Downloading the the 03 service pack in the moment and investigating deeper.

I haven't downloaded any service packs yet, maybe the GUI
is faster with them.

Article: 77649
Subject: fpga board with onboard 2 ethernet PHY chips?
From: "Neo" <amitoj.cheema@gmail.com>
Date: 13 Jan 2005 04:26:07 -0800
Links: << >>  << T >>  << A >>
Hi,
I'm looking for a FPGA board which supports two ethernet PHY chips. Any
suggestions? A Virtex-family device would be preferable.




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search