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http://members.aol.com/ucimicromouse/index.htm One robot that uses Spartan IIE FPGA.... Austin Valli wrote: > Hi, > > What FPGA architecture is more suitable for the Robots, which involves > Pattern recognition (also partial configuration & more than 150k) and > lot of control logic generation. > > Or, Is DSP prefferable for this? > > Regards, > Valli.Article: 60151
INVALIDANTISPAM@aol.com (John K.) wrote in message news:<bj9sb1$gc4bj$1@ID-50260.news.uni-berlin.de>... > Hello people, > > I am strictly a schematic user, please don't turn this thread > into a "but HDLs are really better!!". > I'd like to get a new hobby, i.e. to design some (simple for > now, but then also complex) devices on a SpartanII 300E board. > The kind of devices I'd like to design range from TTL style at > the begin, till, someday, complete CPUs and simple multimedia > devices (e.g. graphic chips as seen in the '80s home computers). where is the problem? just use ISE schematics entry if you want so its available and you can generate FPGA bitstream out schematics exactly as you would from hdl designs. and you can also do simulation if you need. antti http://www.graphord.com/forumArticle: 60152
Jon, Still in production, still shipping to customers. Contact your local sales rep to talk about stocking and pricing. The fact that the newer parts cost a lot less is because they are smaller die for the same functionality. If you think about it, the $ per FPGA gate has been dropping pretty drastically now for many years. In Spartan 3, we are now down to ~100 uCents per gate range. The XCS30 can no hope to compete for this being in such an old technology. Seven years ago, ~$40 for 30K "gates" was a great price.... Austin Jon Elson wrote: > Hello, > > What is the status of the old, 5V Spartan family from Xilinx? > I have 2 current products that use them. (XCS10-3PC84 and > XCS30-3TQ144) I suddenly noticed all the distributors either > no longer list these parts or indicate they are special order. > Newark has a part that matches the part number, but lists > the manufacturer as Mux-Lab Inc, and the price is outrageous, > $42.48, with no discount at any quantity. I got them just a couple > of months ago for $16 in small quantity. > > I was assured by somebody at Xilinx, possibly Peter Alfke, that > the 5 V Spartan line would continue to be available for a long > time. I suppose if they sold off the masks to an obsolete chip > supplier, that is "still available". > > JonArticle: 60153
Hello, When you say, "Why doesn't it work?" it would be helpful to know what the failure mechanism is... I wonder if this is a lab assignment gone wrong, or an astute application of reverse psychology to get an answer to a homework question? ;) For what it's worth, I think you might go back and review how to describe a synchronous counter. Your code may simulate properly, but a synthesis tool may have a difficult time implementing it. You could design a synchronous counter with no clock enable, where the switch signal is used as the clock, assuming you debounce it properly. Or, you could design a synchronous counter that is clocked from a free-running clock, and you use the switch signal as a clock enable, assuming you debounce and synchronize it properly, and then detect transitions on the signal across clock cycles to generate a single "press" event that will allow the counter to increment only one time in response. Eric Simone Winkler wrote: > > Hello! > > I'm trying to build the following thing: a 7-segment-led > that increases its value every time a switch is pressed. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity sevsegment is > Port ( > clk_i: in std_logic; > sevseg : out std_logic_vector(6 downto 0); > reset : in std_logic; > switch: in std_logic); > end sevsegment; > > architecture Behavioral of sevsegment is > signal sevseg_s: std_logic_vector(6 downto 0); > begin > > process(reset,switch,clk_i) > variable counter: integer range 0 to 9; > begin > if clk_i'event and clk_i='1' then > if reset='0' then > counter:=0; > sevseg_s <= "1111110"; > elsif switch'event and switch='0' then > if counter<9 then > counter:=counter+1; > else > counter:=0; > end if; > case counter is > when 0 => sevseg_s <= "1111110"; > when 1 => sevseg_s <= "0110000"; > when 2 => sevseg_s <= "1101101"; > when 3 => sevseg_s <= "1111001"; > when 4 => sevseg_s <= "0110011"; > when 5 => sevseg_s <= "1011011"; > when 6 => sevseg_s <= "1011111"; > when 7 => sevseg_s <= "1110000"; > when 8 => sevseg_s <= "1111111"; > when 9 => sevseg_s <= "1111011"; > end case; > end if; > end process; > > sevseg <= sevseg_s; > > end Behavioral; > > Why doesn't it work? I know that "multiple clocks" are not > allowed, but i can't find any solution to solve my problem.Article: 60154
Ron Cline <Ron.Cline@xilinx.com> wrote in message news:<3F58C987.41B42E6F@xilinx.com>...
> rickman wrote:
> > There is no way to determine when a circuit is metastable or not.
>
> It is possible -- I did it once for a FF design for another company. It
> requires a separate, combinational output signal ("metastable flag-out").
> But, of course, there's no way to use this to kick the FF circuit itself out
> of metastability. All previous comments about this being a no-fix are true.
>
> The flag is generated by taking advantage of the fact that the latch going
> metastable has a cross-coupled gate with a known threshold point during
> metastability. A 2-input logic gate with a different threshold can detect
> that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
> design) threshold point.
Why can't you use this flag to generate another (delayed) clock to the
same FF? It would continue to retrigger itself until it was in a
stable state. If you ORed all of these flags together in a register
you would have a data valid output.
Nothin like async logic to get your blood flowing!
Tom
Article: 60155Tom Seim wrote: > > Ron Cline <Ron.Cline@xilinx.com> wrote in message news:<3F58C987.41B42E6F@xilinx.com>... > > The flag is generated by taking advantage of the fact that the latch going > > metastable has a cross-coupled gate with a known threshold point during > > metastability. A 2-input logic gate with a different threshold can detect > > that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by > > design) threshold point. > > Why can't you use this flag to generate another (delayed) clock to the > same FF? It would continue to retrigger itself until it was in a > stable state. This newly-created feedback loop would have a much longer metastable time-constant than had the original latch. Better to leave well enough alone, I think. > If you ORed all of these flags together in a register > you would have a data valid output. The flag wouldn't indicate a logic state (valid or not), only the presence of metastability. The logic state is indeterminant while the flag is active. - RonArticle: 60156
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bj9gjm$m55$1@sunnews.cern.ch>... > Hi, > > When using QuartusII 2.2 how can someone include a design file which is made > in another project? > > I have tried by using the "Add/Remove files in project" to include a Block > diagram file I have made in a different project and I set the compiler to > focus onto that file but it gives me the error: "Node instance inst > instantiates undefined entity altsyncram0". > I understand that it have not found the files that were created by using the > megafunction. One option is to go to that folder and start copying the files > into this project's folder. But I am sure this is not the best way. > > I thing I read everything in the help files about hierarchies but I haven't > found somewhere that describes this.. In fact you must have to put in "Add/Remove files in project" the files created by the megafunctions too (this files aren't in a common library because you just create a specific version of a generic project), when you use a lot of megafunctions in projects this work becomes tedious and inefficient (it is better to copy the files to the new folder). But You have to do it only if you want making changes in the project. If you don't need to make changes in the design you can use a 'vqm' version of the project and put only this file on the "Add/Remove files in project" . To do it, in the project that you want to use, select in assigments/settings/compiler settins/synthesis the option "save a node level (...) (Verilog Quartus Mapping File)", and recompile. You can instantiate the *.vqm to your vhdl or If You are using the squemathic editor (block desig file), create a symbol to the *.vqm and put it on the block desing file. I hope it could help you in something, IvanArticle: 60157
"Jon Elson" <elson@pico-systems.com> wrote in message news:3F58C665.4070503@pico-systems.com... > Hello, > > What is the status of the old, 5V Spartan family from Xilinx? > I have 2 current products that use them. (XCS10-3PC84 and > XCS30-3TQ144) I suddenly noticed all the distributors either > no longer list these parts or indicate they are special order. > Newark has a part that matches the part number, but lists > the manufacturer as Mux-Lab Inc, and the price is outrageous, > $42.48, with no discount at any quantity. I got them just a couple > of months ago for $16 in small quantity. > > I was assured by somebody at Xilinx, possibly Peter Alfke, that > the 5 V Spartan line would continue to be available for a long > time. I suppose if they sold off the masks to an obsolete chip > supplier, that is "still available". I think that Farnell stocks them at a reasonable price, for small quantities. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 60158
Austin Lesea wrote: >Jon, > >Still in production, still shipping to customers. > >Contact your local sales rep to talk about stocking and pricing. The >fact that the newer parts cost a lot less is because they are smaller >die for the same functionality. > Oh, I understand this! For electrical reasons, I felt that I needed 5 V compatibility, so designed it with the 5V parts. > If you think about it, the $ per FPGA >gate has been dropping pretty drastically now for many years. In >Spartan 3, we are now down to ~100 uCents per gate range. The XCS30 can >no hope to compete for this being in such an old technology. Seven >years ago, ~$40 for 30K "gates" was a great price.... > > Well, the Xilinx web pages show no mention of Spartan without the XL, II, etc. and a search of XCS10 comes up with nothing. Digi-Key used to stock the XCS10 through XCS40 or so, and other distributors also had them in their on-line catalogs. Now, when I search at various distributors, I either get no match or "special order". I'll have to talk to some people. Also, who is "MuxLab, Inc."? They are apparently supplying something to Newark with the part number XCS10-3PC84C, and call it a CMOS-CPLD-xxx or something like that. Is that a real second source? Or, is MuxLab just emptying out their warehouse full of old parts? Thanks, JonArticle: 60159
John K. wrote: >Hello people, > >I am strictly a schematic user, please don't turn this thread >into a "but HDLs are really better!!". >I'd like to get a new hobby, i.e. to design some (simple for >now, but then also complex) devices on a SpartanII 300E board. >The kind of devices I'd like to design range from TTL style at >the begin, till, someday, complete CPUs and simple multimedia >devices (e.g. graphic chips as seen in the '80s home computers). > >I downloaded and installed Webpack, but I've been very >disappointed. It looks totally HDL oriented to me.. maybe >I'm wrong, but I couldn't see there what I'm looking for. > >What I'm looking for (pardon the redundancy) is a simple >but yet powerful editor that will let me enter a schematic >(NAND gates, Flip-Flops, etc..); will also let me make new >devices from schematics (i.e. macros!); then *possibly* >simulate all of that; and then finally burn it into my >SpartanIIE chip, letting me also setup various features >of the FPGA (e.g. how to load the initial contents of >block RAM, etc..). > > I have been using Xilinx's ISE for a while. I used their Foundation before that. I was really mad at them for changing schematic vendors so old schematics were no longer compatible with the newer software. Also, the Aldec schematic entry tool is, to me, a totally horrible nightmare. I just find it works against me so much of the time. I have been using Protel 99SE for some time, and find its schematic entry much better. Protel has a CPLD/FPGA tool, but it is pretty rough around the edges. I tried to use it for Xilinx CPLDs and FPGAs, but there are some problems generating bitstreams for the newer and larger devices. I tried some time ago to port XNF files from Protel to Xilinx, and ran into problems. Recently, I got mad again, and now that ise takes edif files, I tried to make it work again. Well, Protel's idea of EDIF format is not identical to Xilinx's, but it is close enough that I think a parsing/converting program could be thrown together fairly easily to make it work. I'm pretty sure that Protel's EDIF format is actually just WRONG, as net names have & in front of them in some places and not others. Just deleting all &'s fixes that. I have actually pushed a schematic through and hand edited the EDIF file, and got Xilinx to accept it and produce translation and map reports that look right. So, if you have any schematic capture software that has the Xilinx library primitives in it, and can put out an EDIF file, you might want to try that out. I'm pretty sure all the Xilinx tools can accept an EDIF, now. JonArticle: 60160
John K. wrote: >I think in a "object oriented" way.. for example, I make Flip-Flops from >NAND gates. > Depending on how you do this, this could prevent you from using the physical FFs already in the Xilinx architecture. That would be a major mistake, as the performance, clock skew and density would suffer drastically. > So I get a Flip-Flop object. I make registers/latches from >Flip-Flops, so I get a Latch object. I mean, complexity can naturally >get encapsulated and encapsulated, till you have a whole ALU, or a whole >processor, etc.. and your schematic always looks simple (circuits and >subcircuits encapsulated into virtual devices). > This is what most people do with schematics. There's no need to have thousands of pages of nearly identical structures, you make a hierarchy. In fact, a number of parts in the Xilinx libraries are not primitives, directly, they are hierarchical constructs that contain instances of primitives. All of the multi-bit counters, latches, comparators, etc. are made this way. >I don't have much experience with current schematic software (I used >mostly my own.. nothing fancy anyway, but worked well for encapsulating >at least), but I see no reason why schematic based (using macros) should >be any slower or more confusing than HDLs? > >I can only think about one problem: simulation gets slower and slower. >But neither this must be true: if simulating a whole Latch via NAND >gates may be slow, after I know it works well and I have its timing >characteristics known, I can encapsulate also them into the "black >box" and simulation of a Latch will be very quick.. having just to >simulate the function (and delays) from input to output. > > You need to know that after the manufacturer's tools get done munching on the 1-to-1 boolean equations that are extracted from your schematic, the actual logic will bear little resemblance to what you created at the schematic level. All sorts of optimizations are taken with any chunk of combinatorial logic to fit it best into the particular device architecture (4-input logic blocks, for instance). If you have to follow through the final equations to figure out how a signal gets from here to there, you will see it does not resemble what you started with. This can have some significant ramifications if you expect to solve timing problems by throwing extra gates in somewhere. Anything extra will be optimized out. >HDL's IMHO are very confusing, hardware wise. A schematic is much more >natural and intuitive. IMHO of course. > >On the other hand the non-intuitive, too abstract HDLs will make you >design things that then in silicon are very inefficient.. will not >give you a good "big, real picture" of what you're doing, etc.. > > Well, I'm pretty impressed with what Xilinx has done in their translation, optimization and place&route software. They get good packing of a lot of stuff into the chips, I've never had an error that wasn't actually my fault, and the stuff just works. I have done some mixed-mode designs, like a schematic job with binary-to-gray code and vise-versa in HDL, because that particular function is a serial string, and just is very easy and natural to code in HDL form. I have a little toy project that I could do in schematic, but I'm going to try it entirely in VHDL just to see how it goes. JonArticle: 60161
Hi Allan: you should be able to black box the thing, and use it as a lib Andrew Allan Herriman wrote: >On Fri, 5 Sep 2003 09:39:39 +0200, "Thomas Oehme" <toehme@freenet.de> >wrote: > > > >>Hallo, >>this may be an typical newbie-question(sorry). >> >>My project is described in vhdl, but i have an working component in verilog >>i want to use within. >>How will i get the component in my project ? >> >> >>thanks for any answer >> >>Thomas Oehme >> >> > >In ISE 5.x, you can only use one of VHDL and Verilog at a time, using >the normal "flow". > >Workarounds: > >1. Use a compiler such as Synplify or Leonardo. > >2a. Rewrite your Verilog in VHDL. >2b. Rewrite your VHDL in Verilog. > >3. Wait until ISE 6.1 (coming RSN), which supposedly will support >VHDL and Verilog at the same time. > >4. Compile your Verilog to EDIF (or whatever) as a separate step, and >instantiate that in your VHDL as a black box. Compile your VHDL >*without* the Verilog module as part of the list of files to compile. >The back end tools (ngdbuild) will patch the already compiled Verilog >module into the hole left in the VHDL. >Note that this will require two "projects." > >Regards, >Allan. > >Article: 60162
I can sympathize. I was in a multi-day argument thread a couple months back with an HDL zealot. I, too, am a schematic based designer primarily because the currently trendy methods offer no advantages, and have numerous down-sides (like creating legions of people calling themselves "designers" who have no idea how the circuit they described in software is actually implemented). But, that is a very stale argument. Both camps like what they like. I have stayed with Altera tools for more than a decade because they are vastly superior for a schematic based design. I have the latest ISE tools as well, and the schematic capture tools are state-of-the-art -- for the year 1985. I can't stand using their tools, and if I am forced into using a Xilinx part, I do the design in the Altera tools first, then transfer it. It is vastly quicker and easier than dealing with the primitive Xilinx schematic tools. They don't have an integrated simulator either, which truly bites. These tools seem like bits and pieces cobbed together into a not-so-great package. The free Altera tools will provide you the easiest route to design with schematics. All the features of the full paid-for Quartus tools are available in the free web tools, including the integrated simulator. For schematic designers, the Altera simulator is excellent and intuitive. The free tools don't support all their devices, which is the major difference from the version you pay for -- at least as far as I'm concerned. Another advantage with Altera is the new Cyclone family. You can pretty much get all those parts now. You don't have to wait until next year to get production versions of these fast, inexpensive parts and start at about $17 (quantity one price for a 1C3 -8 speed grade). What's not to like? This is the way to go for schematic lovers. "John K." <INVALIDANTISPAM@aol.com> wrote in message news:bj9sb1$gc4bj$1@ID-50260.news.uni-berlin.de... > > Hello people, > > I am strictly a schematic user, please don't turn this thread > into a "but HDLs are really better!!". > I'd like to get a new hobby, i.e. to design some (simple for > now, but then also complex) devices on a SpartanII 300E board. > The kind of devices I'd like to design range from TTL style at > the begin, till, someday, complete CPUs and simple multimedia > devices (e.g. graphic chips as seen in the '80s home computers). > > I downloaded and installed Webpack, but I've been very > disappointed. It looks totally HDL oriented to me.. maybe > I'm wrong, but I couldn't see there what I'm looking for. > > What I'm looking for (pardon the redundancy) is a simple > but yet powerful editor that will let me enter a schematic > (NAND gates, Flip-Flops, etc..); will also let me make new > devices from schematics (i.e. macros!); then *possibly* > simulate all of that; and then finally burn it into my > SpartanIIE chip, letting me also setup various features > of the FPGA (e.g. how to load the initial contents of > block RAM, etc..). > > I have some money to invest, eventually, if the software > is not free.. but I'd like to know all the options before. > > Please.. can anybody shed some light? I'm very confused > and lost.. > > Greets, > John >Article: 60163
EDK 3.2 did have synchronization problems. They have been solved in the EDK 6.1i release which should be out in about a month. Steve Antti Lukats wrote: >>Thank you all. That helped me some, but I am still getting CRAZY!!! >>Whenever I change something and tries to redraw the PBD window it just >>change my changes back to the original and nothing happens!!! Could I >>somehow switch this feature off in the EDK? >> >> > >I found the PBD 200% useless, so doing all modifications in add/edit cores >dialog. After closing it I always say 'regenerate' it will redraw PBD >then I close PBD and say overwrite MHS > >it works that way but agree is ANNOYING, no idea how to disable that >PBD update ... > >antti >http:/www.graphprd.com/forum > >Article: 60164
This was beat to death a few months ago. No one solution, but lots of suggestions. Check Google. "Thanassis Roubies" <aroubies@hotmail.com> wrote in message news:6cc54b63.0308310208.422d98ac@posting.google.com... > Problem Description: > --------------------------------------- > I have created the parallel cable III from the design that is online > at the xilinx website. i am trying to configure my xc95108 but i cant > and i receive an error message > > Error Message: > --------------------------------------- > Error: impact:1210 - '1':Boundary scan chain test failed at bit > position '1'. a problem may exist in the hardware configuration..... > > My parallel cable is very short,and my parallel port works perfectly > fine,since the printer is working. i don't have the cable over a > monitor. i am in despair. i don't know what to do. if i don't program > my CPLD i can't go on. could anyone help?Article: 60165
Avnet has some of them in stock - but they are expensive. Does anyone know of a comprehensive site for obsolete Xilinx part numbers (I used to remember where the obsolete - EOL - parts were listed on the xilinx web page). I would guess they are not makeing many, so die fab time is expensive and the parts are thus expensive - I can't find a LTB notice at http://www.xilinx.com/bvdocs/notifications/chronology.pdf, so I would guess that they are still making them. Also, does anyone know who they sell their dies to - Rochester? Andrew Jon Elson wrote: > Hello, > > What is the status of the old, 5V Spartan family from Xilinx? > I have 2 current products that use them. (XCS10-3PC84 and > XCS30-3TQ144) I suddenly noticed all the distributors either > no longer list these parts or indicate they are special order. > Newark has a part that matches the part number, but lists > the manufacturer as Mux-Lab Inc, and the price is outrageous, > $42.48, with no discount at any quantity. I got them just a couple > of months ago for $16 in small quantity. > > I was assured by somebody at Xilinx, possibly Peter Alfke, that > the 5 V Spartan line would continue to be available for a long > time. I suppose if they sold off the masks to an obsolete chip > supplier, that is "still available". > > Jon >Article: 60166
Based on the message it looks like altsyncram0 is a part of the "different" project. You have one of two choices: 1. Copy all files used by the different project into the new project directory or 2. Add the "different" project directory as a user library in the new project. You can do this from the Assignment->Settings->Files & Directories->User Libraries dialog. Hope this helps. - Subtotal Data Alter Corp. "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:bj9gjm$m55$1@sunnews.cern.ch... > Hi, > > When using QuartusII 2.2 how can someone include a design file which is made > in another project? > > I have tried by using the "Add/Remove files in project" to include a Block > diagram file I have made in a different project and I set the compiler to > focus onto that file but it gives me the error: "Node instance inst > instantiates undefined entity altsyncram0". > I understand that it have not found the files that were created by using the > megafunction. One option is to go to that folder and start copying the files > into this project's folder. But I am sure this is not the best way. > > I thing I read everything in the help files about hierarchies but I haven't > found somewhere that describes this.. > > >Article: 60167
> Use a PLL to double the clock if need be. > > > What do you suggest? > > Take the bull by the horns and design out the latches. > Hi Mike, I think you are correct! This is the only one solution. Thank you, AndreaArticle: 60168
"John_H" <johnhandwork@mail.com> ha scritto nel messaggio news:nK26b.35$X11.9145@news-west.eli.net... > If you need a logic low when there are no drivers, either > add the additional > circuitry to drive a logic low when no selects are active > *or* invert the > logic so your re-inverted TBUF defaults to low when there > are no drivers and > settles conflicts with a logic-high. What happens if you use VHDL's resolved signals (i.e. specifying at HDL level the behaviour of bus conflicts)? It is automatically added something like you described, or resolved signals are just for simulation and don't work with "real" devices? -- LorenzoArticle: 60169
http://www.opencores.org/projects/cpugen/Article: 60170
"Giovanni Ferrante" <gferrante@opencores.org> ha scritto nel messaggio news:tLk6b.85489$sj6.1620419@tornado.fastwebnet.it... > http://www.opencores.org/projects/cpugen/ It seems very interesting. BTW, make the links on the home page "clickable"! -- LorenzoArticle: 60171
Ron Cline wrote:
>
> rickman wrote:
> > There is no way to determine when a circuit is metastable or not.
>
> It is possible -- I did it once for a FF design for another company. It
> requires a separate, combinational output signal ("metastable flag-out").
> But, of course, there's no way to use this to kick the FF circuit itself out
> of metastability. All previous comments about this being a no-fix are true.
>
> The flag is generated by taking advantage of the fact that the latch going
> metastable has a cross-coupled gate with a known threshold point during
> metastability. A 2-input logic gate with a different threshold can detect
> that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
> design) threshold point.
And what happens to the output of this MS-detector gate if one of the
voltages is right at the threshold of the gate? Is it possible that the
output of the gate is at an intermediate voltage and is therefore
indeterminate?
Once again the problem comes from the measurement. There is no knife
that is sharp enough to split every hair known to man or nature.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 60172Austin Lesea wrote: > > Jon, > > Still in production, still shipping to customers. > > Contact your local sales rep to talk about stocking and pricing. The > fact that the newer parts cost a lot less is because they are smaller > die for the same functionality. If you think about it, the $ per FPGA > gate has been dropping pretty drastically now for many years. In > Spartan 3, we are now down to ~100 uCents per gate range. The XCS30 can > no hope to compete for this being in such an old technology. Seven > years ago, ~$40 for 30K "gates" was a great price.... Austin, I'm not tryin to quibble, I just want to understand what your dollar (or cents) figure means. At 0.0001 cents per gate, I get $0.40 for the XC3S400. That is a lot less than the quote I got a few weeks ago. Were you counting "real" gates instead of "user" gates? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60173
Hi! I' m working to a project a little difficult for me, 'cause for the first time I have to simulate a chess game using Fpga and verilog language. I need your advices! :-) Most of the project is realized. Final parts concern VGA display. I know I must work using HS and VS signals, but I don't know rightly how to simulate all that into verilog. I will be very happy if there's someone who can help me or suggest some books about VGA display. Thanx a lot! ^___^Article: 60174
Dear Abby:
You might find Keith Jack's book "Video Demystified" to be useful. If
you are code-centric, then find a copy of IBM's original "AT Technical
Reference Manual". Thats the 5x7 inch book in the blue cover.Barring that,
try Richard Ferraro's book "Programmers Guide to the EGA and VGA cards". And
lastly, if finding those is difficult or costly, try searching google with
some of the titles above as keywords and I suspect you will find a treasure
of information available.
Charles
"Abby" <abhigayl@hotmail.com> wrote in message
news:Tdn6b.34567$R32.1081585@news2.tin.it...
> Hi!
> I' m working to a project a little difficult for me, 'cause for the first
> time I have to simulate a chess game using Fpga and verilog language.
> I need your advices! :-)
> Most of the project is realized.
> Final parts concern VGA display.
> I know I must work using HS and VS signals, but I don't know rightly how
to
> simulate all that into verilog.
> I will be very happy if there's someone who can help me or suggest some
> books about VGA display.
> Thanx a lot! ^___^
>
>
>
>
>
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