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Messages from 60100

Article: 60100
Subject: Re: Flex6K configuration PROM
From: Jay <se10110@yahoo.com>
Date: Fri, 5 Sep 2003 01:21:46 -0500
Links: << >>  << T >>  << A >>
Hi Martin,

Thanks for your response.

In article <uy8x3ya5r.fsf@trw.com>, martin.j.thompson@trw says...
> Jay <se10110@yahoo.com> writes:
>=20
> > I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It look=
s=20
> > like the default choice is the EPC1441 which is not ISP or Flash.
> >=20
> > Altera makes the EPC2 which is Flash/ISP but for some reason it's not=
=20
> > compatible with FLEX6K. Anyone know why? Any way to get it to work with=
=20
> > the EPF6010A?
> >=20
>=20
> I used one a long time ago with a 6016A, worked fine.  What makes you
> think they won't work?

Are you sure it was an EPC2?

They make mention several times not to use it on the Flex 6K family:

http://www.altera.com/literature/ds/dsconf.pdf , page 9, note 1:

"Do not use EPC2 devices to configure FLEX 6000 devices." , and again on=20
page 12, etc.

I'm wondering why the Altera guys haven't followed up in the NG, they=20
seem to be pretty attentive as of late.

> The Altera ones were about =A320 last time I bought them. :-(

That doesn't sound too promising. How much were you paying for the=20
EPF6016As, if I might ask?

Thanks,
Jay.


Article: 60101
Subject: Re: Disable Pull up
From: "Giuseppe³" <miaooaim@inwind.it>
Date: Fri, 5 Sep 2003 08:22:57 +0200
Links: << >>  << T >>  << A >>
I don't sure to undestood your question but using the M0-M1-M2 pins is not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
> Someone knows like turn off the  "pull up" that the family "spartan2"
> connects for default to " tristate" placed inner lines in, from buffer "
> Tbuf"?
> I use "Xilinx ISE 4.1ģ" and  language "vhdl".
> thanks
>
>



Article: 60102
Subject: Re: Flex6K configuration PROM
From: antti@case2000.com (Antti Lukats)
Date: 4 Sep 2003 23:31:51 -0700
Links: << >>  << T >>  << A >>
Jay <se10110@yahoo.com> wrote in message news:<MPG.19c13883e34352259896dd@news.surfcity.net>...
> I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It looks 
> like the default choice is the EPC1441 which is not ISP or Flash.
[snip]
> I'm not tied down to a Flex6K persay, I think however it's the cheapest 
> 3.3V(core) FPGA Altera offers with a TQFP package. 

I had similar problem - ADI development board for high speed ADC has
Flex6K on the board and I needed to change the config - and found the
same story as you - no known solution from Altera, and even though 
Atmel config roms claim Altera compatibility not clear if Atmel rom
would work with Flex 6K.

solutions: for Flex 6K, use cheap serial eeprom (ISSI or other) and cheap
8 pin microcontroller to boot up the serial eeprom, hmm for some smaller
densities some serial eeproms could be used without that micro also,
there was a mailing about this here some time ago

use parallal flash and cheap pld to config
use some micro with enough internal flash to get the config

use some other part - this is probably best solution.
there are many FPGAs in tqfp 100 and some should be cheap as well
APA075 is 17USD qty one (non volatile FPGA, no confi mem)
small XC2S are about 9USD qty 1
hm not sure if cyclone comes in tqgp100

but really if there is no special reason to use flex 6k DO NOT USE it

antti
http://www.graphord.com/forum

Article: 60103
Subject: Re: Flex6K configuration PROM
From: Jay <se10110@yahoo.com>
Date: Fri, 5 Sep 2003 01:40:46 -0500
Links: << >>  << T >>  << A >>
Just to follow up a bit on my own thread, the "cheap" ISP alternative 
wasn't from ISSI, it was from SST. Here's the Google thread:

http://tinyurl.com/mbjl

Now, let's see if we can get that configuration PROM to work with an 
Altera FPGA w/o resorting to an 8-pin uC.

Thanks,
Jay.


Article: 60104
Subject: Re: Flex6K configuration PROM
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 05 Sep 2003 08:19:44 +0100
Links: << >>  << T >>  << A >>
Jay <se10110@yahoo.com> writes:

> I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It looks 
> like the default choice is the EPC1441 which is not ISP or Flash.
> 
> Altera makes the EPC2 which is Flash/ISP but for some reason it's not 
> compatible with FLEX6K. Anyone know why? Any way to get it to work with 
> the EPF6010A?
> 

I used one a long time ago with a 6016A, worked fine.  What makes you
think they won't work?

> I also noticed Atmel makes Altera compatible configuration PROMs that 
> are EEPROM/FLASH. Specifically, the AT17LV512A-10JC (8-PDIP). 
> 
> Can anyone give me a ball park figure on the price for either Altera or 
> Atmel configuration ROM? DigiKey doesn't have them in stock and the 
> price for the Atmel 1MBit one they do have in stock scares me (> $45).
> 

The Altera ones were about £20 last time I bought them. :-(

HTH,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 60105
Subject: ISE: use verilog-modules in an vhdl-design-flow
From: "Thomas Oehme" <toehme@freenet.de>
Date: Fri, 5 Sep 2003 09:39:39 +0200
Links: << >>  << T >>  << A >>
Hallo,
this may be an typical newbie-question(sorry).

My project is described in vhdl, but i have an working component in verilog
i want to use within.
How will i get the component in my project ?


thanks for any answer

Thomas Oehme





Article: 60106
Subject: Sending and receiving Ethernet traffic
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Fri, 05 Sep 2003 08:07:19 GMT
Links: << >>  << T >>  << A >>
I managed to transmit and receive traffic on a 10BASE-T network using some
simple Verilog code and 4 pins of an FPGA connected almost directly to the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems that we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean



Article: 60107
Subject: Re: Suitable FPGA architecture for Robots..
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Fri, 05 Sep 2003 10:11:54 +0200
Links: << >>  << T >>  << A >>
Valli wrote:

> Hi,
> 
> What FPGA architecture is more suitable for the Robots, which involves
> Pattern recognition (also partial configuration & more than 150k) and
> lot of control logic generation.
> 
> Or, Is DSP prefferable for this?

Uhhh... 
I think this is a wrong question as it appears that you are starting 
at the wrong point with your robot design.

Instead of taking an FPGA or a DSP or whatever and building your 
design around it, you should first determine how you want to 
solve your specific problems and what solutions exist so far. 

When you've got a broader view it will be much easier for you to 
decide whether you need an FPGA, a DSP, a microcontroller, or a 
mixture of all of them. 

Regards,
Mario


Article: 60108
Subject: Include design file using QuartusII
From: "Christos" <chris_saturnNOSPAM@hotmail.com>
Date: Fri, 5 Sep 2003 10:13:42 +0200
Links: << >>  << T >>  << A >>
Hi,

When using QuartusII 2.2 how can someone include a design file which is made
in another project?

I have tried by using the "Add/Remove files in project" to include a Block
diagram file I have made in a different project and I set the compiler to
focus onto that file but it gives me the error: "Node instance inst
instantiates undefined entity altsyncram0".
I understand that it have not found the files that were created by using the
megafunction. One option is to go to that folder and start copying the files
into this project's folder.  But I am sure this is not the best way.

I thing I read everything in the help files about hierarchies but I haven't
found somewhere that describes this..




Article: 60109
Subject: Writing a Xilnx testbench
From: Aart van Beuzekom <aart@westcontrol.com>
Date: Fri, 05 Sep 2003 10:54:14 +0200
Links: << >>  << T >>  << A >>
Hei,

When using the Xilins HDL bencher, the memory usage is running up to
1GB. I understood this is a known problem and it is suggested to write
your own test bench. Can anybody give me a clue on how to do this? On
the Xilinx site I was not able to find a description on this, but that
probably is caused by the fact that there is such a huge amount of data
there. To be more specific, I am looking for information on for example
adjusting/sizing simulation time, preferably with example files. All
quite basic, I think.

Thanks,

Aart

Article: 60110
Subject: Re: Moving Sum
From: "Christos" <chris_saturnNOSPAM@hotmail.com>
Date: Fri, 5 Sep 2003 10:56:16 +0200
Links: << >>  << T >>  << A >>
Hi Ray,
Forgive me that I still haven't found any time to read about the CIC filter,
but from the way you describe its operation it does not require less read
and write operations from a simple implementation of a subtract and
accumulate which I am testing at the moment. I still need the same read
pointer and the same memory.
My point is, is there an advantage with CIC that I don't see?

Christos

"Ray Andraka" <ray@andraka.com> wrote in message
news:3F578C86.2D04C220@andraka.com...
> Regardless which method is used, using a CIC limits the number of memory
> transactions per sample to just two: a read and a write.  The memory is
used as
> a delay queue, so the read pointer is N samples behind the write pointer.
The
> memory required for all those channels is pretty big, so DRAM would be the
way
> to go if you are using semiconductor memories.  Since the addressing can
easily
> be made linear, you can simplify it by using page mode or burst accesses.
This
> should make it fast enough to multiplex many channels into one memory .
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 60111
Subject: Re: Suitable FPGA architecture for Robots..
From: antti@case2000.com (Antti Lukats)
Date: 5 Sep 2003 02:10:20 -0700
Links: << >>  << T >>  << A >>
sri_valli_design@hotmail.com (Valli) wrote in message news:<d9acfecb.0309042203.2cfa75dd@posting.google.com>...
> Hi,
> 
> What FPGA architecture is more suitable for the Robots, which involves
> Pattern recognition (also partial configuration & more than 150k) and
> lot of control logic generation.
> 
> Or, Is DSP prefferable for this?

it depends what are the processing speed requirements, but I would say
its easier probably todo with DSP like TMS320LF2812 that would probably
be single chip solution. if you need prefer FPGA then you should get 
pretty large one, XC2S300 or XC3S400 as minimum.

FPGA is better for DSP when its relativly small amount of calculations
but they must be carried out with extrem speed and in streaming fashion.
if you take a DSP then it can also do streaming DSP ops, but when you then
try to use the same DSP for control functions then various task switching
takes pretty much time away, and you must be very careful that real time
tasks get their time always - in FPGA such streaming runs 'in parallel'
so you can implement some DSP function in FPGA fabric, then a RISC controller
in FPGA and control program on that RISC and slow speed DSP functions possible
also. additionally you may implement a small addiotanal DSP core in FPGA.

all the above would make a very tight fit into XC2S300, so a bit larger
device would be recommended.

I had similar decision to make - using DSP processor for DSP and Control
or using DSP functions is FPGA and FPGA softcore RISC for control, my
choice was FPGA XC2S200 or S300 and is still fit, but Xilinx Microblaze
while being pretty small still takes considerable amount of FPGA (low cost
ones) so I dont have very much left for DSP (hopefully enough).

Altera NIOS could be used in 16 bit mode on Cyclone, but here I can not
say what the resource utilization is.

antti
http://www.graphord.com/forum

Article: 60112
Subject: Re: Flex6K configuration PROM
From: "Daniel Lang" <dblx@xtyrvos.caltech.edu>
Date: Fri, 5 Sep 2003 02:47:52 -0700
Links: << >>  << T >>  << A >>

"Jay" <se10110@yahoo.com> wrote in message
news:MPG.19c1e5aecb0ec39e9896de@news.surfcity.net...
> > but really if there is no special reason to use flex 6k DO NOT USE it
>
> I am limited by two factors:
>
> 1. FPGA must *run* on 3.3V (not just be 3.3V compliant)
> 2. FPGA should be in 100-pin TQFP or smaller (smaller the better,
> without resorting to BGA / CSP)
>
> While most of the FPGAs have 3.3V I/O, they run on <=2.5V , which I
> can't accomodate. The APA075 looks good but it also needs a 2.5V VDD.
>

Why can't you generate a 2.5 volt power supply?  You could probably get
away with a PN diode in the SOD-323 package and a 1K pulldown resistor
(to establish a minimum current) to drop the 3.3 volts to 2.6 volts.
The Altera EP1K10TC100 (ACEX 1K) would be perfect.

Daniel Lang



Article: 60113
Subject: Q: Xilinx PROM file generation
From: Gerald Weile <GWE@msc-ge.com>
Date: Fri, 05 Sep 2003 12:01:28 +0200
Links: << >>  << T >>  << A >>
Hello,

is there any way to create a PROM programming file that contains
not only Xilinx BIT files but also a Lattice BIT file ?

Best regards,
Gerald
-- 
     ---------------------------------------------------
     Gerald Weile     mailto:GWE@msc-ge.com
MSC Vertriebs GmbH    Phone:+49-7249-910-186  Fax: -268
     ASIC Design        http://www.msc-ge.com


Article: 60114
Subject: Filter Output Quantization in Digital Down Converter
From: nagaraj_c_s@yahoo.com (Nagaraj)
Date: 5 Sep 2003 03:17:05 -0700
Links: << >>  << T >>  << A >>
Hi,
   I am using DDC from Xilinx CoreGen. My application requires a 6MHz
sampled signal (freq = 2MHz, BW = 2MHz) to be down converted to
baseband,resampled at 2 MHZ (ultimately the signal will be at baseband
with 2 sided bandwidth of 2MHz).
   My input bit width is 4. I have configured my DDS mixer to 8 bit
output with SFDR of 25dB. I am not using CIC filter since
downconversion ratio is small (by 3) and also cutoff fc is high (1/2)
w.r.t. lower sampling rate of 2MHz.
   I am using CFIR filter as my decimation filter in each of the I and
Q arm for restricting the signal BW to 1MHz. I am using 15 tap filter
with normalized 8 bit filter coefficients.
   When I generate the core, what I see is, the required output bit
width is 18.
   What I want is my output bit width of the DDC should be 4 bits
(with less degradation in performance of the filter). That means I
have to quantize the filter output. If I quantize uniformly(4 MSBs), I
am obtaining wrong results.
   My question is this. Is it possible to quantize such an output to 4
bits? If not, How can I calculate & justify the number of quantization
bits required at the output?
Any specific references?

Regards,
Nagaraj

Article: 60115
Subject: Re: ISE: use verilog-modules in an vhdl-design-flow
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 05 Sep 2003 20:17:09 +1000
Links: << >>  << T >>  << A >>
On Fri, 5 Sep 2003 09:39:39 +0200, "Thomas Oehme" <toehme@freenet.de>
wrote:

>Hallo,
>this may be an typical newbie-question(sorry).
>
>My project is described in vhdl, but i have an working component in verilog
>i want to use within.
>How will i get the component in my project ?
>
>
>thanks for any answer
>
>Thomas Oehme

In ISE 5.x, you can only use one of VHDL and Verilog at a time, using
the normal "flow".

Workarounds:

1.  Use a compiler such as Synplify or Leonardo.

2a. Rewrite your Verilog in VHDL.
2b. Rewrite your VHDL in Verilog.

3.  Wait until ISE 6.1 (coming RSN), which supposedly will support
VHDL and Verilog at the same time.

4.  Compile your Verilog to EDIF (or whatever) as a separate step, and
instantiate that in your VHDL as a black box.  Compile your VHDL
*without* the Verilog module as part of the list of files to compile.
The back end tools (ngdbuild) will patch the already compiled Verilog
module into the hole left in the VHDL.
Note that this will require two "projects."

Regards,
Allan.

Article: 60116
Subject: Re: Flex6K configuration PROM
From: "Deni" <dejan.durdenic@zg.hinet.hr>
Date: Fri, 5 Sep 2003 12:22:56 +0200
Links: << >>  << T >>  << A >>
I have used ATMEL parts - they're much cheaper and reprogrammable.

for price comparison only, look at www.ebv.com (German distributor, has both
Atmel
and Altera) - they have price list search on-line...

regards

Dejan



Article: 60117
Subject: 200MHz ucf constraints for Xilinx DA Decimation by 2
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Fri, 5 Sep 2003 11:28:52 +0100
Links: << >>  << T >>  << A >>

Hi folks,

I have generated a DA filter in coregen with the following specs:

Decimation by 2
40 taps symmetric
18 bit coes (signed)
12 bit input
2 clock cycles per output

The input <sampling> rate is 100MHz down to 50MHz.

However, I want to clock it at 200MHz down to 100MHz to save area - hence
the 2 clocks per output.

I am targetting an xc2v3000fg676-5 and I am pretty sure this is achievable
since the polyphases need only run at 100MHz - only the data demuxing needs
to run at 200MHz.

Constraining the whole lot via the CLK signal to 5ns (200MHz) doesn't work -
gets to about 177MHz with 16 logic levels across what is clearly a carry
chain (which needs only to run at 100MHz).

Here is what I tried in the ucf to try and tell ISE 5.2.03i what to do:

NET "CLK*" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 5 ns HIGH 50 %;
NET "ND*" TNM_NET = "ND";
TIMESPEC "TS_CLK_ND" = FROM "CLK" TO "ND" "TS_CLK" * 2;

This doesn't work though - the timing report still moans about a carry chain
failing the 5ns constraint even though it would meet the 10ns constraint it
should be tied to.  I think the logic will work at these rates but it would
be nice to know for sure via correct contraints.

So, can someone suggest some ucf details I can use to tell the tools what to
do please?  Do I need to specify some internal signal rather than ND?

Thaks for your time,

Ken


-- 
To reply by email, please remove the _MENOWANTSPAM from my email address.




Article: 60118
Subject: Re: Disable Pull up
From: fabrizio@planet1.it (Master)
Date: 5 Sep 2003 04:00:20 -0700
Links: << >>  << T >>  << A >>
"Giuseppe³" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...
> I don't sure to undestood your question but using the M0-M1-M2 pins is not
> the right way to do what you want?
> 
> Regards
> Giuseppe
> 
> "master" <ff@pla.it> ha scritto nel messaggio
> news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
> > Someone knows like turn off the  "pull up" that the family "spartan2"
> > connects for default to " tristate" placed inner lines in, from buffer "
> > Tbuf"?
> > I use "Xilinx ISE 4.1ģ" and  language "vhdl".
> > thanks
> >
> >

excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ģ, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks

Article: 60119
Subject: Schematic simulation and then FPGA programming?
From: INVALIDANTISPAM@aol.com (John K.)
Date: 5 Sep 2003 11:33:53 GMT
Links: << >>  << T >>  << A >>

Hello people,

I am strictly a schematic user, please don't turn this thread
into a "but HDLs are really better!!".
I'd like to get a new hobby, i.e. to design some (simple for
now, but then also complex) devices on a SpartanII 300E board.
The kind of devices I'd like to design range from TTL style at
the begin, till, someday, complete CPUs and simple multimedia
devices (e.g. graphic chips as seen in the '80s home computers).

I downloaded and installed Webpack, but I've been very
disappointed. It looks totally HDL oriented to me.. maybe
I'm wrong, but I couldn't see there what I'm looking for.

What I'm looking for (pardon the redundancy) is a simple
but yet powerful editor that will let me enter a schematic
(NAND gates, Flip-Flops, etc..); will also let me make new
devices from schematics (i.e. macros!); then *possibly*
simulate all of that; and then finally burn it into my
SpartanIIE chip, letting me also setup various features
of the FPGA (e.g. how to load the initial contents of
block RAM, etc..).

I have some money to invest, eventually, if the software
is not free.. but I'd like to know all the options before.

Please.. can anybody shed some light? I'm very confused
and lost..

Greets,
John


Article: 60120
Subject: Re: EDK problem!
From: "John T." <john@dat.com>
Date: Fri, 5 Sep 2003 14:41:16 +0200
Links: << >>  << T >>  << A >>

"Sathya Thammanur" <sathyatm@yahoo.com> wrote in message
news:5ca58e96.0309040934.4be7d638@posting.google.com...
> antti@case2000.com (Antti Lukats) wrote in message
news:<80a3aea5.0309030231.1a98e839@posting.google.com>...
> > > Thanx for the reply. My question is more likely: Where, in what menu
do you
> > > set an external input to be an interrupt source??? Where do you
declare the
> > > name of the interrupt function??? With a timer you can do that by
> > > right-clicking the timer and chose a name for the "timer interrupt
handler
> > > function".
> >
> > uups, I didnt think
> > "I usually don't (think), and my wife says its total disaster when I do"
> > ;)
> >
> > I am afraid to get the int line out you need to define a real dummy
> > peripheral that simple routes the pin to interrupt controller.
> > then add this peripheral component, place the ports and connect.
> > in the vhdl of the component you only have one wire-connection
> >
> > I should think sometimes sorry, you are right if there is no component
> > driving interrupt you can not assign int handler either
> >
> > antti
>
> Hi,
> To set an external interrupt to be an interrupt source, there is no
> mechanism available in the GUI currently. But, you could add the
> following line to the MSS file after the version is declared :
>
> PARAMETER VERSION = 2.0.0
> PARAMETER HW_SPEC_FILE = system.mhs
> PARAMETER INT_HANDLER = myint_handler, INT_PORT = myint_pin
>
> This will configure microblaze to call "myint_handler" whenever the
> external interrupt "myint_pin" interrupts microblaze. Also, this is
> assuming that "myint_pin" is directly connected to the interrupt port
> of microblaze without an interrupt controller.
>
> Hope this helps
> Sathya

Thank you all. That helped me some, but I am still getting CRAZY!!!
Whenever I change something and tries to redraw the PBD window it just
change my changes back to the original and nothing happens!!! Could I
somehow switch this feature off in the EDK?

John



Article: 60121
Subject: Re: Schematic simulation and then FPGA programming?
From: marlboro <>
Date: Fri, 5 Sep 2003 06:45:48 -0700
Links: << >>  << T >>  << A >>
Hi, 
I'm not HDL fan either, but I know there's an ECS tool in Webpack that allows you to do schematic (never use Webpack, I have ISE 5.1) 

To simulate the design you may need a free ModelSim starter license. There's one thing I like to add: this combination sofwares (ECS and Modelsim Starter)is very limited. I had bad time when switching from Xilinx Foundation to ISE. 

I hate to say this but that's true for me: If you are a Schematic Designer use Foundation for all the devices it supports (at this time Spartan3, Virtex2Pro, Coolrunner?... not in the list) 

May be I'm a slow learner, or I missed something here, would like to hear other opinions. 

Regards



Article: 60122
Subject: Re: 200MHz ucf constraints for Xilinx DA Decimation by 2
From: "Alvin Andries" <Alvin_Andries@nowhere.agilent.com>
Date: Fri, 5 Sep 2003 15:59:15 +0200
Links: << >>  << T >>  << A >>
Hi Ken,

"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message
news:bj9oe8$sjq$1@dennis.cc.strath.ac.uk...
>
> Hi folks,
>
> I have generated a DA filter in coregen with the following specs:
>
> Decimation by 2
> 40 taps symmetric
> 18 bit coes (signed)
> 12 bit input
> 2 clock cycles per output
>
> The input <sampling> rate is 100MHz down to 50MHz.
>
> However, I want to clock it at 200MHz down to 100MHz to save area - hence
> the 2 clocks per output.
>
> I am targetting an xc2v3000fg676-5 and I am pretty sure this is achievable
> since the polyphases need only run at 100MHz - only the data demuxing
needs
> to run at 200MHz.
>
> Constraining the whole lot via the CLK signal to 5ns (200MHz) doesn't
work -
> gets to about 177MHz with 16 logic levels across what is clearly a carry
> chain (which needs only to run at 100MHz).
>
> Here is what I tried in the ucf to try and tell ISE 5.2.03i what to do:
>
> NET "CLK*" TNM_NET = "CLK";
> TIMESPEC "TS_CLK" = PERIOD "CLK" 5 ns HIGH 50 %;
> NET "ND*" TNM_NET = "ND";
> TIMESPEC "TS_CLK_ND" = FROM "CLK" TO "ND" "TS_CLK" * 2;
>
> This doesn't work though - the timing report still moans about a carry
chain
> failing the 5ns constraint even though it would meet the 10ns constraint
it
> should be tied to.  I think the logic will work at these rates but it
would
> be nice to know for sure via correct contraints.
>
> So, can someone suggest some ucf details I can use to tell the tools what
to
> do please?  Do I need to specify some internal signal rather than ND?
>
> Thaks for your time,
>
> Ken
>
>
> --
> To reply by email, please remove the _MENOWANTSPAM from my email address.
>

What you've described is known as a multi-cycle path (data updates only
every X clock cycles allowing for the operation to span multiple clock
cycles).
I don't remember the exact ucf syntax, but I think it's a generic device to
device constraint (the example in the Xilinx documentation is very good).
Please note that you may specify this time as "X * <clock_period_name>",
which allows your design to be easily scaled for different frequencies.

Hope this helps,
Alvin.



Article: 60123
Subject: Re: use verilog-modules in an vhdl-design-flow
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Fri, 5 Sep 2003 15:02:27 +0100
Links: << >>  << T >>  << A >>
Thomas Oehme <toehme@freenet.de> wrote in message
news:bj9egd$gmu21$1@ID-205636.news.uni-berlin.de...
> Hallo,
> this may be an typical newbie-question(sorry).
> My project is described in vhdl, but i have an working component in
verilog
> i want to use within.
> How will i get the component in my project ?
> thanks for any answer
> Thomas Oehme

Thomas,

This depends on your tool set.

If you've got HDL->third party synthesis tool->FPGA P+R tool, this
should be easy enough.

An overview is....
Instantiate a VHDL component that has the same port mapping as
the VHDL component. Synthesise your VHDL and a black box is
created in the EDIF file for the component.

Synthesise the verilog to create the component that'll fit in the
black box (make sure you don't allow output buffers to be
implelmented).

Run your P+R tool, it should then plug the edif of the component
into the VHDL file.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk





Article: 60124
(removed)




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