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Messages from 131525

Article: 131525
Subject: Re: video stream transfer via UART and Bluetooth in FPGA
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 24 Apr 2008 07:52:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 24 Apr., 15:27, Narendra Sisodiya <narendra.sisod...@gmail.com>
wrote:
> I need to send video stream over a bluetoth link ,
> case 1 ) the video lise is some format (suggest a easy format) in CF
> compact flash card , I need to read this file and send it through
> UART, Kindly give me any link to do this
>
> case 2 ) I have vidoe starter kit and video is need to be captured and
> processed and then I will send it through UART
>
> which case will be easy ?
>
> another problem is , I have bluetooth Kit (ROK101007) which has
> protocol stack upto HCI layer - I need to transfer stream via
> bluetooth , so inorder to transfer data  I think i need to make HCI
> Interface layer in  VHDL and put the data in HCI data format and then
> transmit it via UART connection,,
> suggest me what to do,, I ultimater goal is to transfer video data
> (either live stream or file stored in CF card ) via Bluetooth Link,
> I have bluetooth Kit (contains layer upto HCI ) -- see it diagram at
> --
>
> http://bp3.blogger.com/_AOehQh51ooE/R722ZML8iII/AAAAAAAAAVk/o92AjwOZe...
>
> Thanks n Regards

the ROK is NOT real HCI compliant thing at all.. check the reference
designs from memec (now avnet) there are some sources for this module


Antti

Article: 131526
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 24 Apr 2008 16:18:34 +0100
Links: << >>  << T >>  << A >>
Alan Nishioka wrote:
> Symon wrote:
>> Alan Nishioka wrote:
>>> Xilinx is canceling the Virtex-E XCV1000E-FG860.
>>
>> Maybe an interposer would work? Mount the FG900 on that, mount the
>> interposer on your board? Something like this...
>> http://advanced.com/pdf/AIC_BGA_Interposer_DataSheet_revJun07.pdf
>> HTH., Syms.
>
> I fear that an interposer won't work at 75MHz.  It was hard enough to
> get to work as it is.  But it is worth some thought.  I wonder how
> much it costs?
>
> Thank you everyone for your responses.  I figured it was worth a shot
> if anyone had a radical idea.
>
> Alan Nishioka

Hi Alan,

Surprisingly, it may be it works 'better' than the ordinary solution. This 
is because the interposer's power planes can be set up differently from the 
main PCB's power planes. Whereas the main PCB's power planes are probably a 
compromise for the whole circuit, the interposer's planes can be designed to 
be optimal for the FPGA. A more expensive stackup can be used as the 
interposers are small. Bypass caps can be mounted on the interposer.

Here's a link which explains better than I can.
http://www.samtec.com/sudden_service/current_literature/powerposer.asp

Anyway, good luck with it all, I've been in similar situations myself, and 
the usual solution is a redesign. :-(

Best, Syms.



Article: 131527
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: "MH" <blah@blahblah.blah>
Date: Thu, 24 Apr 2008 16:32:59 +0100
Links: << >>  << T >>  << A >>

"Alan Nishioka" <alan@nishioka.com> wrote in message news:xQqPj.5333$iK6.4113@nlpi069.nbdc.sbc.com...
> Xilinx is canceling the Virtex-E XCV1000E-FG860.
>
> We are currently shipping a product that uses 13 of these chips on 4 different boards.
>
> Does anyone have any ideas on how to deal with this?
>
> One possibility is to rev the boards to use the XCV1000E-FG900, making minimal changes to the boards around the fpga.
>
> Complete re-design of the boards for this old system is out of the question.  Stockpiling a bunch of parts won't work because 
> we don't know what future quantities will be and the parts are very expensive.
>
> Alan Nishioka
> alan@nishioka.com


Hey Alan,

I'll do a V5 replacement design if the price is right - although it's
been a few years since I worked on that particular project....

Cheers

Mike H

(Didn't see you at NAB?) 



Article: 131528
Subject: ACTEL FPGA static timing analysis
From: Shyam Sundar <shyamsundar.sriram@gmail.com>
Date: Thu, 24 Apr 2008 08:37:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am using actel 1280 FPGA. How to use the Timer to detect set up
violations arising due to clock skew between two registers of a
counter?

Article: 131529
Subject: Re: Verilog state machines, latches, syntax and a bet!
From: Muzaffer Kal <kal@dspia.com>
Date: Thu, 24 Apr 2008 15:55:20 GMT
Links: << >>  << T >>  << A >>
On Wed, 23 Apr 2008 08:54:24 -0700 (PDT), Dave <dhschetz@gmail.com>
wrote:

> The default assignment
>does not imply memory, it's just a shorthand notation to keep the code
>more readable.

Isn't the whole idea of a combinatorial process to avoid memory? In
the two process model, the non-clocked process is supposed to be fully
combinational. You can imagine the default assignment as the branch of
a mux coming from the output of the memory directly and the other
branch which is actually calculated next state. If there is no
calculated next state the current state gets loaded again.

Article: 131530
Subject: Re: Verilog state machines, latches, syntax and a bet!
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 24 Apr 2008 10:01:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 11:55=A0am, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 23 Apr 2008 08:54:24 -0700 (PDT), Dave <dhsch...@gmail.com>
> wrote:
>
> > The default assignment
> >does not imply memory, it's just a shorthand notation to keep the code
> >more readable.
>
> Isn't the whole idea of a combinatorial process to avoid memory?

Yes...the memory is 'supposed to' be implemented in a separate clocked
process (for the two process design approach).

> In
> the two process model, the non-clocked process is supposed to be fully
> combinational.

But there is nothing preventing the designer from inadvertantly
creating a latch in this process.  The two process approach presents
no advantages and has several disadvantages as compared to the one
process approach.

> You can imagine the default assignment as the branch of
> a mux coming from the output of the memory directly and the other
> branch which is actually calculated next state. If there is no
> calculated next state the current state gets loaded again.

If there is no 'calculated next state' in the combinatorial process
then you have a design error because you've just created a transparent
latch that will come up and bite you at the most inopportune time.
This latch is the 'unwanted memory' that is being created which should
not exist when using the two process form.  All this unpleasantness is
completely avoided by simply using a one process design approach.

KJ

Article: 131531
Subject: Re: video stream transfer via UART and Bluetooth in FPGA
From: Narendra Sisodiya <narendra.sisodiya@gmail.com>
Date: Thu, 24 Apr 2008 10:34:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 7:52 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 24 Apr., 15:27, Narendra Sisodiya <narendra.sisod...@gmail.com>
> wrote:
>
>
>
> > I need to send video stream over a bluetoth link ,
> > case 1 ) the video lise is some format (suggest a easy format) in CF
> > compact flash card , I need to read this file and send it through
> > UART, Kindly give me any link to do this
>
> > case 2 ) I have vidoe starter kit and video is need to be captured and
> > processed and then I will send it through UART
>
> > which case will be easy ?
>
> > another problem is , I have bluetooth Kit (ROK101007) which has
> > protocol stack upto HCI layer - I need to transfer stream via
> > bluetooth , so inorder to transfer data  I think i need to make HCI
> > Interface layer in  VHDL and put the data in HCI data format and then
> > transmit it via UART connection,,
> > suggest me what to do,, I ultimater goal is to transfer video data
> > (either live stream or file stored in CF card ) via Bluetooth Link,
> > I have bluetooth Kit (contains layer upto HCI ) -- see it diagram at
> > --
>
> >http://bp3.blogger.com/_AOehQh51ooE/R722ZML8iII/AAAAAAAAAVk/o92AjwOZe...
>
> > Thanks n Regards
>
> the ROK is NOT real HCI compliant thing at all.. check the reference
> designs from memec (now avnet) there are some sources for this module
>
> Antti

May you suggest any good bluetooth kit which will be suited for my
work and any existing work for bluetooth data transfer from FPGA,
basically , In PC (Linux ) we have blueZ stack which will communicate
with kits, I cannot have embedded linux on my design,, i have to make
a VHDL source and EDK project which can communicate to any bluetooth
kit , So I think I have to design the the stack in Hardware .. am i
coorect....?? Pelase help me-- what to do,,,

Article: 131532
Subject: Re: video stream transfer via UART and Bluetooth in FPGA
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 24 Apr 2008 11:07:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 24 Apr., 19:34, Narendra Sisodiya <narendra.sisod...@gmail.com>
wrote:
> On Apr 24, 7:52 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 24 Apr., 15:27, Narendra Sisodiya <narendra.sisod...@gmail.com>
> > wrote:
>
> > > I need to send video stream over a bluetoth link ,
> > > case 1 ) the video lise is some format (suggest a easy format) in CF
> > > compact flash card , I need to read this file and send it through
> > > UART, Kindly give me any link to do this
>
> > > case 2 ) I have vidoe starter kit and video is need to be captured and
> > > processed and then I will send it through UART
>
> > > which case will be easy ?
>
> > > another problem is , I have bluetooth Kit (ROK101007) which has
> > > protocol stack upto HCI layer - I need to transfer stream via
> > > bluetooth , so inorder to transfer data  I think i need to make HCI
> > > Interface layer in  VHDL and put the data in HCI data format and then
> > > transmit it via UART connection,,
> > > suggest me what to do,, I ultimater goal is to transfer video data
> > > (either live stream or file stored in CF card ) via Bluetooth Link,
> > > I have bluetooth Kit (contains layer upto HCI ) -- see it diagram at
> > > --
>
> > >http://bp3.blogger.com/_AOehQh51ooE/R722ZML8iII/AAAAAAAAAVk/o92AjwOZe...
>
> > > Thanks n Regards
>
> > the ROK is NOT real HCI compliant thing at all.. check the reference
> > designs from memec (now avnet) there are some sources for this module
>
> > Antti
>
> May you suggest any good bluetooth kit which will be suited for my
> work and any existing work for bluetooth data transfer from FPGA,
> basically , In PC (Linux ) we have blueZ stack which will communicate
> with kits, I cannot have embedded linux on my design,, i have to make
> a VHDL source and EDK project which can communicate to any bluetooth
> kit , So I think I have to design the the stack in Hardware .. am i
> coorect....?? Pelase help me-- what to do,,,

no, you are not coorect.

Antti

Article: 131533
Subject: Re: will there be any problem with diffrent version of sysgen & EDK
From: ghelbig@lycos.com
Date: Thu, 24 Apr 2008 11:17:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 6:14 am, Narendra Sisodiya <narendra.sisod...@gmail.com>
wrote:
> hi, I have ISE 9.1 + EDK 9.1 (all updates)
> Now i have downloaded the xilinx sysgen 10.1 (60 day trial) as 9.1 is
> not available
> also I have matlab R2006b
> will threre be any problem with versions , in near future --
> othrewise i will search 9.1 ,
>
> Thanks n Regards

In my experience, all the Xilinx components absolutely had to be of
exactly the same revision.  Because of this, I would not even try
using Sysgen-10.1 with ISE/EDK-9.1

Either update ISE/EDK, or ask "pretty-please" to Austin or Peter and
see if they will find you a sysgen-91.

G.

Article: 131534
Subject: Re: How to instantiate macro in verilog
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Thu, 24 Apr 2008 12:17:52 -0600
Links: << >>  << T >>  << A >>
Moazzam wrote:
> On Apr 21, 10:12 pm, Kevin Neilson
> <kevin_neil...@removethiscomcast.net> wrote:
>> Haile Yu (Harry) wrote:
>>> Dear all,
>>> I've designed a macro, and put "ring.nmc" file in my project dir.
>>> In my verilog module file, I wrote
>>> ...
>>> ring r1(.en(en),.ro(ro));
>>> ...
>>> to instantiate ring macro, but failed.
>>> Any one could give some hint?
>>> Thank you!
>> If this is a ring oscillator, you may be having problems with the tools
>> stripping away the logic.  -Kevin
> 
> Hi,
> Kevin is right, also I use macros: declared as black box and write
> their "portlist followed by endmodule " in a "macro_name.v" file in
> the working directory.
> 
> Hope this helps,
> /MH
I'm not sure what you mean, and your syntax is unusual:  I think a 
"macro" is a software term.  Anyway, I'm not sure what the issue is 
here, but if you are trying to make a ring oscillator, one problem is 
that the synthesizer and mapper try to strip it away because it's a 
combinatorial loop and makes no sense from a logical standpoint.  So you 
might have to put some sort of "keep" directives to prevent this.  -Kevin

Article: 131535
Subject: Re: Turning off the DLL to run DDR2 at very low frequency
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Thu, 24 Apr 2008 12:23:52 -0600
Links: << >>  << T >>  << A >>
adubinsky457@gmail.com wrote:
> On Apr 21, 4:36 pm, Kevin Neilson
> <kevin_neil...@removethiscomcast.net> wrote:
>> adubinsky...@gmail.com wrote:
>>> Hi,
>>> There's been a few discussions about this the last couple years, but
>>> it seems nothing ended with firm conclusions. What I would like to do
>>> is to run DDR2 at 25MHz (DDR50). I understand that to do this I have
>>> to turn off the DLL (which can't work at below 125MHz) and that this
>>> should work but is not supported. My question is, what happens then?
>>> Ie: How do the DQS signals behave during read? Do they turn off,
>>> become random, are synchronized with the clock? Is it safe to just
>>> read the data a quarter cycle after the clock edge, or is it more
>>> complicated than that? I haven't designed an sdram core before, but
>>> I'm going to have to do this for this project and have many other,
>>> more general questions. If someone knows some good reading material,
>>> please let me know.
>>> Aleksandr Dubinsky
>> You won't find any firm conclusions.  As you've probably found out, the
>> datasheets make no statements one way or another about usage when the
>> DLL is disabled.  I did some experiments with this for a project that
>> was later aborted.  As I recall, I ran DDR (type 1, I think) at 75MHz or
>> so, disabling the DLL.  As I recall it worked fine.  The main difference
>> just seems to be that you don't have a guaranteed difference between the
>> clock and DQS.  If your design doesn't depend on this, then it should
>> work.  I think most designs rely on a narrow window where they expect
>> DQS to show up, because the clock speed and copper lengths are fixed.
>> But if you have a design that is flexible enough to allow for any sort
>> of delay, it should work OK.  This type of flexibility is difficult,
>> though.  There is ambiguity in the DQS edge, because you might not know
>> which edge it is.  My design required writing data to the DRAM and then
>> reading it back to determine which DQS edge I was seeing.  As you know,
>> though, disabling the DLL carries no guarantees and performance may
>> differ between brands.
>>
>> You could always have a design which runs the IOBs at high speeds
>> (125MHz) but then connects to a memory controller running at a lower
>> rate.  I.e., the effective speed would be about the same as a slower
>> single-clock design because you would have gaps between the bursts.  But
>> you'd need asynchronous FIFOs.  -Kevin
> 
> 
> "The main difference just seems to be that you don't have a guaranteed
> difference between the clock and DQS."
> 
> It sounds like you're saying that I still have to track and
> synchronize to the DQS and that it acts a bit unpredictably, at least
> at 75MHz.
> 
> "My design required writing data to the DRAM and then reading it back
> to determine which DQS edge I was seeing."
> 
> You mean your controller was constantly re-calibrating?
> 
> "You could always have a design which runs the IOBs at high speeds
> (125MHz) but then connects to a memory controller running at a lower
> rate."
> 
> My reasons for running at 25MHz is signal quality on the bus.
> 
> - Alex
Take care that you have all the on-die termination settings (such as the 
RTT register) correct--this might help the bus quality.

What I was trying to say is that with the DLL on, the range of the DQS 
edge is fairly narrow.  I think most designs are meant to work with a 
single clock rate and the assumption that the copper delays are within a 
narrow range (that vary slightly only because of temperature/voltage) 
and then the controller can be simplified because it knows basically 
where the edge will be and there is no cycle ambiguity.  Without this 
DLL this window becomes large.  I'm not saying that it necessarily 
drifts rapidly with time--just that you can't say before reset where the 
edge will be.  My controller didn't recalibrate continuously--just at 
reset, which seemed to work fine.  The good thing is that with low 
speeds the controller becomes easier in that you don't have to worry 
about finding the exact middle of the DQS pulse--the pulse is fat enough 
that you can simply find the edge and then delay a certain fixed amount 
of time before latching.  -Kevin

Article: 131536
Subject: Re: Verilog state machines, latches, syntax and a bet!
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Thu, 24 Apr 2008 12:44:25 -0600
Links: << >>  << T >>  << A >>
ee_ether wrote:
> Hi,
> 
> A colleague and I are having a friendly debate on coding state
> machines in Verilog, targeting synthesis for FPGAs.  Comments are very
> appreciated.  I am NOT trying to start a holy war here regarding
> syntax style (one process vs. two process, etc).
> 
> Crux of the matter:  Do you need to define values for outputs of your
> state machine in EVERY state, or do you only need to define values for
> outputs in states where you want the output to update/change?
> 

You shouldn't need to specify output values for states in which the 
output doesn't change.  However, this sometimes makes it hard to debug 
something like a flag because you have to make sure that you deassert 
the signal in all states that can follow the state in which you asserted it.

For things like flags that are only to be asserted on a few states, I 
like to do this:

always@(posedge clk)
begin
   flag <= 0;  // set the default value
   case (state)
     state0: state <= state1;
     state1: state <= state2;
     state2: flag  <= 1;
     state3: state <= state0;
   endcase
end

You can see that for state2, the value of flag is set twice:  once to 0 
and then later to 1.  In a clocked process which uses nonblocking 
signals, the assignment made last is the one that is used.  (Sometimes 
order *is* important with nonblocking assignments.)  This ensures that 
flag is assigned to 0 in every other state.  If the synthesizer has 
state machine extraction, it might just implement the logic to assert 
flag's clock enable in the two states (state2 and state3) where it 
actually changes.  An explicit synthesis would update flag on every 
cycle but only assign it to 1 on state2.  If the machine is one-hot, it 
wouldn't matter too much either way.
-Kevin

Article: 131537
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: dalai lamah <antonio12358@hotmail.com>
Date: Thu, 24 Apr 2008 18:46:37 GMT
Links: << >>  << T >>  << A >>
Un bel giorno austin digit:

> With the small volume, re-design of the pcb is just not going to be
> worth the money spent (you will never recover it)

It doesn't look so expensive. Of course it depends on PCB complexity, but
let's say 1000 $ for remastering and 1000 $ for the new PCB masks. In a
product where a single piece mounts 13 of those parts (AVnet sells 100
pieces of them at 963$ each!) it's quite easy to write off a 2000 $
investment.

-- 
emboliaschizoide.splinder.com

Article: 131538
Subject: Re: DCM configuration in Virtex-4 FPGA
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 24 Apr 2008 15:13:56 -0400
Links: << >>  << T >>  << A >>
<mspiegels@gmail.com> wrote in message 
news:158c50e1-7947-4c77-80a8-b887eab3e267@z72g2000hsb.googlegroups.com...
> Heey Austin and Mikhail,
>
> Thanks for the replies, it's still a bit difficult for me to make sens
> of it all because i have to learn more about these "buffers" (IBUFG
> and BUFG) but some more research on the internet will probably do the
> trick. It's clear now that these DCM's are internal and no physical
> pins are involved. A little fight with ISE to get the DCM IP-block
> work will be needed :)
> Offcourse if anyone has made a little program with a DCM involved, any
> code of how it's implemented is welcome.
> Once again: thanks!

It is all in the documentation for the tools and for the chips. Internet 
research is not required. DCM IP block is very easy to get to work. However, 
perhaps before going there you should acquire some more basic skills of 
working with the tools. Learn how to do a LED flasher or something like 
that... Then add a DCM in it...


/Mikhail




Article: 131539
Subject: Re: the order in which some switches are turned on
From: jkljljklk <maricic@gmail.com>
Date: Thu, 24 Apr 2008 14:02:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 23, 1:21 am, laura <laura.brandu...@gmail.com> wrote:
> Hi all,
>
> I have an array of N switches . Initially all are OFF.
>
> Somebody turns them ON in some order. It is possible that more
> switches are turned ON in the same moment.
>
> I need a device which shows me the order in which the switches were
> turned ON. For instance the device should give me: 4,3,1,5,2 (this is
> the order in which the switches were turned ON).
>
> The way in which the output is shown in not important. It must be
> simple to read (by a human, computer, etc).
>
> It is important that the device is able to handle the turned ON (in
> the same moment) of the multiple switches.
>
> thanks,
> Laura

You can create a process that will be triggered by a clock. The faster
this clock is, more accurate your timing will be - ie not more then
one switch will be turned on for one clock cycle. At every clock event
all the switches are read, and if one of them is turned on, its value
is written by this process to some array that will give you the order
of the switches. Hope this help.
Dan

Article: 131540
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Thu, 24 Apr 2008 21:38:16 +0000 (UTC)
Links: << >>  << T >>  << A >>
dalai lamah <antonio12358@hotmail.com> wrote:
> Un bel giorno austin digit:

> > With the small volume, re-design of the pcb is just not going to be
> > worth the money spent (you will never recover it)

> It doesn't look so expensive. Of course it depends on PCB complexity, but
> let's say 1000 $ for remastering and 1000 $ for the new PCB masks. In a
> product where a single piece mounts 13 of those parts (AVnet sells 100
> pieces of them at 963$ each!) it's quite easy to write off a 2000 $
> investment.

But then the manifacturer needs to cope with two bitfiles..
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 131541
Subject: Re: video stream transfer via UART and Bluetooth in FPGA
From: Narendra Sisodiya <narendra.sisodiya@gmail.com>
Date: Thu, 24 Apr 2008 15:25:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 11:07 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 24 Apr., 19:34, Narendra Sisodiya <narendra.sisod...@gmail.com>
> wrote:
>
>
>
> > On Apr 24, 7:52 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 24 Apr., 15:27, Narendra Sisodiya <narendra.sisod...@gmail.com>
> > > wrote:
>
> > > > I need to send video stream over a bluetoth link ,
> > > > case 1 ) the video lise is some format (suggest a easy format) in CF
> > > > compact flash card , I need to read this file and send it through
> > > > UART, Kindly give me any link to do this
>
> > > > case 2 ) I have vidoe starter kit and video is need to be captured and
> > > > processed and then I will send it through UART
>
> > > > which case will be easy ?
>
> > > > another problem is , I have bluetooth Kit (ROK101007) which has
> > > > protocol stack upto HCI layer - I need to transfer stream via
> > > > bluetooth , so inorder to transfer data  I think i need to make HCI
> > > > Interface layer in  VHDL and put the data in HCI data format and then
> > > > transmit it via UART connection,,
> > > > suggest me what to do,, I ultimater goal is to transfer video data
> > > > (either live stream or file stored in CF card ) via Bluetooth Link,
> > > > I have bluetooth Kit (contains layer upto HCI ) -- see it diagram at
> > > > --
>
> > > >http://bp3.blogger.com/_AOehQh51ooE/R722ZML8iII/AAAAAAAAAVk/o92AjwOZe...
>
> > > > Thanks n Regards
>
> > > the ROK is NOT real HCI compliant thing at all.. check the reference
> > > designs from memec (now avnet) there are some sources for this module
>
> > > Antti
>
> > May you suggest any good bluetooth kit which will be suited for my
> > work and any existing work for bluetooth data transfer from FPGA,
> > basically , In PC (Linux ) we have blueZ stack which will communicate
> > with kits, I cannot have embedded linux on my design,, i have to make
> > a VHDL source and EDK project which can communicate to any bluetooth
> > kit , So I think I have to design the the stack in Hardware .. am i
> > coorect....?? Pelase help me-- what to do,,,
>
> no, you are not coorect.
>
> Antti

Ok, I am wrong ,  then please tell me how to do this task, ?

Article: 131542
Subject: Re: will there be any problem with diffrent version of sysgen & EDK
From: Narendra Sisodiya <narendra.sisodiya@gmail.com>
Date: Thu, 24 Apr 2008 16:01:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 11:17 pm, ghel...@lycos.com wrote:
> On Apr 24, 6:14 am, Narendra Sisodiya <narendra.sisod...@gmail.com>
> wrote:
>
> > hi, I have ISE 9.1 + EDK 9.1 (all updates)
> > Now i have downloaded the xilinx sysgen 10.1 (60 day trial) as 9.1 is
> > not available
> > also I have matlab R2006b
> > will threre be any problem with versions , in near future --
> > othrewise i will search 9.1 ,
>
> > Thanks n Regards
>
> In my experience, all the Xilinx components absolutely had to be of
> exactly the same revision.  Because of this, I would not even try
> using Sysgen-10.1 with ISE/EDK-9.1
>
> Either update ISE/EDK, or ask "pretty-please" to Austin or Peter and
> see if they will find you a sysgen-91.
>
> G.

Actually,, I have 9.2 sysgen exe file and My friend reported that he
has done his project with it and worked fine , He got some problem
with 9.1 -- Actually I do not have registration id for 9.2 version. on
xilinx website they give registration of 10.1 ,
So from where I can get registration id (60 day trial) for 9.2 sysgen


Article: 131543
Subject: ATF750 for Proteus
From: "Julio Espada" <newsnet@jmo.biz>
Date: Fri, 25 Apr 2008 01:28:36 +0100
Links: << >>  << T >>  << A >>
Hi!

I'm looking for the Atmel ATF750C library for Proteus but I'm unable to find 
it on both Atmel & Labcenter sites. Does anyone know where can I find this ? 
Or perhaps, any other application that can simulate the ATF750C ?

Thanks in advance for any help.


Article: 131544
Subject: Re: FPGA comeback
From: "jtw" <wrightjt @hotmail.invalid>
Date: Fri, 25 Apr 2008 04:09:57 GMT
Links: << >>  << T >>  << A >>
Way back in the day... there was Yahoo and AltaVista, as well as a few 
others, before Google came on the scene.  Not to mention newsgroups...

Symon's [condescending] advice was to do some research on your own, using 
the readily available information on the internet, before asking the same 
question that many have asked before.... and many have answered.

After you review the history, and can ask relevant questions, this newsgroup 
can be a fountain of interesting and, sometimes, useful information.

JTW

"RealInfo" <therightinfo@yahoo.com> wrote in message 
news:funar7$pit$1@news4.netvision.net.il...
Dear Symon the same advice to you if you can not understand simple english 
...

"My question is which board and which FPGA vendor is reccomanded according 
to
    your experience "

Does GOOGLE have any experince in FPGA   so it/he/she whatever  can give 
some advise ?

Thanks any way ...





"Symon" <symon_brewer@hotmail.com>  :fun8t6$fv7$1@aioe.org...
> RealInfo wrote:
>> Hi
>>
>> I want to get into FPGA design after long time I was out of it.
>>
>> I did some work with ALTERRA long ago .
>>
>> I mainly did VHDL models for asic .
>>
>> I want to buy some FPGA board and to do some projects on it with VHDL
>> to get into that field again .
>>
>> My question is which board and which FPGA vendor is reccomanded
>> according to your
>> experience.
>>
>> Thanks in advance
>> ec.
>
> Dear ec,
> If you are unable to use Google to help yourself, perhaps you should stay
> out of FPGA design. Now, be a good chap, and do some research before you
> post.
> Condescendingly, Syms.
> http://catb.org/~esr/faqs/smart-questions.html#before
> to find
> http://www.fpga-faq.com/FPGA_Boards.shtml
>
> 


Article: 131545
Subject: Re: Survey: FPGA PCB layout
From: JosephKK <quiettechblue@yahoo.com>
Date: Thu, 24 Apr 2008 21:36:22 -0700
Links: << >>  << T >>  << A >>
On Thu, 17 Apr 2008 17:13:27 -0400, "Steve" <sjburke1@comcast.net>
wrote:

>
>"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message 
>news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com...
>> qrk wrote:
>>> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com>
>>> wrote:
>>>
>>>> Does anybody out there have a good methodology for determining your
>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean?
>>>> The brute force method is fairly maddening. I'd be curious to hear if
>>>> anybody has any 'tricks of the trade' here.
>>>>
>>>> Also, just out of curiosity, how many of you do your own PCB layout,
>>>> versus farming it out? It would certainly save us a lot of money to
>>>> buy the tools and do it ourselves, but it seems like laying out a
>>>> board out well requires quite a bit of experience, especially a 6-8
>>>> layer board with high pin count FPGA's.
>>>>
>>>> We're just setting up a hardware shop here, and although I've been
>>>> doing FPGA and board schematics design for a while, it's always been
>>>> at a larger company with resources to farm the layout out, and we
>>>> never did anything high-speed to really worry about the board layout
>>>> too much. Thanks in advance for your opinions.
>>>>
>>>> Dave
>>>
>>> Sure wish there was a slick way of doing FPGA pinouts. I usually use
>>> graph paper and figure out the FPGA pinout to other parts to minimize
>>> routing snarls.
>>>
>>> I do pcb layouts on my own and other folks designs. Our boards have
>>> high-speed routing, switching power supplies, and high-gain analog
>>> stuff; sometimes all on the same board. Unless the service bureau has
>>> someone who understands how to lay out such circuitry and place
>>> sensitive analog stuff near digital junk, it is more trouble to farm
>>> out than do it yourself if you want the board to work on the first
>>> cut.
>>>
>>
>> Or find a good layouter and develop a long-term business relationship. My 
>> layouter knows just from looking at a schematic which areas are critical. 
>> He's a lot older than I am and that is probably one of the reasons why his 
>> stuff works without much assistance from me. Nothing can replace a few 
>> decades of experience.
>>
>>
>>> Doing your own layout will take a lot of learning to master the PCB
>>> layout program and what your board vendor can handle. It will take 5
>>> to 10 complicated boards to become mildly proficient at layout. I
>>> don't know about saving cost. Your time may be better spent doing
>>> other activities rather than learning about layout and doing the
>>> layouts. ...
>>
>>
>> Yep, that's why I usually do not do my own layouts. Occassionally I route 
>> a small portion of a circuit and send that to my layouter. No DRC or 
>> anything, just to show him how I'd like it done.
>>
>>
>>>     ... The upside to doing your own layout - you control the whole
>>> design from start to finish. If you have a challenging layout, you'll
>>> have a much higher probability of having a working board on the first
>>> try which has hidden savings (getting to market earlier <- less
>>> troubleshooting + less respins).
>>>
>>> ---
>>> Mark
>>
>>
>> -- 
>> Regards, Joerg
>>
>> http://www.analogconsultants.com/
>>
>> "gmail" domain blocked because of excessive spam.
>> Use another domain or send PM.
>
>I agree with Joerg. Good high speed or mixed signal PCB layout is a career 
>choice, and we electrical engineers already chose our career. A good layout 
>requires someone who understands not just the software package, but the 
>details of how the manufacturing operation is going to proceed, what the 
>limits of the processes are, what the assembly operations require of the 
>board, and is anal about things like footprint libraries and solder mask 
>clearances and a thousand other details that I'm only partially aware of. 
>The more complex your design, the more critical these things become.
>
>I have two good local outfits for farming out boards. For complex stuff, 
>they know I'll come to their place and sit next to the designer for a good 
>bit of the initial placement. While we are doing placement, we are also 
>discussing critical nets, routing paths, layer usage, etc.  That gives us 
>direct face to face communication and avoids spending lots of time trying to 
>write/draw everything in gory detail (which gets ignored or misunderstood a 
>lot of the time). That investment pays big dividends in schedule and board 
>performance.
>
>Don't be fooled by the relatively low cost of the software. That's not where 
>the big costs are.
>
>I once laid off my entire PCB layout department and sent all the work 
>outside, because although my employees all knew how to use the software, 
>none of them could tell me what their completion date would be, or how many 
>hours it would take, and they certainly weren't interested in meeting 
>schedules. The outside sources would commit to a cost and a delivery date. 
>And we already knew they could meet our performance objectives. Fixed price 
>contracts are great motivators. Missing an engineering test window, or 
>slipping a production schedule because of a layout delay can be enormously 
>expensive.
>
>Of course, if I had let my engineers do their own layouts, the motivation 
>would have been present, but the technical proficiency would not. How 
>proficient can anyone become if they only do layout a few times a year? 
>Also, on many projects engineers use the layout period for other important 
>things like documentation, test procedures, writing test code, etc. Doing 
>your own layout serializes these tasks and will stretch your schedule.
>
>So my advice is to keep doing what you have been doing. Its far more likely 
>that its the cheapest approach, even though you occasionally have to write a 
>big check.
>
>Steve
>

Pretty much honest responses.  Almost all of good value. 

 Mark hinted and Joerg mentioned one of the foremost subjects,
floorplanning.  This will impact everything you do.  From the original
schematic drawing to the FPGA  VHDL/Verilog coding and optimizing to
PWB layout , documentation, and testing.  Each of these activities
requires floorplanning to get good results.  To achieve the best PWD
layout results make several different versions for your first few
boards and route them all to completion.  It will make huge
improvements in your understanding.
 

Article: 131546
Subject: Re: will there be any problem with diffrent version of sysgen & EDK
From: Narendra Sisodiya <narendra.sisodiya@gmail.com>
Date: Thu, 24 Apr 2008 21:54:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 25, 4:01 am, Narendra Sisodiya <narendra.sisod...@gmail.com>
wrote:
> On Apr 24, 11:17 pm, ghel...@lycos.com wrote:
>
>
>
> > On Apr 24, 6:14 am, Narendra Sisodiya <narendra.sisod...@gmail.com>
> > wrote:
>
> > > hi, I have ISE 9.1 + EDK 9.1 (all updates)
> > > Now i have downloaded the xilinx sysgen 10.1 (60 day trial) as 9.1 is
> > > not available
> > > also I have matlab R2006b
> > > will threre be any problem with versions , in near future --
> > > othrewise i will search 9.1 ,
>
> > > Thanks n Regards
>
> > In my experience, all the Xilinx components absolutely had to be of
> > exactly the same revision.  Because of this, I would not even try
> > using Sysgen-10.1 with ISE/EDK-9.1
>
> > Either update ISE/EDK, or ask "pretty-please" to Austin or Peter and
> > see if they will find you a sysgen-91.
>
> > G.
>
> Actually,, I have 9.2 sysgen exe file and My friend reported that he
> has done his project with it and worked fine , He got some problem
> with 9.1 -- Actually I do not have registration id for 9.2 version. on
> xilinx website they give registration of 10.1 ,
> So from where I can get registration id (60 day trial) for 9.2 sysgen

problem solved , Thanks, my friend has given me sysgen 9.1 + reg-id
also
Thanks

Article: 131547
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: Alan Nishioka <alan@nishioka.com>
Date: Thu, 24 Apr 2008 22:12:03 -0700
Links: << >>  << T >>  << A >>
MH wrote:
> "Alan Nishioka" <alan@nishioka.com> wrote in message news:xQqPj.5333$iK6.4113@nlpi069.nbdc.sbc.com...
>> Xilinx is canceling the Virtex-E XCV1000E-FG860.
>>
>> We are currently shipping a product that uses 13 of these chips on 4 different boards.
>>
>> Does anyone have any ideas on how to deal with this?
>>
>> One possibility is to rev the boards to use the XCV1000E-FG900, making minimal changes to the boards around the fpga.
>>
>> Complete re-design of the boards for this old system is out of the question.  Stockpiling a bunch of parts won't work because 
>> we don't know what future quantities will be and the parts are very expensive.
>>
>> Alan Nishioka
>> alan@nishioka.com
> 
> 
> Hey Alan,
> 
> I'll do a V5 replacement design if the price is right - although it's
> been a few years since I worked on that particular project....
> 
> Cheers
> 
> Mike H
> 
> (Didn't see you at NAB?) 

I didn't know you read usenet :-)

I'm afraid PB doesn't want to pay either of us.
I'm just sad that it's the end of the line for this product, since it is 
the project I am most proud of in my career.

I didn't go to NAB this year.  I've left the business (or to be more 
accurate, the business left me).  I went to ESC instead.

Alan Nishioka

Article: 131548
Subject: Re: How to instantiate macro in verilog
From: Moazzam <moazzamhussain@gmail.com>
Date: Thu, 24 Apr 2008 22:15:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 11:17=A0pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
> Moazzam wrote:
> > On Apr 21, 10:12 pm, Kevin Neilson
> > <kevin_neil...@removethiscomcast.net> wrote:
> >> Haile Yu (Harry) wrote:
> >>> Dear all,
> >>> I've designed a macro, and put "ring.nmc" file in my project dir.
> >>> In my verilog module file, I wrote
> >>> ...
> >>> ring r1(.en(en),.ro(ro));
> >>> ...
> >>> to instantiate ring macro, but failed.
> >>> Any one could give some hint?
> >>> Thank you!
> >> If this is a ring oscillator, you may be having problems with the tools=

> >> stripping away the logic. =A0-Kevin
>
> > Hi,
> > Kevin is right, also I use macros: declared as black box and write
> > their "portlist followed by endmodule " in a "macro_name.v" file in
> > the working directory.
>
> > Hope this helps,
> > /MH
>
> I'm not sure what you mean, and your syntax is unusual: =A0I think a
> "macro" is a software term. =A0Anyway, I'm not sure what the issue is
> here, but if you are trying to make a ring oscillator, one problem is
> that the synthesizer and mapper try to strip it away because it's a
> combinatorial loop and makes no sense from a logical standpoint. =A0So you=

> might have to put some sort of "keep" directives to prevent this. =A0-Kevi=
n- Hide quoted text -
>
> - Show quoted text -


Hi,
I will try to explain my previous post:

while making an instance of a macro file, as described by OP,I use
following syntax:

//-----------------------------------------------------------------//
ring r1(.en(en),.ro(ro));   //synthesis black_box

Make a new file in editor as:

module ring (
                    en,
                    ro
  );

input enable;
output ro;

endmodule

//------------------------------------------------------------//

In my knowledge, making a file as above avoids synthesis error of
unavailability of file.
And declaration of instance as a blackbox would make the tool search
for a netlist of
the macro.

I may not be following the exact steps but it actually works for me
while playing with
Bus Macros of Dynamic Partial reconfiguration or working with EDN/NGC
files with no
verilog RTL.

/MH




Article: 131549
Subject: delta sigma adc.....
From: krunal <krunal.coep@gmail.com>
Date: Thu, 24 Apr 2008 22:40:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi....I want to implement Sigma Delta ADC in Spartan 3E starter
kit....i have implemented it as xilinx's xapp-155.....in ise it works
well for 8 bit....but give problem for 16 bit.....When i open it in
sysgen it now work.......actually in program the dac.v is
included......i dont know how to open that include file in
sysgen....please help........if any one have verilog or vhdl code for
that please send me........and i want to interface the exeternal ADC
also.....so please help me......



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