Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 121125

Article: 121125
Subject: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
From: "commone" <dechenxu@yahoo.com.cn>
Date: Tue, 26 Jun 2007 02:44:33 -0500
Links: << >>  << T >>  << A >>
Mark
     Did you mean that if I assign the "PLL1_outp" to c1 it will function
as general I/O pin; otherwise,if I assign the PLL1_outp to c2 it will
function as PLL<#>_out? I do not know if there is an option available in
Quartus II to determine this pin to function as a general I/O pin or
PLL<#>_OUT. But does this problem influence the compensation for clock
skew?
     Another question: 
   IN "Pin Information for the Cyclone« II EP2C15A, EP2C20..." it is said
that "These pins can only use the differential I/O standard if it is being
fed by a PLL output" for PLL[1..4]_OUTP. (on page 19)
   But in Cyclone II device handbook it is said that "One of these outputs
(C2) can also drive a dedicated PLL<#>_OUT pin (single ended or
differential)." (Table 2-4 on page 2-26)
   So my question is if the PLL1_OUTP can be funtion as a single ended
external clock out fed by internal pll ouput C2 or it must be used along
with PLL1_OUTN to function as a differential clock output fed by c2.
Thanks,
Leon

Article: 121126
Subject: Re: Amontec chameleon
From: Antti <Antti.Lukats@googlemail.com>
Date: Tue, 26 Jun 2007 07:48:23 -0000
Links: << >>  << T >>  << A >>
On Jun 26, 8:35 am, "Ravishankar S" <ravishanka...@in.bosch.com>
wrote:
> Hello Amontec, Larry,
>
> Spefically for you, since I did not get any reposone from the Amontec site!
>
> Could you explain the features of the chameleon. How does it work ? Can it
> be configured to work with any debug connection. Specifically I want to
> debug a MPC8241 (COP connector) and possibly a TriCore controller. How will
> the chameleon help here..
>
> It has DB-25 parallel ports on both sides (I - O ) , how is the debug-port
> (like COP) to be connected ?
>
> Kind Regards,
> Ravishankar

Since you havent got a reply from Larry let me answer you:

with chameleon you can either use existing configurations, or you can
create your own LPT-ADAPTER if you know the function-schematic.

just create the project with ISE, as output generate XSVF with OLD
version of XSVF tool !! rename the file to .ASVF then you can use
amontec
tool to reconfire chameleon.

or if you have modified XSVF player then you can use latest version of
XSVF also.

have fun!

Antti













Article: 121127
Subject: Re: Coding style of verilog for FPGA synthesis
From: Mir <irfanfaisalmir@gmail.com>
Date: Tue, 26 Jun 2007 00:55:58 -0700
Links: << >>  << T >>  << A >>

Hello,

It seem to be problem in your test bench (TB). I think you are try to
generate stimulus which does not support hardware wrt timing. Timing
simulation is the check for timing of your design.

First put timescale directive on the top of TB eg ( `timescale 1ns/
1ps)

Secondly check your input clock signal frequency in TB. I mean if you
are using statement like always #1 clk=~clk in Test bech. It means you
are generating 1GHz clock from TB.. be careful. You may also see other
input signals like clock in TB.

In short, if you get unknown or high-impedence valuse at th outputs..
it does not mean your design is BAD. First you should check the
stimulus. It may wrong..

GOOD LUCK

Regards,
Mir


Article: 121128
Subject: Re: VGA 1080x1920 pixel chipset
From: "MH" <blah@blahblah.blah>
Date: Tue, 26 Jun 2007 10:14:46 +0100
Links: << >>  << T >>  << A >>
"vasile" <piclist9@gmail.com> wrote in message news:1182833447.150084.178110@w5g2000hsg.googlegroups.com...
> Hi,
> I need a VGA 1080x1920 chip supporting HDTV. Anyone here has used
> before such IC ?
>
> thank you,
> Vasile
>


Check out the Virtex-5 based Advanced Video Development Platform
from IPT. This contains an Analog Devices ADV7321 DAC chip, which
is perfectly capable of outputting 1920 x 1080 analog video in RGB or YPbPr.
http://www.imageproc.com/xilinx.php


MH.



Article: 121129
Subject: Re: Trouble using DCMs in EDK 8.2
From: Perry <lipeng.net@gmail.com>
Date: Tue, 26 Jun 2007 03:35:28 -0700
Links: << >>  << T >>  << A >>
On Jun 26, 2:19 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote:
> Perry wrote:
> > On Jun 25, 10:01 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote:
>
> >>I'm currently developing a design for the XUP development board. The
> >>development software is Xilinx EDk 8.2
> >>The system requires several frequencies.
>
> >>Power PC : 100 MHz
> >>PLB      : 50 MHz
>
> >>User IP  : 50 MHz, 2.5 MHz
>
> >>The EDK uses DCM_0 to divide the 100 MHz by 2. I use 2 cascaded DCMs to
> >>generate the 2.5 MHz (first divides by 2, second divides by 10).
> >>But when I want to generate the bitstream the following messages and
> >>errors occur:
>
> >>INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not
> >>connected
> >>    to an external port in this design.  A new port
> >>    'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected
> >>to this
> >>    signal.
> >>INFO:NgdBuild:889 - Pad net
>
> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
> >>    is not connected to an external port in this design.  A new port
>
> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
> >>    has been added and is connected to this signal.
>
> >>Applying constraints in "xup_morpheus5.ucf" to the design...
>
> >>Checking timing specifications ...
> >>INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
> >>    "TS_sys_clk_pin", was traced into DCM instance
> >>    "dcm_0/dcm_0/Using_Virtex.DCM_INST". The following new TNM groups
> >>and period
> >>    specifications were generated at the DCM output(s):
> >>    CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD dcm_0_dcm_0_CLK2X_BUF
> >>TS_sys_clk_pin/2
> >>HIGH 50%
> >>    CLKDV: TS_dcm_0_dcm_0_CLKDV_BUF=PERIOD dcm_0_dcm_0_CLKDV_BUF
> >>TS_sys_clk_pin*2
> >>HIGH 50%
> >>INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLKDV_BUF", used in period
> >>specification
> >>    "TS_dcm_0_dcm_0_CLKDV_BUF", was traced into DCM instance
>
> >>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I
> >>    /DCM_INST". The following new TNM groups and period specifications were
> >>    generated at the DCM output(s):
> >>    CLKDV:
> >>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_
> >>CLKDV_BUF=PERIOD
> >>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK
> >>DV_BUF TS_dcm_0_dcm_0_CLKDV_BUF*2 HIGH 50%
> >>INFO:XdmHelpers:851 - TNM
>
> >>"board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I
> >>    _CLKDV_BUF", used in period specification
>
> >>"TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbi
> >>    t_I_CLKDV_BUF", was traced into DCM instance
>
> >>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_2
> >>    _I/DCM_INST". The following new TNM groups and period specifications
> >>were
> >>    generated at the DCM output(s):
> >>    CLKDV:
> >>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_
> >>I_CLKDV_BUF=PERIOD
> >>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C
> >>LKDV_BUF
> >>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_
> >>CLKDV_BUF*10 HIGH 50%
>
> >>ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has
> >>    multiple driver(s):
> >>      pin PAD on block
>
> >>plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BR
> >>    AM_Clk with type PAD,
> >>      pin O on block dcm_0/dcm_0/Using_BUGF_for_CLKDV.CLKDV_BUFG_INST
> >>with type
> >>    BUFG
> >>ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk'
> >>is driving non-buffer primitives:
> >>  pin C on block reset_block/reset_block/core_cnt_en with type FD,
> >>  pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type FD,
> >>  pin C on block reset_block/reset_block/Rstc405resetchip with type FD,
> >>  pin C on block reset_block/reset_block/Peripheral_Reset_0 with type FD,
> >>  pin C on block reset_block/reset_block/Rstc405resetsys with type FD,
> >>  pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type FD,
> >>  pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type FDRE,
> >>  pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type FDRE,
> >>  pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type FDRE,
> >>  pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type FDRE,
> >>  pin C on block reset_block/reset_block/SEQ/pr_dec_0 with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/pr_dec_1 with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/chip_dec_0 with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/chip_dec_2 with type FD,
> >>  pin C on block reset_block/reset_block/SEQ/pr_dec_2 with type FD,
> >>  pin C on block reset_block/reset_block/SEQ/chip_dec_1 with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/bsr_dec_0 with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/bsr_dec_2 with type FD,
> >>  pin C on block reset_block/reset_block/SEQ/seq_clr with type FDR,
> >>  pin C on block reset_block/reset_block/SEQ/ris_edge with type FDR
>
> >>ERROR:NgdBuild:455 - logical net
>
> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
> >>  has multiple driver(s):
> >>      pin O on block
>
> >>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/
> >>    CLKDV_BUFG_INST with type BUFG,
> >>    pin PAD on block
> >>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1
> >>    with type PAD
>
> >>ERROR:NgdBuild:924 - input pad net
>
> >>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
> >>    is driving non-buffer primitives:
> >>      pin O on block
>
> >>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/
> >>    CLKDV_BUFG_INST with type BUFG
>
> >>Does anybody know this problem. I did not apply any changes to the
> >>PLB_BRAM_IF_CNTL. Do I have to specify the new clock lines in one of the
> >>EDK files?
>
> >>Thanks in advance
> >>Sebastian Goller
>
> > It seems that you have connected more than one nets to the same output
> > or inout port.
>
> I already checked the source code and the edif netlist
> (design_analyzer). Everything is okay. The point that confuses me the
> most is, that the error regarding plb_bram_if_cntlr_1_port_BRAM_Clk
> occurs when I use the DCM_0 in the EDK. If I use the same frequency for
> the PowerPC and the PLB there is no problem at all.
> Same thing with the two cascaded DCMs in the user IP. No signal has more
> than one driver.
> The simulation of the behavioral model and the structural model works fine.
> Is there anything I have to add to the .mhs or the .mpd or to another file?
> I have already tried to modify the .ucf-file. I added the following lines
>
> Net "sys_clk_s" TNM_NET = "sys_clk_s";
> TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" "TS_sys_clk_pin"/2;
> Net "board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1"
> TNM_NET = "clkdv_dcm1";
> TIMESPEC "TS_clkdv_dcm1" = PERIOD "clkdv_dcm1" "TS_sys_clk_s"/2;
>
> After restarting NGDBUILD the following error occurs:
>
> INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not
> connected
>     to an external port in this design.  A new port
>     'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected
> to this
>     signal.
> INFO:NgdBuild:889 - Pad net
>
> 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>     is not connected to an external port in this design.  A new port
>
> 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>     has been added and is connected to this signal.
>
> Applying constraints in "xup_morpheus5.ucf" to the design...
> INFO:NgdBuild:757 - Line 14 in 'xup_morpheus5.ucf': The constraint for NET
>     'sys_clk_s' is being attached to the equivalent NET
>     'plb_bram_if_cntlr_1_port_BRAM_Clk'.
> ERROR:NgdBuild:756 - Line 16 in 'xup_morpheus5.ucf': Could not find net(s)
>     'board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' in the
> design.
>     To suppress this error specify the correct net name or remove the
> constraint.
> ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
> ERROR:NgdBuild:19 - Errors found while parsing constraint file
>     "xup_morpheus5.ucf".
>
> What I do not understand is that NGDBUILD gives me an information about
> the signal
> "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1"
> and five seconds later the signal can not be found in the design.

You set timing constraint for "board1_unit_0/board1_unit_0/
USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1", but you didnt specify
a pin for it. Try to set a pin constraint for it.


Article: 121130
Subject: Re: How to choose FPGA for a huge computation?
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: Tue, 26 Jun 2007 04:12:39 -0700
Links: << >>  << T >>  << A >>
Yes. I should rewrite it:

double a[ii][jj][kk];
double b[ii][jj][kk];
double c[ii][jj][kk];
double d[ii][jj][kk];
int i,j,m;
for (i=1;i<ii;i++)
    for (j=1;j<jj;j++)
        for (k=1;k<kk;k++)
            c[i][j][k] = (a[i][j][k] * b[i+1][j-1][k+1] + c[i-1][j+1]
[k]) / d[i-2][j-2][k-2];

The index number varies. I show above is just for example.

There are about 7 stages sequentially in the whole algorithm, and each
stage has the similar nested loop operation. The data needed by the
next stage depends upon the calculation results from the previous
stage.

So how to deal with this kind of problem?


Article: 121131
Subject: Re: Coding style of verilog for FPGA synthesis
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 26 Jun 2007 06:00:27 -0700
Links: << >>  << T >>  << A >>
Allen wrote:

> We design a hardware written in Verilog and synthesize by Synopsys
> Design Vision.
> The post-synthesis simulation is shown that the function of hardware
> is correct.
> Now, we are going to verify function of hardware by downloading it to
> Xilinx FPGA.
> We synthsize the hardware design by using ISE 7.1i. Unfortunately, the
> post-synthesis simulation failed ( all the output is unknown or high-
> impeadance). I tried to synthesize with keeping hierarchy, but it
> still unuseful.
> 
> What can I do next step? We don't have much experience in this field.

I would get the latest ISE 9.1 and try synthesis using that.

  -- Mike Treseler

Article: 121132
Subject: Re: Multidimensional Register in Modul Port List
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 26 Jun 2007 14:37:47 +0100
Links: << >>  << T >>  << A >>
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:oopv731n9ua58ql7qn2biakupqgiq4t1v1@4ax.com...
>
> Your mileage may vary, but I think this shows promise.  The synth
> tool I tried made a really excellent job of this, using a tree
> of LUTs in the obvious optimal way.  It didn't, though, use
> carry chains - sorry Symon!
> -- 
>
Hi Jonathan,
It might need a little 'massage' to get it to use the chains. The chain 
method can detect a single '0' on its inputs. (In normal use the chain 
detects all ones meaning carry...) So, we need a bunch of 4 input, i.e. LUT 
sized, NOR gates to feed the chain. If any input to the OR gates is high, 
the output of that or gate goes low, and thus the output of the chain can go 
high (or low depending on what constant is on the di inputs of the MUXCYs).
Maybe the synthesis tool needs the thing to be coded with these NOR gates in 
mind to use the chains? I just instantiate them, but there you go...
Anyway, interesting stuff, and very timely for my project! Ta very much!
Cheers, Syms. 



Article: 121133
Subject: Re: Desperate to find the right FPGA board
From: PFC <lists@peufeu.com>
Date: Tue, 26 Jun 2007 16:14:09 +0200
Links: << >>  << T >>  << A >>
On Mon, 25 Jun 2007 12:48:22 +0200, John Adair <g1@enterpoint.co.uk> wrote:

> We do an Ethernet module for a Raggedstone1development board. The only
> problem is we are out of stock on Ethernet Phy module. We expect these
> back in about 4 weeks.
>
> Raggedstone1 details here  
> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html.
>
> We also have other modules coming that will offer some high speed link
> capability to other boards. These will be announced as soon as we get
> them built and tested.
>
> John Adair
> Enterpoint Ltd.
>
	Your Darnaw1 + a PHY module is in my shortlist. I sent you an email, BTW.
	Can you give more details about upcoming gear ? If it looks good I may  
decide to wait.

	Thanks.

Article: 121134
Subject: Re: How to choose FPGA for a huge computation?
From: PFC <lists@peufeu.com>
Date: Tue, 26 Jun 2007 16:27:18 +0200
Links: << >>  << T >>  << A >>
> Yes. I should rewrite it:

> double a[ii][jj][kk];
> double b[ii][jj][kk];
> double c[ii][jj][kk];
> double d[ii][jj][kk];
> int i,j,m;
> for (i=1;i<ii;i++)
>     for (j=1;j<jj;j++)
>         for (k=1;k<kk;k++)
>             c[i][j][k] = (a[i][j][k] * b[i+1][j-1][k+1] + c[i-1][j+1]
> [k]) / d[i-2][j-2][k-2];

> The index number varies. I show above is just for example.

> There are about 7 stages sequentially in the whole algorithm, and each
> stage has the similar nested loop operation. The data needed by the
> next stage depends upon the calculation results from the previous
> stage.

> So how to deal with this kind of problem?

        More questions.

        I assume you have to do this computation repeatedly ? Which part of the  
computation changes between runs ? All of a,b,c,d, or just one or two ? Or  
just the offsets, maybe ?
        Do your 7 stages each use the value of c computed from the previous  
stages ? Does each stage use the same a,b,d as the previous ones, or  
different ? 

Article: 121135
Subject: Re: DARNAW! - PGA Style FPGA Module
From: PFC <lists@peufeu.com>
Date: Tue, 26 Jun 2007 16:40:00 +0200
Links: << >>  << T >>  << A >>

>> Finally first picture of Darnaw1 our PGA style FPGA board is here here
>> http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on
>> pricing and spec in the next couple of days will appear on the
>> website. Those with eagle eyes can work it out the spec from the
>> picture.
>>
>> First shipments will have 16Mbit SPI flash to allow programming of the
>> FPGA but also to act as a code store for processors like MicroBlaze
>> implemented within the FPGA. There is also SDRAM on board. Small
>> numbers of this product will be available to ship next week.
>>
>> We would be interested to have feedback on this product and what you
>> like, and what we could improve on this product and the related series
>> of products we have planned.

	Point :

	There is no FPGA module on the market with the following characteristics :

	- FPGA large enough to fit Microblaze and user cores (the Darnaw has it !)
	- Big, FAST RAM (the Darnaw has it !) so we can use xilinx cache links  
and DMA core and not be limited by a single slow SDRAM chip
	- CHEAP (your price for the Darnaw is good ! much better than competitors)
	- Easy to use connector : I think the PGA socket sucks.
	I would prefer a module shaped like a laptop SDRAM stick, sell the  
connector with it, much easier to plug and use, easier to route the PCB  
for it, better signal integrity. Plus, it's cheaper to manufacture for you  
!
	- Ethernet PHY to use OpenCores MAC core (damn, Darnaw doesn't have it,  
but you sell some as extra modules, so it's OK)

	So, here is the feedback ;)
	Can we get more info about the upcoming modules ?

Article: 121136
Subject: Re: Confused about FPGA devices recommended by Xilinx for my FFT project
From: Telenochek <elet.mirror@gmail.com>
Date: Tue, 26 Jun 2007 15:48:22 -0000
Links: << >>  << T >>  << A >>


Thanks!



Article: 121137
Subject: Xilinx ISE 9.1 - Version Control - VSS
From: "Jeremy" <jeremylees@hotmail.com>
Date: Tue, 26 Jun 2007 12:48:07 -0500
Links: << >>  << T >>  << A >>
Greetings,

Has anyone used Microsoft Visual Source Safe or any other software version control applications to manage ISE projects? More specifically what files are required to be maintained to keep a project intact, and which files can be regenerated through Synthesis and Place and Route?

Regards,
Jeremy

Article: 121138
Subject: Re: How to choose FPGA for a huge computation?
From: ajjc <ajjc@optngn.com>
Date: Tue, 26 Jun 2007 11:00:24 -0700
Links: << >>  << T >>  << A >>
On Jun 26, 4:12 am, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote:
> Yes. I should rewrite it:
>
> double a[ii][jj][kk];
> double b[ii][jj][kk];
> double c[ii][jj][kk];
> double d[ii][jj][kk];
> int i,j,m;
> for (i=1;i<ii;i++)
>     for (j=1;j<jj;j++)
>         for (k=1;k<kk;k++)
>             c[i][j][k] = (a[i][j][k] * b[i+1][j-1][k+1] + c[i-1][j+1]
> [k]) / d[i-2][j-2][k-2];
>
> The index number varies. I show above is just for example.
>
> There are about 7 stages sequentially in the whole algorithm, and each
> stage has the similar nested loop operation. The data needed by the
> next stage depends upon the calculation results from the previous
> stage.
>
> So how to deal with this kind of problem?

It is hard to see exactly what you are doing without seeing
it...*grin*...
but in that spirit, check out the paper:

APPLICATION-SPECIFIC MEMORY INTERLEAVING FOR FPGA-BASED GRID
COMPUTATIONS: A GENERAL DESIGN TECHNIQUE, byTom VanCourt and Martin
Herbordt
http://www.bu.edu/caadlab/FPL06_mem.pdf

alan


Article: 121139
Subject: Re: Xilinx ISE 9.1 - Version Control - VSS
From: Alex Colvin <alexc@TheWorld.com>
Date: Tue, 26 Jun 2007 18:13:07 +0000 (UTC)
Links: << >>  << T >>  << A >>
>Has anyone used Microsoft Visual Source Safe or any other software version control applications to manage ISE projects? More specifically what files are required to be maintained to keep a project intact, and which files can be regenerated through Synthesis and Place and Route?

allegedly, a Microsoft employee has been quoted as saying, "Visual 
SourceSafe?  It would be safer to print out all your code, run it through 
a shredder, and set it on fire."

I've used CVS, with VHDL source files in a top-level directory, and ISE
project files in a subdirectory "ISE" (so that ISE stores all its other
cruft there).

Source files and ISE/*.ise project go into CVS. Also *.xco and ISE/*.edn
and ISE/*.ngc files created from core generator. For good measure, I check
in the ISE/*.bit bitstream, just so I can test versions quickly and so I
don't don't need to have the XIlinx tools to get it.

The goal is to save everything necessary as well as anything convenient,
and make it easy to rebuild the project should I totally mess up ISE. If
necessary, I can reconstruct the ISE files. All this uses a remote CVS
repository from a machine that has no backup.

-- 
	mac the na´f

Article: 121140
Subject: Re: Xilinx ISE 9.1 - Version Control - VSS
From: Alex Colvin <alexc@TheWorld.com>
Date: Tue, 26 Jun 2007 18:30:41 +0000 (UTC)
Links: << >>  << T >>  << A >>
>The goal is to save everything necessary as well as anything convenient,
>and make it easy to rebuild the project should I totally mess up ISE. If
>necessary, I can reconstruct the ISE files. All this uses a remote CVS
>repository from a machine that has no backup.

errr.. the development machine has no backup. the CVS repository machine 
has backup and no development.
-- 
	mac the na´f

Article: 121141
Subject: regarding the montavista linux preview kit
From: "N.V. Chandramouli" <mouli1982@gmail.com>
Date: Tue, 26 Jun 2007 18:46:37 -0000
Links: << >>  << T >>  << A >>
Dear all,
           I am working on Virtex-4 Fx12LC (ML 403 ) Fpga that has
powerpc hard core.
I would want to load Linux RTOS onto it and try and access the on chip
memory and Fpga logic from that.
May I know if any body has the preview kit for Linux for that version
of the VIrtex-4 FPGA.
It would be great if they can disclose the details as to where can I
find the same.
thanks and regards
vijay


Article: 121142
Subject: Re: Xilinx ISE 9.1 - Version Control - VSS
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 26 Jun 2007 20:26:33 +0100
Links: << >>  << T >>  << A >>
http://en.wikipedia.org/wiki/Subversion_(software) 



Article: 121143
Subject: Re: Xilinx ISE 9.1 - Version Control - VSS
From: Matthew Hicks <mdhicks2@uiuc.edu>
Date: Tue, 26 Jun 2007 19:46:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
Our research group uses subversion, I've interned at places that use CVS 
(they wanted to move to subversion), and I think ISE has a built-in versioning 
system.


---Matthew Hicks


> Greetings,
> 
> Has anyone used Microsoft Visual Source Safe or any other software
> version control applications to manage ISE projects? More specifically
> what files are required to be maintained to keep a project intact, and
> which files can be regenerated through Synthesis and Place and Route?
> 
> Regards,
> Jeremy



Article: 121144
Subject: Can FPGAs inputs detect low currents?
From: Marc Weber <marco-oweber@gmx.de>
Date: Tue, 26 Jun 2007 22:31:58 +0200 (CEST)
Links: << >>  << T >>  << A >>
Hello

I'm new to FPGAs.

I need some kind of 30-40 channel input extension beeing able to detect
0.01mA currents. (The current should flow through your fingrs .. ;)
I already know that implementing some kind of multiplexer is no problem.
But can I use a FPGA as well to detect these low currents?
This could be done by a analog comparator or by amplifying using two
transistors.

Of course this could be done using asics. But I don't know wether I need
that a high volume to pay off.

Marc Weber

Article: 121145
Subject: Re: Can FPGAs inputs detect low currents?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 26 Jun 2007 13:51:11 -0700
Links: << >>  << T >>  << A >>
If you read the data sheet, you find a 10 microamp max leakage current
specification. That is the same magnitude as your sense current. Looks
like a problem...
Let me tell you a secret: Th FPGA input leakage current is in reality
much lower. We specify 10 microamp because that is easy to test, and
the fall-out is zero.

My suggestion: Try a few Xilinx FPGAs or CPLDs, make sure that the
output (on that same pin) is 3-stated, and then use a 1 Megohm
resistor and a +/- 10 V power supply to measure the threshold voltage
and leakage current.
It should work just fine for you.
Peter Alfke, Xilinx Applications

On Jun 26, 1:31 pm, Marc Weber <marco-owe...@gmx.de> wrote:
> Hello
>
> I'm new to FPGAs.
>
> I need some kind of 30-40 channel input extension beeing able to detect
> 0.01mA currents. (The current should flow through your fingrs .. ;)
> I already know that implementing some kind of multiplexer is no problem.
> But can I use a FPGA as well to detect these low currents?
> This could be done by a analog comparator or by amplifying using two
> transistors.
>
> Of course this could be done using asics. But I don't know wether I need
> that a high volume to pay off.
>
> Marc Weber



Article: 121146
Subject: Re: Can FPGAs inputs detect low currents?
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 26 Jun 2007 13:57:56 -0700
Links: << >>  << T >>  << A >>
"Marc Weber" <marco-oweber@gmx.de> wrote in message 
news:f5rt3u$hkv$1@aioe.org...
> Hello
>
> I'm new to FPGAs.
>
> I need some kind of 30-40 channel input extension beeing able to detect
> 0.01mA currents. (The current should flow through your fingrs .. ;)
> I already know that implementing some kind of multiplexer is no problem.
> But can I use a FPGA as well to detect these low currents?
> This could be done by a analog comparator or by amplifying using two
> transistors.
>
> Of course this could be done using asics. But I don't know wether I need
> that a high volume to pay off.
>
> Marc Weber

For current that flows through one's fingers, is there enough ESD protection 
for your needs?  FPGAs are more robust than some circuits but give it a zap 
with some fingers fresh off the dry, winter carpet and TSZAAAP!!!!  No more 
FPGA.

Is finger current sensing what you need or simply what you think may work 
well?  There are capacitive touch sensor techniques being promoted by the 
likes of Analog Devices (REAL nice capacitive sensor) and Cypress with their 
CapSense technology.  You can keep all your sensitive silicon insulated from 
the vicious outside world.

- John_H 



Article: 121147
Subject: Re: Can FPGAs inputs detect low currents?
From: austin <austin@xilinx.com>
Date: Tue, 26 Jun 2007 13:58:57 -0700
Links: << >>  << T >>  << A >>
Marc,

In every IOB, in every Virtex E, Virtex 2, Virtex 2P, Virtex 4, Virtex
5, and every Spartan 3, 3E, 3A, 3AN there is:

a CMOS differential input comparator.

Unfortunately the leakage current specification for any IO pin is +/- 10uA.

Your signal, .01mA IS 10 uA! so we can not be used The signal you need
to detect is the same size as the leakage variations).

Leakage below 10uA takes a very high quality comparator (expensive), so
I doubt there are any 'simple' solutions (like you claim).

"Any ASIC" would also require less than 1uA pin leakage, which is
non-trivial.  Low leakage means the pin has very little ESD protection
(ESD protection results in more potential for leakage).

Good luck.  Perhaps there is a low cost, low leakage quad comparator
which could be used for detection before the FPGA?

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3986
(15nA leakage)

Austin

Article: 121148
Subject: Re: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
From: i_s_uzun@yahoo.com
Date: Tue, 26 Jun 2007 14:00:21 -0700
Links: << >>  << T >>  << A >>
Hello,

You can use following product from FTDI.

DLP Design - DLP-2232M-G : http://www.ftdichip.com/Products/EvaluationKits/DIPModules.htm

To interface with the USB chip, I suggest you use picoblaze. If you
need the picoblaze code, let me know.

Isa


Article: 121149
Subject: CameraLink to Hotlink-II video converter
From: Rotem Gazit <rotem.gazit@gmail.com>
Date: Tue, 26 Jun 2007 14:12:41 -0700
Links: << >>  << T >>  << A >>
Hi All,
We are looking for a board (or adaptor) able to convert CameraLink
video to Hotlink-II.

Thanks in advance,
Rotem




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search