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There isn't any maximum number of logic levels as far as I know. Its just the more levels you have the slower your chip will be. In a recent project we has 20 levels in a Vertex 2 and ran at 20MHz. The cell interconnect tends to dominate the delay (as opposed to cell delay) in automatically placed designs. Something like 80/20 is not uncommon. Regards jaiphen_interqos@yahoo.com.hk (starpanda) wrote in message news:<64c11999.0202190148.2ee494e@posting.google.com>... > Hi, > Is there anyone knows the maximum # of logic level for Xilinx FPGA? > Because I remeber if the # of logic level is too large will affect the > performance of the design.Article: 39776
If you're running with a delay annotated netlist then you shouldn't be getting any warnings. If you using the Xilinx mem timing models with RTL then I could understand the warnings. You could make a non-timing mem model for RTL sim or you could put a simulation delay in the address lines that are ignored at synthesis. Something like wire //synopsys translate_off #1 //synopsys translate_on slow_we=we; Regards p.s. I don't recommend going to negative edge to solve simulation model issues. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a4rkqa$2h9g7$2@ID-84877.news.dfncis.de>... > "Antonio" <dottavio@ised.it> schrieb im Newsbeitrag > news:fb35ea96.0202172343.7ae21d4b@posting.google.com... > > > # : WARNING: */RAMB4_S1 SETUP High VIOLATION ON ADDR(8) WITH RESPECT > > TO CLK; > > # : Expected := 0.01 ns; Observed := 0 ns; At : 1275 ns > > # : Time: 1275 ns, Iteration: 3, Instance: /U1/U2/U2/B13. > > # : WARNING: */RAMB4_S1 SETUP Low VIOLATION ON ADDR(7) WITH RESPECT TO > > CLK; > > # : Expected := 0.01 ns; Observed := 0 ns; At : 1275 ns > > # : Time: 1275 ns, Iteration: 3, Instance: /U1/U2/U2/B13. > > I think this problem has been discussed recently, its a bug in the > simulation model of the RAM. > > > and really many other similar warnings, but let's try to understand > > what the error say, > > the problem is that the clock and the address change on the same time > > while from data_sheets > > seems that the address must arrive a little bit before 0.01ns. > > Yes, a "little" bit more, so 2ns or so. ;-) > > > > > The only rimedy I know is to change the operating edge of the ram so > > now the address change on > > negative edge of the clock and the ram work on positive edge. Now the > > simulation it's ok but > > the speed on FPGA is reduced to 45MHz. > > This is clear, since the address changes on the negative edge and has so > only 1/2 clock cycle to propaget to the RAM. Switch back to te positive edge > and ignore the warning of the simulator. If you have a clean synchronous > design, just look at the timing analyzer, it will tell you how fast you can > go.Article: 39777
I don't think they do in that family. Depending on your application it may matter more or less. If you're using the FPGA as an ASIC proto you'd probably prefer the inferred multiplier style anyway. In order to use those hard macro's you have to manually instantiate them. Regards prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0202181110.5534bf79@posting.google.com>... > hi, > > Do Altera FPGAs (Apex 20KE) come with specifically provided > multipliers or do the multipliers in your design need to be considered > as part of the total gate count ? > > Thanks, > PrashantArticle: 39778
Have you experimented with other BIOS parallel port modes (EPP, ECP, SPP)? I have heard of problems in other non-printer parallel port applications using Dell. Regards "shiva kumar" <shivak210m@yahoo.com> wrote in message news:<ee74e9d.-1@WebX.sUN8CHnE>... > why does the JTAG CABLE not work on Dell systems for programming > vertex FPGA's.Article: 39779
Hi, I think their first devices with hardware multipliers is their new Stratix family. CU, CS > prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0202181110.5534bf79@posting.google.com>... > > hi, > > > > Do Altera FPGAs (Apex 20KE) come with specifically provided > > multipliers or do the multipliers in your design need to be considered > > as part of the total gate count ? > > > > Thanks, > > PrashantArticle: 39780
Insight sells a 2V1000 eval board...but it does not have a pci interface, something that's always handy... You may also want to check out the 'maxrevolution' board (use google) cheers, Seb "Salman Sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message news:20020219101741.6ec48d09.sheikh@pop500.gsfc.nasa.gov... > Hello, > > Anyone know of anybody who sells Development and/or prototype boards with a Virtex II 2V3000 or larger on it? I only have seen one with a 2V40 on it. > Thanks. > > > Salman > > > -- > Salman Sheikh > NASA/GSFC Code 564 > Greenbelt, MD 20771 > 301-286-3763 301-286-0220 (fax)Article: 39781
Apply the correct voltage...see if it programs If it's a 3.3V device, normally it can't cope with 5V. cheers, Seb "X. Q." <qijun@okigrp.com.sg> wrote in message news:3c71b28d@news.starhub.net.sg... > Hi, > > Last time I purchased a XC9572 CPLD and an SC2S100 Spartan-II chip. > I applied a 5V to it's VCCO. I want to know how to decide whether the chip > has been spoiled. > > Thanks. > >Article: 39782
i second this cheers, Seb "C.Schlehaus" <carlhermann.schlehaus@t-online.de> wrote in message news:a4u8i4$f0$05$1@news.t-online.com... > Hi, > I think their first devices with hardware multipliers is their new > Stratix family. > > CU, CS > > > prashantj@usa.net (Prashant) wrote in message > news:<ea62e09.0202181110.5534bf79@posting.google.com>... > > > hi, > > > > > > Do Altera FPGAs (Apex 20KE) come with specifically provided > > > multipliers or do the multipliers in your design need to be considered > > > as part of the total gate count ? > > > > > > Thanks, > > > Prashant > >Article: 39783
In article <u75b2r8rif62ed@corp.supernews.com>, Craig Ward <ccward@waitrose.com> wrote: >Hi, > >Can anyone give me advice on how to improve my clock speed in my design. I >am using timing constraints before you ask!!. >The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR >(ise 4.1etc). The delays in my design appear to be caused by a few long >nets >(fan out 1 etc). There is lots of free space on the chip so this is not a >problem. My target speed is 6.25ns period and the best I can get to is 7ns >etc with par effort at maximum. I have tried re-entrant routing with no >success. > >The design is still being updated and added to so can anyone tell me how I >can get better par in general ? I would imagine that manual placement would >give me better results in theory but then each time i changed the design I >would have to repeat this process?? Help! Well, the floorplanner helps and makes the process easier, but there are serious bugs in the 4.1 floorplanner. ObCouldYouJustAddAPipleineStage? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 39784
I am designing a system using a 100MHz clock. The orignal clock is a 3.3v LVPECL output. I will be distributing the clock differntially. I am wondering about any differential input standards for the Spartan2 that might be appropriate to this signal. (For example, there is a simple voltage divider conversion from LVPECL to LVDS.) Otherwise I will need to include a an LVPECL to LVTTL translator. This is not a big deal, but if I can avoid it, I would prefer to do so. Thanks, TheronArticle: 39785
Hello all, I know that this issue is well discussed in this newsgroup but still I have some questions. In a Virtex-E FPGA the setup time for the EN,WE signals are 2.5 ns and 2.2ns (plz confirm) but the setup time for the address,data is about 1.1ns (plz confirm). I want to use 3 BRAMs 128x32 in a Virtex-E 600 (speed grade 6) @ 77 MHz (or clock period=12ns), do I have to keep the "input" signals stable for 2 clock periods to succeed a correct timing in the read/write operations or is it totally wrong (except for too slow)? Best Regards, HarrisArticle: 39786
"X. Q." <qijun@okigrp.com.sg> writes: > Last time I purchased a XC9572 CPLD and an SC2S100 Spartan-II chip. > I applied a 5V to it's VCCO. I want to know how to decide whether the chip > has been spoiled. Try using it correctly. If it works, it isn't *completely* broken.Article: 39787
I've had problems with Dell parallel ports with other devices. The fix for me has been to use an old parallel port zip drive to buffer the signal! I'm not sure this will help in this case, but if you can find an old zip drive, it's worth a try!Article: 39788
Hallo! I'm trying to put my small design into a MAX3064ATC44 but would really like more than the 64 registers this device offers me. I do want to keep the 44 pin TQFP, but maybe 96 or even 128 registers would be nice. Any suggestions? Frank -- ------------------------------------------------------------------------ Frank A. Vorstenbosch <SPAM_ACCEPT="NONE"> Phone: +44-7976-430 569 Wimbledon, London SW19 frank@kingswood-consulting.co.ukArticle: 39789
"Craig Ward" <ccward@waitrose.com> schrieb im Newsbeitrag news:u75b2r8rif62ed@corp.supernews.com... > Hi, > > Can anyone give me advice on how to improve my clock speed in my design. I > am using timing constraints before you ask!!. ;-)) Yes, this is one thing. But a timing constraint is no magic word that creates fast logic. Its just a request to the tools, "Please, I would like to run this clock very fast, can you do anything for me?" And sometimes your prayers will be heard and the design will meet timing. ;-) > The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR Fine, but this does not mean too much. If you have a bad coding style, also the good synthesizer cant help you. YOu should provid some informations about the design (general function, does is use BLOCKRAM, selectRAM , big MUXEX etc. > (ise 4.1etc). The delays in my design appear to be caused by a few long > nets > (fan out 1 etc). There is lots of free space on the chip so this is not a This does not mean so much. > problem. My target speed is 6.25ns period and the best I can get to is 7ns Hmm, close, but still not fast enough. > etc with par effort at maximum. I have tried re-entrant routing with no > success. Have a look at the timing analyzer. It will tell you, which path is too slow. then you can in parallel open the floorplanner, it will show you where the logic elements are placed. Most it tuns out that the automatic placer is a little bit stupid, but not always. then you can rearange the placement and run a second P&R (now with YOUR placement) > > The design is still being updated and added to so can anyone tell me how I > can get better par in general ? I would imagine that manual placement would > give me better results in theory but then each time i changed the design I > would have to repeat this process?? Help! In general yes, but not at all. You can (should) split your design into functional blocks and try to optimize them individual. See some of the coding style guides on the net (or in the Xilinx Doc) for further hints. -- MfG FalkArticle: 39790
Frank Vorstenbosch wrote: > > Hallo! > > I'm trying to put my small design into a MAX3064ATC44 but would really > like more than the 64 registers this device offers me. I do want to > keep the 44 pin TQFP, but maybe 96 or even 128 registers would be nice. > 64 macrocells in TQFP44 is the industry ceiling. Depending on your logic mapping, you could use the Atmel ATF1504. This allows logic doubling, via dual feedback paths, so you can pack more into a 44 pin package. Pin latches can be synthesised, and a register buried to get 2 latches per PIN macrocell. Foldback paths also give more usefull logic. If you need 128 x D FF's, you'll need a TQFP100 -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 39791
Chris Dick <chrisd@xilinx.com> wrote in message news:<3C721519.23C0FF6@xilinx.com>... > Hi, I was wondering if you managed to resolve your problem with the halfband filter? > > best regards > > Chris > Chris, Check out Yury's reply dated Jan 25, 2002 in this thread. NewmanArticle: 39792
First off, your target clock it pretty high by FPGA statndards, but certainly acheivable depending on what you are trying to accomplish. Since it sounds like you've exhausted the tool control knob options, I'd suggest you look at pipelining more of your design, more registers, anywhere you can put them. Stuff like smaller state machines, instead of one big mother, have a bunch of baby ones triggering each other, stuff like that. Look at your longet paths and ask yourself "Why is this signal here?" Hope that helps, Regards "Craig Ward" <ccward@waitrose.com> wrote in message news:<u75b2r8rif62ed@corp.supernews.com>... > Hi, > > Can anyone give me advice on how to improve my clock speed in my design. I > am using timing constraints before you ask!!. > The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR > (ise 4.1etc). The delays in my design appear to be caused by a few long > nets > (fan out 1 etc). There is lots of free space on the chip so this is not a > problem. My target speed is 6.25ns period and the best I can get to is 7ns > etc with par effort at maximum. I have tried re-entrant routing with no > success. > > The design is still being updated and added to so can anyone tell me how I > can get better par in general ? I would imagine that manual placement would > give me better results in theory but then each time i changed the design I > would have to repeat this process?? Help! > > Cheers > CraigArticle: 39793
> (fan out 1 etc). There is lots of free space on the chip so this is not a > problem. My target speed is 6.25ns period and the best I can get to is 7ns > etc with par effort at maximum. I have tried re-entrant routing with no > success. > Craig, Have you tried Multi Pass Place and Route? This tool uses different cost tables to try different placement schemes, of which, one or more of them may meet your timing criteria. NewmanArticle: 39794
You could put series resistors between the uP outputs and the CPLD JTAG inputs so that the external JTAG can overdrive the uP when the cable is connected. When the cable isn't connected, the uP drives (more slowly) those lines. David Hawke <dhawke@xilinx.com> wrote in message news:<3C7295D8.348AC6E1@xilinx.com>... > Rick, > > Just connect the port to the MCU, implement an SVF player in the MCU > (details on our web site), and then ensure that the MCU cannot drive when > the board is being boundary scanned. > > Dave > > rickman wrote: > > > I think I may have missed a significant point about the Coolrunner CPLDs > > and ISP. I picked the XCR3256XL because I needed to be able to do > > boundary scan on the board for production test and I wanted to be able > > to change the design on the fly (meaning from the MCU on the board). But > > it looks like the only way to program this part is to use the JTAG port. > > Connecting the JTAG port to the MCU prevents me from using the JTAG port > > for boundary scan. > > > > Am I missing something? Does ISP mean connecting the board to a PC > > through a JTAG cable? Is that the only way I can program an XPLA3 part? > > I could replace this part with a 3.3 volt FPGA, but I hate to do that > > since I expect 3.3 volt FPGAs will be going the way of the dodo bird in > > a year or two and they are not cheap in the meantime. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > --Article: 39795
I would have to say that they are already optimized. Indeed, the multiplier performance is a bench mark by which many FPGA vendors are judged, so I'd imagine some effort has been expended in this direction. However, having said that, I think its a great project. Being a newbe, means you are not prejudiced by the existing art, and are more free to consider novel approaches the old times ruled out long ago for now obsolete reasons. Przemyslaw Wegrzyn <czajnik@czajsoft.pl> wrote in message news:<a4rh5v$9bs$1@panorama.wcss.wroc.pl>... > Hello ! > > I need to implement signed 16x16 bit multiplier in my graduate project, I'm > going to use Spartan-II device. > > The question is: > Are the multipliers generated by Xilinx's Multiplier Generator v4.0 IP well > optimized ? > Can I gain any better performance/resource utilisation building a > multiplier block myself (at reasonable effort) ? > > P.WegrzynArticle: 39796
FYI, I reported a similar problem to this newsgroup recently except my platform is a Virtex II. Turned out we have engineering sample parts in our boards which apparently do not have working SRL16 components which prevents the serialized filters from working. Clark "Chris Dick" <chrisd@xilinx.com> wrote in message news:3C721519.23C0FF6@xilinx.com... > Hi, I was wondering if you managed to resolve your problem with the halfband filter? > > best regards > > Chris > > Yury wrote: > > > newman5382@aol.com (newman) wrote in message news:<e6038423.0201180501.c52e394@posting.google.com>... > > > yuryws@optonline.com (Yury) wrote in message news:<fb9fd058.0201172014.12b797fa@posting.google.com>... > > > > Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. > > > > Pre-synthesis simulation looks excellent, however when the filter is > > > > loaded into Spartan-II the output looks like complete random junk. All > > > > timing is met. > > > > > > > > Does anyone have a similar experience or an idea for a potential > > > > problem area? > > > > > > > > Thanks. > > > > > > I have not used this Coregen IP, but you mentioned that the > > > Pre-synthesis simulations look excellent. How about post PAR > > > simulations? One can also do an inbetween post PAR simulation without > > > the SDF if need be. The reason I mention this is maybe the > > > constraints need a little bit more work. > > > > > > Are you sure the digital input data is frequency limited to within > > > your > > > digital filter's specifications? > > > > > > Are you using DLL's?, they have min/max frequency and jitter > > > specifications. > > > > > > Newman > > > > I stimulate the pre-synthesis design with a certain input data stream. > > I use the same stream as an input to a tool called Elanix (used for > > signal processing). The pre-synthesis output of Xilinx and the output > > of Elanix agree clock for clock for 64K samples (which indicates to me > > that the design is correct). I am starting to suspect the descrepancy > > between the Coregen model of the FIR and its behavioral VHDL > > description provided by the same Coregen. > > I have to do the post routing functional and/or timing simulation, but > > I have not gotten to it yet. > > > > DLLs are rock solid, their jitter is minimal (could not affetct the > > spectrum). > > > > The frequency content of the input data is irrelevant, since I compare > > the output of the Xilinx filter to that of an independent filter > > simulator. Even if the data is out of band the output smaples still > > should agree. > > > > Thanks > > -- > Dr Chris Dick > Xilinx DSP Group Manager > DSP Chief Architect > Xilinx Inc > 2100 Logic Drive > San Jose > CA 95124 > > Phone: 408.879.5377 > Fax: 408.626.6440 > eFax: 508.355.7668 > >Article: 39797
We recently upgraded our foundation ISE with a service pack. Now our filters using the Virtex II embedded multiplies is taking 12 ns instead of the 10ns we had before the upgrade.(Which probably reflects more accurate timing) I looked at the design in FPGA editor and found that even though the MULT component has a clock input our design is not using it(even though we've registered the i/o in VHDL). Does anyone now how to force the tools to use the clock input on the V2 MULT component from VHDL? Thanks, ClarkArticle: 39798
In general, the only thing you connect to the clk pin of a flop should be a wire from the a dedicated clock pin. The parts are really set up internally that way. I suppose you could use the GPIO input pin as an enable. Do something like run all the flops at higher frequency than the "count" signal. Then sample the GPIO count enable with the global clock (use 2 flops in series) and make a leading edge detector to use that single clock pulse as an enable to your counter. Regards "Robert VanRooyen" <rrooyen@lifewaveinc.com> wrote in message news:<u6qq057ndrho48@corp.supernews.com>... > Hello, > > I am having a fundamental clocking problem with sequential blocks within the > webpack schematic capture environment. I distilled my design down to a > single counter (CB4CE) that I want to clock from an external input pin that > is not a dedicated CLK[0..n] pin. The rising edge of my external input > should simply advance the counter. Under simulation (ModelSim) this works > fine but when I download it to the part (XCR3064XL-10VQ44C) it only toggles > bit0 of the counter and bit1-3 remain static. When I tie the dedicated CLK0 > (~32KHz) to the counter clock input then it works as expected in terms of > the counter output, i.e., bit0-3. This is the first time I've used the > webpack tools and I'm not sure if I need to do something "special" in order > to use external inputs to drive a rising edge clock input on a library > component. > > Here is the basic wiring list for the "simple" counter circuit; > -SERIAL_CLK (pin 43, B1) to rising edge of clock input of the CB4CE > -CE on CB4CE is tied to VCC > -CLR on CB4CE is tied to GND > -Q0 on CB4CE is tied to an OBUF which drives pin 35 (A0) to which is > attached an LED indicator > -Q1 on CB4CE is tied to an OBUF which drives pin 34 (A1) to which is > attached an LED indicator > -Q2 on CB4CE is tied to an OBUF which drives pin 33 (A8) to which is > attached an LED indicator > -Q3 on CB4CE is tied to an OBUF which drives pin 31 (A10) to which is > attached an LED indicator > > Recall that when I used the rising edge clock from the dedicated CLK0 input > (pin 40) into the CB4CE counter it works correctly in the simulator and when > it is running on the actual part. > > My conclusion thus far is that I cannot drive clock inputs on sequential > library devices directly from a generic input without doing something > special? I have tried running the external clock through a D-FLOP while > clocking it from the dedicated CLK0 and using the Q output to drive the > clock input on the CB4CE in the hope that the D-FLOP would somehow "qualify" > my clock input, but alas that didn't make any difference. > > Thanks, > > RobertArticle: 39799
Cheers for all the replys, I will having another go next week so hopefully I will have some success!! Cheers Craig Craig Ward <ccward@waitrose.com> wrote in message news:u75b2r8rif62ed@corp.supernews.com... > Hi, > > Can anyone give me advice on how to improve my clock speed in my design. I > am using timing constraints before you ask!!. > The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR > (ise 4.1etc). The delays in my design appear to be caused by a few long > nets > (fan out 1 etc). There is lots of free space on the chip so this is not a > problem. My target speed is 6.25ns period and the best I can get to is 7ns > etc with par effort at maximum. I have tried re-entrant routing with no > success. > > The design is still being updated and added to so can anyone tell me how I > can get better par in general ? I would imagine that manual placement would > give me better results in theory but then each time i changed the design I > would have to repeat this process?? Help! > > Cheers > Craig > >
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