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On Sunday, April 15, 2012 9:32:18 PM UTC+5:30, Frank Buss wrote: > manusha1980@gmail.com wrote: >=20 > > after few years i want to restart FPGA development once again - initial= ly for personel fun, but later may move in to commercial development too. A= t the moment i am trying to find a suitable processor core for the work. Th= ese are my requirements: > >=20 > > 1. It must have a good documentation + tools + community support > > 2. It should be mature and future proof > > 3. Better if it is Free, how ever commercial cores are OK too provided = that i have the full documentation + tool set for free to get started. > >=20 > >=20 > > Few years back i played a little with openrisc. This time too i initial= ly wanted to go with it. However documentation for openrisc seems to be ext= remely low and incomplete. Im not sure the status of tools and support, but= seems like they are lacking as well. I'd like to get some advice from expe= rt engineers about this before going forward. Also like to know about bette= r alternatives as well. >=20 > How fast do you need it? I've used NIOS, the smallest version is free. > Sometimes a bit difficult to setup a project and to use Eclipse, but > when it works, it is nice, with integrated debugger. >=20 > --=20 > Frank Buss, http://www.frank-buss.de > electronics and more: http://www.youtube.com/user/frankbuss On Sunday, April 15, 2012 9:32:18 PM UTC+5:30, Frank Buss wrote: > manusha1980@gmail.com wrote: >=20 > > after few years i want to restart FPGA development once again - initial= ly for personel fun, but later may move in to commercial development too. A= t the moment i am trying to find a suitable processor core for the work. Th= ese are my requirements: > >=20 > > 1. It must have a good documentation + tools + community support > > 2. It should be mature and future proof > > 3. Better if it is Free, how ever commercial cores are OK too provided = that i have the full documentation + tool set for free to get started. > >=20 > >=20 > > Few years back i played a little with openrisc. This time too i initial= ly wanted to go with it. However documentation for openrisc seems to be ext= remely low and incomplete. Im not sure the status of tools and support, but= seems like they are lacking as well. I'd like to get some advice from expe= rt engineers about this before going forward. Also like to know about bette= r alternatives as well. >=20 > How fast do you need it? I've used NIOS, the smallest version is free. > Sometimes a bit difficult to setup a project and to use Eclipse, but > when it works, it is nice, with integrated debugger. >=20 > --=20 > Frank Buss, http://www.frank-buss.de > electronics and more: http://www.youtube.com/user/frankbuss i'd like to have something that i can use for serious stuff, for example mp= 3 encoding/decoding, implementing neural networks, decoding movies. I start= ed out with leon2/leon3 and things have been good so far. but still interes= ted in knowing alternatives.Article: 153676
manusha1980@gmail.com wrote: > > i'd like to have something that i can use for serious stuff, for example > mp3 encoding/decoding, implementing neural networks, decoding movies. > I started out with leon2/leon3 and things have been good so far. but > still interested in knowing alternatives. If you have a low end FPGA like Cyclone, I think just a CPU imlemented in the FPGA will be too slow for things like decoding movies, but you could add FPGA logic for some tasks. With NIOS you can embed it as custom instructions, but the usual way is memory mapped. Of course, the easiest solution would be to buy a Raspberry Pi for $25 for the tasks you've mentioned, except the neural networks, which could be faster with FPGAs, because of the high parallel processing capabilities and the simple implementation of one neuron, but take a look at GPUs too for it. -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 153677
On Sun, 15 Apr 2012 09:17:23 -0700, manusha1980 wrote: > On Sunday, April 15, 2012 9:32:18 PM UTC+5:30, Frank Buss wrote: >> manusha1980@gmail.com wrote: >> >> > after few years i want to restart FPGA development once again - >> > initially for personel fun, but later may move in to commercial >> > development too. At the moment i am trying to find a suitable >> > processor core for the work. >> How fast do you need it? I've used NIOS, the smallest version is free. > i'd like to have something that i can use for serious stuff, for example > mp3 encoding/decoding, implementing neural networks, decoding movies. I > started out with leon2/leon3 and things have been good so far. but still > interested in knowing alternatives. If you're using a processor core for serious stuff, instead of using it to control the serious stuff, you're probably missing the point of an FPGA... - BrianArticle: 153678
On 15/04/2012 18:17, manusha1980@gmail.com wrote: > On Sunday, April 15, 2012 9:32:18 PM UTC+5:30, Frank Buss wrote: >> manusha1980@gmail.com wrote: >> >>> after few years i want to restart FPGA development once again - >>> initially for personel fun, but later may move in to commercial >>> development too. At the moment i am trying to find a suitable >>> processor core for the work. These are my requirements: >>> >>> 1. It must have a good documentation + tools + community support >>> 2. It should be mature and future proof 3. Better if it is Free, >>> how ever commercial cores are OK too provided that i have the >>> full documentation + tool set for free to get started. >>> >>> >>> Few years back i played a little with openrisc. This time too i >>> initially wanted to go with it. However documentation for >>> openrisc seems to be extremely low and incomplete. Im not sure >>> the status of tools and support, but seems like they are lacking >>> as well. I'd like to get some advice from expert engineers about >>> this before going forward. Also like to know about better >>> alternatives as well. >> >> How fast do you need it? I've used NIOS, the smallest version is >> free. Sometimes a bit difficult to setup a project and to use >> Eclipse, but when it works, it is nice, with integrated debugger. >> > i'd like to have something that i can use for serious stuff, for > example mp3 encoding/decoding, implementing neural networks, decoding > movies. I started out with leon2/leon3 and things have been good so > far. but still interested in knowing alternatives. You can use a NIOS for serious stuff - you are not going to get anything significantly faster in an FPGA soft core (I expect Xilinx's soft core is similar). MP3 encoding/decoding is not /that/ demanding. Neural networks, of course, scale from something that can run on a tiny microcontroller to networks that take forever to run on the biggest supercomputer, so they are a useless example. Decoding video is not going to run in software on a 150/200 MHz processor - you do the hard work in the FPGA itself. The trick here is to bind it well with the NIOS - perhaps using custom instructions, or a memory-mapped peripheral. You can even use Altera's tools for turning C code into FPGA hardware. There are also some FPGA's with hard cores (PPC or ARM). These will run a lot faster, but cost a lot more.Article: 153679
On Mon, 16 Apr 2012 09:04:29 +0200 David Brown <david@westcontrol.removethisbit.com> wrote: > [snip] > > You can use a NIOS for serious stuff - you are not going to get anything > significantly faster in an FPGA soft core (I expect Xilinx's soft core > is similar). The II/s and II/f maybe. But the free II/e needs at least 6 cycles per instruction. Altera's benchmarks on it are in the 20-30 MIPS range for Cylone III, and even on a Stratix V don't get up to even 50 MIPS. Sure they're tiny, you can parallel a mess of them, but they're really meant for occasional control plane stuff rather than heavy lifting. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 153680
On 16/04/2012 19:00, Rob Gaddi wrote: > On Mon, 16 Apr 2012 09:04:29 +0200 > David Brown<david@westcontrol.removethisbit.com> wrote: > >> [snip] >> >> You can use a NIOS for serious stuff - you are not going to get anything >> significantly faster in an FPGA soft core (I expect Xilinx's soft core >> is similar). > > The II/s and II/f maybe. But the free II/e needs at least 6 cycles per > instruction. Altera's benchmarks on it are in the 20-30 MIPS range > for Cylone III, and even on a Stratix V don't get up to even 50 MIPS. > Sure they're tiny, you can parallel a mess of them, but they're really > meant for occasional control plane stuff rather than heavy lifting. > Well, yes, I was referring to the "real" Nios's - the ones designed for fast, efficient processing in a soft core, rather than the version aimed at minimal space. As you say, the II/e has its usage - but not as a fast processor.Article: 153681
Simon There is now a date confirmed for the 24th May at Arrrow Electronics offices in Theale near Reading. That should be fairly good for a lot of companies in M3/M4 corridors and even anyone that wants to fly in through Heathrow. Details of this new date should appear in the next day or so. There is a date clash between our new Altera based seminar date and our first Xilinx based equivalent seminar so we have moved the latter to 20th June now for anyone that is interested in that. John Adair Enterpoint Ltd. On Apr 5, 8:49=A0am, Simon Watson <simon.m.wat...@gmail.com> wrote: > > Details athttp://enterpoint.co.uk/main-3/seminars/and initial dates > > are at our office(or close by) in Malvern, UK in May. We are looking > > at other venues for re-runs elsewhere in the UK, Europe and the US and > > open to suggestions anywhere where we might get a sensible attendance. > > Hi John, > > Something a bit further south (London area) would be good. I would have b= een up for taking holiday to do this - but unfortunately, Malvern is a bit = too far for me to get to easily / cost effectively! > > I'd imagine you'd get a reasonable amount of interest from businesses in = the south-east as London is very easily accessible. > > Best regards, > > SimonArticle: 153682
Sign for the Altera based Reading event only is at http://www.arroweurope.com/news-events/arrow-events/detail/article/altera-i= mplementing-pcie-in-altera-fpgas.html. Other dates still booked through us directly. John Adair Enterpoint Ltd. On Apr 17, 5:04=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > Simon > > There is now a date confirmed for the 24th May at Arrrow Electronics > offices in Theale near Reading. That should be fairly good for a lot > of companies in M3/M4 corridors and even anyone that wants to fly in > through Heathrow. Details of this new date should appear in the next > day or so. > > There is a date clash between our new Altera based seminar date and > our first Xilinx based equivalent seminar so we have moved the latter > to 20th June now for anyone that is interested in that. > > John Adair > Enterpoint Ltd. > > On Apr 5, 8:49=A0am, Simon Watson <simon.m.wat...@gmail.com> wrote: > > > > > > > > > > Details athttp://enterpoint.co.uk/main-3/seminars/andinitial dates > > > are at our office(or close by) in Malvern, UK in May. We are looking > > > at other venues for re-runs elsewhere in the UK, Europe and the US an= d > > > open to suggestions anywhere where we might get a sensible attendance= . > > > Hi John, > > > Something a bit further south (London area) would be good. I would have= been up for taking holiday to do this - but unfortunately, Malvern is a bi= t too far for me to get to easily / cost effectively! > > > I'd imagine you'd get a reasonable amount of interest from businesses i= n the south-east as London is very easily accessible. > > > Best regards, > > > SimonArticle: 153683
Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be someting like the 32Bit unix timestamp. Does anybody know if there is some method to generate a timestamp during the "syntheses time" within vhdl? Target system is xilinx spartan3 / xilinx web pack regards ArneArticle: 153684
On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote: > Hello all, > > I want to implement a "build" timestamp into some FPGA Designs (like the > C __DATE__ makro). > Optimal would be someting like the 32Bit unix timestamp. > > Does anybody know if there is some method to generate a timestamp during > the "syntheses time" within vhdl? > > Target system is xilinx spartan3 / xilinx web pack > > regards > Arne I do the same thing in my projects here. I also have constants for (an auto-incrementing) build number as well as a source code management system unique tag number. The bad news is that this can't be done in native VHDL. The good news is that it's trivial to do if you script your builds (i.e. you don't use an IDE (such as the ISE GUI) to build your designs). Create a file with a package which contains the constants, e.g. package foo is constant underscore_underscore_date : integer := 0; end package foo; package body foo is end package body foo; Modify your (probably TCL) build scripts to parse this file and call a program to patch in a new value for the constant before the file gets compiled. Any scripting language would do; I use Perl for this. The autoincrementing build number is a little more complicated - the script will check out the file; read the value of the constant; increment it then check the file back in. Regards, AllanArticle: 153685
On 22/04/2012 04:28, Allan Herriman wrote: > On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote: > >> Hello all, >> >> I want to implement a "build" timestamp into some FPGA Designs (like the >> C __DATE__ makro). >> Optimal would be someting like the 32Bit unix timestamp. >> >> Does anybody know if there is some method to generate a timestamp during >> the "syntheses time" within vhdl? >> >> Target system is xilinx spartan3 / xilinx web pack >> >> regards >> Arne > > > I do the same thing in my projects here. > > I also have constants for (an auto-incrementing) build number as well as > a source code management system unique tag number. > > > The bad news is that this can't be done in native VHDL. > > The good news is that it's trivial to do if you script your builds (i.e. > you don't use an IDE (such as the ISE GUI) to build your designs). .. > > > Modify your (probably TCL) build scripts to parse this file and call a > program to patch in a new value for the constant before the file gets > compiled. Any scripting language would do; Here is a very simple ready made Tcl one: http://www.ht-lab.com/freeutils/date2hdl/date2hdl.html Good luck, Hans www.ht-lab.comArticle: 153686
thanks for you hint, > The bad news is that this can't be done in native VHDL. I have suspected something like that. > Modify your (probably TCL) build scripts to parse this file and call a > program to patch in a new value for the constant before the file gets > compiled. Any scripting language would do; I use Perl for this. For my embedded C projects I do some similar stuff, I patch a version and date structure to the binary output after compiling. So modifying a vhdl file with the needed information would not be the problem for me. Currently I am still using the ISE GUI, but I couldn't find any option to run custom a pre-build command. I am not sure that I am experienced enough with the build process to drop the GUI since I am using some IP cores and other GUI settings for my design. Is there any option to use still the GUI but run some customized programs at some point? Maybe be adding some lines to some tcl script somewhere? On the other hand I would be very attractive to have more control over the vhdl build since I always have some problems determining the files which I should put under subversion revision control. regards ArneArticle: 153687
On Sunday, April 22, 2012 11:36:05 AM UTC+3, Arne Pagel wrote: > thanks for you hint, >=20 > > The bad news is that this can't be done in native VHDL. >=20 > I have suspected something like that. >=20 > > Modify your (probably TCL) build scripts to parse this file and call a > > program to patch in a new value for the constant before the file gets > > compiled. Any scripting language would do; I use Perl for this. >=20 > For my embedded C projects I do some similar stuff, I patch a version and= date structure to the=20 > binary output after compiling. > So modifying a vhdl file with the needed information would not be the pro= blem for me. > Currently I am still using the ISE GUI, but I couldn't find any option to= run custom a pre-build=20 > command. > I am not sure that I am experienced enough with the build process to drop= the GUI since I am using=20 > some IP cores and other GUI settings for my design. >=20 > Is there any option to use still the GUI but run some customized programs= at some point? > Maybe be adding some lines to some tcl script somewhere? >=20 > On the other hand I would be very attractive to have more control over th= e vhdl build since I always=20 > have some problems determining the files which I should put under subvers= ion revision control. >=20 > regards > Arne In the past I did something similar (a date stamp not a time stamp) to this= but I was running it manually. I wrote a matlab code and I was running it = with octave through a batch file via scheduled tasks, many times in a day. = But later on I gave up using it because following a synthesis with date sta= mp was not so good for me besides it was confusing. I went on with a manual= version and an automatic build number.=20 All levels of synthesis in ISE can be run with TCL scripts so instead of us= ing ISE GUI you can run your synthesis with a script file, there are many t= utorials for doing this. Also in order to add a build number to your design simply you will write a = function doing file read operation from a build file, increment it and writ= e back again to that file and you will assign the return of the function (y= our build number) to your signal like :=20 signal build_no : std_logic_vector(15 downto 0) :=3D MyBuildNumberFunction; Assume that this assignment is done in a build.vhd file, at every synthesis= build no will increase.Article: 153688
On Sun, 22 Apr 2012 03:28:53 +0000, Allan Herriman wrote: > On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote: > >> Hello all, >> >> I want to implement a "build" timestamp into some FPGA Designs (like >> the C __DATE__ makro). >> Optimal would be someting like the 32Bit unix timestamp. >> >> Does anybody know if there is some method to generate a timestamp >> during the "syntheses time" within vhdl? >> >> Target system is xilinx spartan3 / xilinx web pack >> >> regards >> Arne > > > I do the same thing in my projects here. > > I also have constants for (an auto-incrementing) build number as well as > a source code management system unique tag number. > > > The bad news is that this can't be done in native VHDL. > > The good news is that it's trivial to do if you script your builds (i.e. > you don't use an IDE (such as the ISE GUI) to build your designs). > > Create a file with a package which contains the constants, e.g. > > > package foo is > > constant underscore_underscore_date : integer := 0; > > end package foo; > > package body foo is end package body foo; > > > Modify your (probably TCL) build scripts to parse this file and call a > program to patch in a new value for the constant before the file gets > compiled. Any scripting language would do; I use Perl for this. > > The autoincrementing build number is a little more complicated - the > script will check out the file; read the value of the constant; > increment it then check the file back in. For completeness, I should probably point out that the other way of doing this involves getting the value of your constant from a top-level generic. Many compilers (e.g. XST) allow the values of generics to be changed from the command line. This still needs scripting if you want it to be automated. Many IDEs will allow generic overrides through the GUI, but it is a manual process. Regards, AllanArticle: 153689
>On 10.04.2012 15:10, tabenash2002 wrote: >> Hallo guys, >> >> I'm pretty new to hardware programming. >> >> At the end of the day, it should be able to use a matlab script to send >> data from PC to FPGA. > >Then make your life easy: use an usb -> parallel port adapter >(like http://www.amazon.de/Parallel-Centronics-Adapter-Druckerkabel-36pol/dp/B002CP8U3U ) >and connect some of the data pins to the FPGA. A simple print in matlab to >the proper PRN port should be sufficient. > Hallo Guys, thanks alot for your contributions. I have done abit of research and i have the following information available: I will be using a Virtex-5 lx50 Evaluation board, with USB controller from Cypress. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153690
On Sat, 21 Apr 2012 22:52:22 +0200 Arne Pagel <arne@pagelnet.de> wrote: > Hello all, > > I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). > Optimal would be someting like the 32Bit unix timestamp. > > Does anybody know if there is some method to generate a timestamp during the "syntheses time" within > vhdl? > > Target system is xilinx spartan3 / xilinx web pack > > regards > Arne I've needed to do this several times, and I agree with everyone else. It can't be done in native VHDL, and probably can't be done through the GUI. For Altera, I've used Tcl to set generics in the build script. For Xilinx, I've used a Makefile to pass the result of $(date +s) as a generic on the command line. You can also use any scripting language as a part of your build process to generate a package file. Having tried all those approaches, they're all pains in the backside, and none of them could I find a way to integrate into the GUI based flow. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 153691
On 04/10/2012 06:31 PM, Herbert Kleebauer wrote: > On 10.04.2012 15:10, tabenash2002 wrote: >> Hallo guys, >> >> I'm pretty new to hardware programming. >> >> At the end of the day, it should be able to use a matlab script to send >> data from PC to FPGA. > > Then make your life easy: use an usb -> parallel port adapter > (like http://www.amazon.de/Parallel-Centronics-Adapter-Druckerkabel-36pol/dp/B002CP8U3U ) > and connect some of the data pins to the FPGA. A simple print in matlab to > the proper PRN port should be sufficient. Herbert, The simplicity of this solution is brilliant! Yours sincerely, ReneArticle: 153692
Hello, The information that I find about hard macros is a little bit terse. What I= am missing mainly is how to get to a hard macro. This is nowhere specified= . Does one start from a simple VHDL design to obtain a hard macro? What I mainly need is a small component with some inputs and outputs, to wh= ich I can join another component (if you did not guess, this is about dynam= ic partial reconfiguration). It seems that I need the following: - An ISE project consisting of an embedded design (got that, and floorplann= ed too) and this component to which I can connect clock, reset, switches an= d LEDs. - This component in a separate design - This component combined with logic blocks which connect to the signal del= ivered by the macro. - The possibility to create a differential bitstream from the macro and the= (macro + logic block) Is a bus macro then a combination of LUTs which just pass signals through? Btw. I found a whole lot of papers about reconfiguration, but most of them = seemed more to be about architectures on how to reconfigure, not on the pra= ctical issue of generating bitstream contents for reconfiguration. It seems= that the research with the most practical result is done at the University= of Oslo. I will certainly try GoAhead, but in the meantime I also want to = know the hard way. Regards, JurgenArticle: 153693
From customer demand we are doing a cut down Merrick6 with only 2 way array XC6SLX150 FPGAs (without DDR fitted in array) plus the XC6SLX150T that controls the everything on the board. This new board variant is on introductory offer of $1,000 until the end of June. John Adair Enterpoint Ltd.Article: 153694
On Apr 24, 3:08=A0am, Rene <a...@b.c> wrote: > On 04/10/2012 06:31 PM, Herbert Kleebauer wrote: > > > On 10.04.2012 15:10, tabenash2002 wrote: > >> Hallo guys, > > >> I'm pretty new to hardware programming. > > >> At the end of the day, it should be able to use a matlab script to sen= d > >> data from PC to FPGA. > > > Then make your life easy: use an usb -> =A0parallel port adapter > > (likehttp://www.amazon.de/Parallel-Centronics-Adapter-Druckerkabel-36po= l/d...) > > and connect some of the data pins to the FPGA. A simple print in matlab= to > > the proper PRN port should be sufficient. > > Herbert, > > The simplicity of this solution is brilliant! > > Yours sincerely, > Rene My understanding is that the old parallel printer port is a 5V signalling standard and apply this to a modern FPGA will result in damage. Ed McGettigan -- Xilinx Inc.Article: 153695
Hi, I wanted to know if there's any simulator like proteus for FPGAs, like where we can have a FPGA interfaced with some other ICs or LCD etc and without implementing it on hardware, we can see the output on simulator. Like in proteus we can have different microcontrollers, LCDs and other ICs, and see if our code is working properly. Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153696
On Wed, 25 Apr 2012 00:14:40 -0500 "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I wanted to know if there's any simulator like proteus for FPGAs, like > where we can have a FPGA interfaced with some other ICs or LCD etc and > without implementing it on hardware, we can see the output on simulator. > Like in proteus we can have different microcontrollers, LCDs and other ICs, > and see if our code is working properly. > > Regards > > --------------------------------------- > Posted through http://www.FPGARelated.com Yes, you build simulation models of the other hardware on the board in VHDL (or Verilog) and run it through your usual simulator. I generally have ADCs and DACs using real as the analog voltage, and LCD panels using string as the display. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 153697
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http://indiasolo.com/46/king004/Article: 153699
Am Mittwoch, 25. April 2012 07:14:40 UTC+2 schrieb salimbaba: > Hi, > I wanted to know if there's any simulator like proteus for FPGAs, like > where we can have a FPGA interfaced with some other ICs or LCD etc and > without implementing it on hardware, we can see the output on simulator. > Like in proteus we can have different microcontrollers, LCDs and other ICs, > and see if our code is working properly. > > Regards > > --------------------------------------- > Posted through http://www.FPGARelated.com Hi, almost any HDL simulator can do board level simulation, provided you have models for the stuff you want to attach to your FPGA. Here's a site where you can find a number of simulation models to begin with: http://www.freemodelfoundry.com Sometimes IC vendors provide you with simulation models of their devices too. Also some EDA vendors have collections of simulation models, but they want to be paid of course (e.g. Synopsys smartmodels) Have a nice simulation Eilert
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