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I's hard to say what's wrong, you may try these: 1) Test it with different brands/sizes HDDs 2) If I remember corectly, you may need to use the WriteDMAExt. (48 bit addressing) 3) A Maxtor HDD spec. also help 4) It sounds like the address was truncated/ or wrapped aroundArticle: 84951
"Joey" <johnsons@kaiserslautern.de> wrote in message news:d7kpmg$m53$2@news.uni-kl.de... > > You can just make use of pointers and thats easy enough, isn't it? > > "Marco" <marcotoschi_no_spam@email.it> schrieb im Newsbeitrag > news:d7kfc5$fup$1@news.ngi.it... > > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > > news:newscache$w5ndhi$t3a$1@lbox.itee.uq.edu.au... > > > Hi Marco, > > > > > > Marco wrote: > > > > Which C function should I use to perform read or write into block ram > > (connected to opb bus with opb bus controller)? > > > > > > > > Xio_in8 and Xio_out8 ? > > > > > > Not necessary - just read and write it like normal memory. > > > > > > Regards, > > > > > > John > > > > > > Could you explain, please? > > > > Normally, when I write a C program, I create variables... and everything > is > > stored in memory, but it is implicit. > > > > So, what sohuld I do to read or write into memory? In what way may I > save, > > in example a matrix into block ram? > > > > Thanks > > Marco > > > > > > I can use C pointers to point to address space mapped from microblaze?Article: 84952
> For example use "register" variables/keywords , > compute commonly used variables before hand and so on and at the end we got > a satisfactory computational speed. With GCC there should be no need for this. Was you compiling with optimisation switched on (-O2)? Cheers, JonArticle: 84953
Hi, I have this ...%#$%#$% commodore=one. Recently it (auto)started an "emergency" flash procecure.. It halted (CRC error) now its dead.. Anyway, there is a program called c1-flasher (by Mr Lukats) but this program produces errors under the XP. (access violation ar address 0000000000 read of address 00000000000). Any ideas? On my c-1 there is a JTAG, I think I have to make a byteblaster cable and connect this to this JTAG connector.. As I know nothing about this, I supposed that I must have the c-one powered on? I will appreciate ANY help. Regards Chris SYNTICHAKISArticle: 84954
I am developing a Xlinx Virtex 4 FPGA system and require to change a pcore frequently during the development phase. Whenever I modify the pcore, I have to clean the netlist in EDK and resynthesize/reroute the entire hardware design. This takes a lot of time. Is there any way to just synthesize/place 'n route the modified pcore as opposed to the entire hardware design.Article: 84955
"Chris S" <csynt@YAH00.c0m> schrieb im Newsbeitrag news:BEC3E841.7EE%csynt@YAH00.c0m... > Hi, > I have this ...%#$%#$% commodore=one. > Recently it (auto)started an "emergency" flash procecure.. > It halted (CRC error) now its dead.. > > Anyway, there is a program called c1-flasher (by Mr Lukats) but this program > produces errors under the XP. (access violation ar address 0000000000 read > of address 00000000000). > > Any ideas? > > On my c-1 there is a JTAG, I think I have to make a byteblaster cable and > connect this to this JTAG connector.. > As I know nothing about this, I supposed that I must have the c-one powered > on? > > I will appreciate ANY help. > > Regards > > Chris SYNTICHAKIS > Hi Chris sorry I have not been able to help, the issue is a bit more complex as the flash is connected to devices that are not on the JTAG chain, so the process is very weird, I use the 2 PLDs in EXTEST mode to download a small ip core into the ACEX, then I again use EXTEST on the PLD to flash the rom, it works, worked... but at the moment I am just too tired working hours from 05:40 to 23:56 are not so fun, I am not promising to help as (too tired) my c1-flasher did work, but has never been tested with XP SP2 I think anttiArticle: 84956
Kishore, Usual i test the FPGA by writing test program such as LED test...If you have an LED on board which is connect to FPGA why not use a counter and switch on and off the LED. PraveenArticle: 84957
You can specify in the MPD of pcore under development. OPTION CORE_STATE = DEVELOPMENT This forces platgen to re-synthesize the pcore on ever iteration. So, need to clean. For place-route, you'll need to follow the documents regarding incremental place-route. http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/dev/dev0018_6.html You can skip the setup for incremental synthesis as this is handled by platgen in a bottom-up synthesis flow. Kunal wrote: > I am developing a Xlinx Virtex 4 FPGA system and require to change a > pcore frequently during the development phase. Whenever I modify the > pcore, I have to clean the netlist in EDK and resynthesize/reroute the > entire hardware design. This takes a lot of time. > Is there any way to just synthesize/place 'n route the modified pcore > as opposed to the entire hardware design. >Article: 84958
Hi, I am developing the firmware for a development system. Ths system has the 8051 chip and spartan3. 8051 has its PORTC(0, 1, 2) connect to TDMI, TCK and TMS of SP3. 8051 read a file through USB and generate wavefomr of JTAG control singals. Since we are not going to verifiy and the JTAG TCK is fairly slow, we do not use TDO and TDO just has a 4.7K pullup and has no other signal conncet to it. The download file is generate by: - using IMPACT to generat the XVF file - using xvf2xsvf502.exe to generate XSVF file - using XPLAY to generate a TDI/TMS bit stream file from XSVF. XPLAY is ued to drive the printer port, I just monitor the bit send to print port and save it into a data file. Question is: - is the new version of xvf2xsvf502 support spartan3? Or it is a generic tool and should support all? - XSVF file can be generated directly from IMPACT, comparing the file size of the XSVF generated with xvf2xsvf502 and the one directly generated by IMPACT, I can see the file size is different. So any reason? - since the board also has a JTAG connector, so I can download the bit map using IMPACT directly. This works fine. But when I take the data file converted from xsvf file and download FPGA through 8051, it does not finish correctly (the done signal of SP3 will not go up). I am pretty new to FPGA development. Your suggest is appreciate. thanks in advance, frankArticle: 84959
Hi, xsvf file can be generate by IMPACT directly, andalso can be generated by svf2xsvf502 from XVF file. So what is the difference betwwen these two approach? I saw the xsvf file size is different. thanks, frankArticle: 84960
Cacheline and bursts are two different type of transactions. The processor can only generate single word, four word cacheline, and eight word cacheline transactions but not burst transactions. Eight word cacheline transactions are generated for memory areas that are cacheable. Four word cacheline transactions are generated for non-cacheable memory on the instruction side. Single word transactions are generated for non-cacheable memory on the data side. Now, as for the data width - it depends. If your peripheral is on the PLB it can be either 32 bits or 64 bits wide. If your peripheral is on the OPB it has to be 32 bits wide. In any case you need to make sure that during the data phase the wdaddr input signals on the PLB are created correctly. Otherwise the processor will hang waiting for the transaction to complete and deliver data to all four words. The PPC405 processor block reference guide explains the different transaction types and the signals on the PPC core. - PeterArticle: 84961
Kunal wrote: > I am developing a Xlinx Virtex 4 FPGA system and require to change a > pcore frequently during the development phase. Whenever I modify the > pcore, I have to clean the netlist in EDK and resynthesize/reroute the > entire hardware design. This takes a lot of time. > Is there any way to just synthesize/place 'n route the modified pcore > as opposed to the entire hardware design. > As an alternative to the "official" method mentioned by Paulo, another way to trigger a recompile of a single core is to do: rm -f implementation/my_core.ngc rm -f implementation/cache/my_core.ngc Those are Unix(Linux) commands, but I am sure something similar exists under Windows ;) If you are really ambitious, you can modify the makefiles so that this step is automatically handled by the make system whenever a source file changes. For example, I have a added to system_incl.make: MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \ ... (additional files deleted) MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc MY_DIMM_FILES = pcores/plb_dimm_v1_11_a/hdl/vhdl/clock_gen.vhd \ ... (additional files deleted) MY_REGS_IMPLN = implementation/my_regs_wrapper.ngc MY_REGS_FILES = pcores/plb_regs_v1_00_a/hdl/vhdl/regs_core.vhd \ pcores/plb_regs_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \ pcores/plb_regs_v1_00_a/hdl/vhdl/plb_regs.vhd \ pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.mpd \ pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.pao MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \ $(MY_DIMM_IMPLN) $(MY_BITS_IMPLN) MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \ $(MY_DIMM_FILES) $(MY_REGS_FILES) And then to system.make I have inserted: ################################################################# # HARDWARE IMPLEMENTATION FLOW ################################################################# $(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES) rm -f implementation/my_ddr_clocks_wrapper.ngc rm -f implementation/cache/my_ddr_clocks_wrapper.ngc $(MY_DIMM_IMPLN): $(MY_DIMM_FILES) rm -f implementation/my_dimm_wrapper.ngc rm -f implementation/cache/my_dimm_wrapper.ngc $(MY_REGS_IMPLN): $(MY_REGS_FILES) rm -f implementation/my_regs_wrapper.ngc rm -f implementation/cache/my_regs_wrapper.ngc implementation/$(SYSTEM).bmm \ $(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ ...Article: 84962
The xparameters.h, other include files, and libraries are based on the driver selected for that peripheral. In XPS, select Project->Software Platform Settings (or double click on the processor in the System tab) and assign a driver to the opb_spi. You can select between none, spi, and generic. I would recommend selecting spi. As Duane Clark pointed out you can also manually add the spi driver to your [project name].mss file. There is no problem with manually adding IPs to the .mhs file, but if you want to use their driver one must also add it to the .mss file. Tip: One can assign the default drivers to all the IP in the system by selecting Project->Assign Default Drivers. "ARRON" <mlpei279@gmail.com> wrote in message news:ee8e9e2.-1@webx.sUN8CHnE... > I have added the opb_spi core in my project,I can assure the opb_spi have been inserted in the project(because i can find the synthesise and implemention file of opb_spi).But i can't find any parameter about opb_spi in the xparameters.h,and can't the head file in the directory of PPC405_0/libsrc or PPC405_0/include, what is wrong?Article: 84963
At president I am doing some projects with EDK 6.3i on Virtex-II Pro under Windows XP OS. I want to use the GCC compiler, so I want to know how to get it, how to install it, how to start it and so on. Who has the related reference? Please help me£¡ Thank you! AthenaArticle: 84964
hello,everyone.I always build my project and compile it in EDK,but now i want to compile my project in gcc,who can tell me the process of compile the project step by step, thanks a lot!!!!Article: 84965
I am very glad to see so many discussions. Thank you!
At present I am using the PowerPC, because its bram is 128K, but the bram of microblze(64K) is not enough for us to run our programme. This is another problem.
About GCC£¬ I don't quite understand about Jon's meaning. I am just using the integrated tool EDK under Windows XP to "build the project", "update the bitstream", then I can get the file "download.bit", so I am not familiar with the command interface GCC, then how to start the GCC under EDK, is it the ¡°tools->software debugger¡±? How to compile with optimisation switched on (-O2)?
Lina
----------the former discussions----
How to speed up float computing
lina - 12:54am Jun 1, 2005 PST Guest User
Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50. There are many math computing in the program, and I do them using the software libs provided by the board, as a result, it is very very slow that we could not endure. So I would like to know the effective and simple method to speed up the float computing. Please help me. Thank you very much.
Jon Beniston - 01:55am Jun 1, 2005 PST (#1 of 5) Guest User
Get EDK 7.1, which has support for h/w floating point.
lina - 04:14am Jun 1, 2005 PST (#2 of 5)
Thank you very much for your answer! We will try it.
Ben Jones - 08:34am Jun 1, 2005 PST (#3 of 5) Guest User
Hi Lina,
"Jon Beniston" <jon@beniston.com> wrote in message news:1117616106.265895.110170@g43g2000cwa.googlegroups.com...
Get EDK 7.1, which has support for h/w floating point.
Just to clarify - this is almost but not quite true. If your code is running on MicroBlaze, then the new EDK does indeed include support for a floating-point unit in the FPGA fabric. If you are using the PowerPC (and since you're using V2-Pro, I suspect you probably are), then it doesn't.
I can suggest a few options:
1) Use a Microblaze core with FPU, either for your whole application or to accelerate those algorithms which use floating point arithmetic; 2) Get a PowerPC floating-point unit, for example:
<http://www.qinetiq.co.uk/home_rtes/quixilica_products/firmware_cores/quixili> ca_fpu_ppc.html
3) Consider moving to Virtex-4 FX, which will soon have a PowerPC floating-point unit available.
Hope this helps,
-Ben-
Joey - 10:01am Jun 1, 2005 PST (#4 of 5) Guest User
Hi Lina
I was also experiencing the same problems. Infact the computation was taking such a long time. At the end what we did was rewrite the whole program with very less computations. For example use "register" variables/keywords , compute commonly used variables before hand and so on and at the end we got a satisfactory computational speed. One more hint: Put the instructions in the ISOCM memory and dont use any Instruction side cache memory !! The results which I got were more than 10 times better Joe
"lina" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag news:ee8e9cb.-1@webx.sUN8CHnE...
Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50.
There are many math computing in the program, and I do them using the
software libs provided by the board, as a result, it is very very slow
that we could not endure. So I would like to know the effective and simple
method to speed up the float computing. Please help me. Thank you very
much.
Jon Beniston - 11:55am Jun 1, 2005 PST (#5 of 5) Guest User
For example use "register" variables/keywords , compute commonly used
variables before hand and so on and at the end we got a satisfactory computational
speed.
With GCC there should be no need for this. Was you compiling with optimisation switched on (-O2)?
Cheers, Jon
Article: 84966For more information on the Incremental Compilation feature in Quartus II 5.0, refer this chapter in the Quartus II handbook - http://www.altera.com/literature/hb/qts/qts_qii51015.pdf Seshan seshans@altera.comArticle: 84967
Athena wrote: > At president I am doing some projects with EDK 6.3i on Virtex-II Pro under Windows XP OS. I want to use the GCC compiler, so I want to know how to get it, > > how to install it, > > how to start it and so on. Who has the related reference? Please help me£¡ > > Thank you! Athena EDK 6.3i comes with a gnu tool chain (containing gcc). You can access it through EDK's xygwin shell. The command is powerpc-eabi-gcc. The official gnu gcc manual can be found at http://gcc.gnu.org/onlinedocs/gcc-3.4.3/gcc/ (This is version 3.4.3, pretty close to the one supplied by xilinx) For linking to EDK-built libraries, see the following Makefile: #begin code CC = powerpc-eabi-gcc BSP = /home/hzheng/work/smctest LINKSCR = $(BSP)/TestApp/src/TestAppLinkScr LINKARGS = -Wl,-T -Wl,$(LINKSCR) I = -I$(BSP)/ppc405_0/include L = -L$(BSP)/ppc405_0/lib CFLAGS += $(I) -O2 SMCFILES = main.o xil_printf.o all: $(SMCFILES) $(CC) $(L) $(LINKARGS) -o executable.elf $(SMCFILES) clean: rm -f *.o; rm -f executable.elf #end code Alternatively, you could try to make your own tool chain, but it's quite complicated, especially if you build it on cygwin under windows.Article: 84968
Under Windows, the simplest way to get GCC is to install cygwin (http://www.cygwin.com).Just click on download and follow the instructions. (There is also a Mingw version, but Cygin is significantly easier to set up.) Once cygwin is installed, run the bash shell. At the prompt, type startx & and a xwindow terminal shell will appear, and you can get at emacs and GCC. If emacs is (*shudder*) too primitive for you, download (under regular windows), eclipse (http://www.eclipse.org) and the CDT extensions. This will give you a highly sophisticated IDE that can compile using Cygwins GCC. The way I run it is at the xwindow shell, change directory to /cygdrive/c/eclipse (which is another name for C:\eclipse) and run ./eclipse & Eclipse will run as a regular windows program, but it will automatically use Cygwins GCC Managed C++ projects will customize the makefile for you, whereas the unmanaged projects will let you do the makefile. Eclipse CDT is a lot easier to use than Visual Studio C++.NET. Using a JNI bridge, you can also toss in Eclipse's incredible GUI and graphical editing toolkits to create your front end. You can also get kdevelop,et all by getting Cygwin KDE, but in my experience, eclipse CDT is still a better choice. On the other hand, you can also dual boot Linux, since all Linuxes have a GCC development enironment. Mandrake is the easiest Linuxfor a beginner. Fedora Core is probably the most popular, but if you plan to go corporate, Tao (among others) Linux is an OS version of RedHat Enterprise Linux and usually is 100% compatible (an important point if you want to play with any commercial Linux products, which are notoriously incompatible with FOSS Linux distributions) Athena wrote: > At president I am doing some projects with EDK 6.3i on Virtex-II Pro unde= r Windows XP OS. I want to use the GCC compiler, so I want to know how to g= et it, > > how to install it, > > how to start it and so on. Who has the related reference? Please help me= =A3=A1 >=20 > Thank you! AthenaArticle: 84969
Hi I am using Spartan-3 fpga I need to generate 35.328 MHz clock I have an external xtal of 35.328 MHz feeding to FPGA. From this clock i need to generate 35.328 MHz square wave with fine resolution. We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution. I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept. Is there any-other way out ? ( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices. So i thought of using FPGA for this purpose as an alternative solution. ) Thanks bijoyArticle: 84970
Hi, MicroBlaze can use as much BRAM as you have in the FPGA and is not limited to 64kbyte. PowerPC is a more powerful processor than MicroBlaze but both uses the same BRAM within the FPGA. The new FPU on MicroBlaze is accelerating floating-point operations with many magnitudes and is included for free in EDK. Göran lina wrote: > I am very glad to see so many discussions. Thank you! > > At present I am using the PowerPC, because its bram is 128K, but the bram of microblze(64K) is not enough for us to run our programme. This is another problem. > > About GCC£¬ I don't quite understand about Jon's meaning. I am just using the integrated tool EDK under Windows XP to "build the project", "update the bitstream", then I can get the file "download.bit", so I am not familiar with the command interface GCC, then how to start the GCC under EDK, is it the ¡°tools->software debugger¡±? How to compile with optimisation switched on (-O2)? > > Lina > > > > ----------the former discussions---- > > How to speed up float computing > > lina - 12:54am Jun 1, 2005 PST Guest User > > Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50. There are many math computing in the program, and I do them using the software libs provided by the board, as a result, it is very very slow that we could not endure. So I would like to know the effective and simple method to speed up the float computing. Please help me. Thank you very much. > > > > Jon Beniston - 01:55am Jun 1, 2005 PST (#1 of 5) Guest User > > Get EDK 7.1, which has support for h/w floating point. > > lina - 04:14am Jun 1, 2005 PST (#2 of 5) > > Thank you very much for your answer! We will try it. > > Ben Jones - 08:34am Jun 1, 2005 PST (#3 of 5) Guest User > > Hi Lina, > > "Jon Beniston" <jon@beniston.com> wrote in message news:1117616106.265895.110170@g43g2000cwa.googlegroups.com... > > Get EDK 7.1, which has support for h/w floating point. > > > > > Just to clarify - this is almost but not quite true. If your code is running on MicroBlaze, then the new EDK does indeed include support for a floating-point unit in the FPGA fabric. If you are using the PowerPC (and since you're using V2-Pro, I suspect you probably are), then it doesn't. > > I can suggest a few options: > > 1) Use a Microblaze core with FPU, either for your whole application or to accelerate those algorithms which use floating point arithmetic; 2) Get a PowerPC floating-point unit, for example: > > <http://www.qinetiq.co.uk/home_rtes/quixilica_products/firmware_cores/quixili> ca_fpu_ppc.html > > 3) Consider moving to Virtex-4 FX, which will soon have a PowerPC floating-point unit available. > > Hope this helps, > > -Ben- > > Joey - 10:01am Jun 1, 2005 PST (#4 of 5) Guest User > > Hi Lina > > I was also experiencing the same problems. Infact the computation was taking such a long time. At the end what we did was rewrite the whole program with very less computations. For example use "register" variables/keywords , compute commonly used variables before hand and so on and at the end we got a satisfactory computational speed. One more hint: Put the instructions in the ISOCM memory and dont use any Instruction side cache memory !! The results which I got were more than 10 times better Joe > > "lina" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag news:ee8e9cb.-1@webx.sUN8CHnE... > > Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50. > There are many math computing in the program, and I do them using the > software libs provided by the board, as a result, it is very very slow > that we could not endure. So I would like to know the effective and simple > method to speed up the float computing. Please help me. Thank you very > much. > > > > > Jon Beniston - 11:55am Jun 1, 2005 PST (#5 of 5) Guest User > > For example use "register" variables/keywords , compute commonly used > variables before hand and so on and at the end we got a satisfactory computational > speed. > > > > > With GCC there should be no need for this. Was you compiling with optimisation switched on (-O2)? > > Cheers, JonArticle: 84971
Just prepare any projects which deal with the issues and run an implementation flow. Then Xilinx software give you the answer. krzysztof U¿ytkownik "Yttrium" <Yttrium@pandora.be> napisa³ w wiadomo¶ci news:Qz2ne.106661$k57.6462564@phobos.telenet-ops.be... > Hey, > > I have to start a V4 design and am looking through a datasheet and i was > wondering if you can connect a regional clk to a DCM (if in a nearby > regional clk domain)? or even through logic? > > kind regards, > > Y > >Article: 84972
Hi Folks,
Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI)
using AMBA AHB/APB 2.0 Specification?? Your help will be greatly
appreciated.
Article: 84973John Larkin wrote: [...] >>> True power is just the product of the e*i samples, lowpass >>> filtered. Easy. >> Isn't that Volt-Amperes? You need the phase angle to separate the >> components into true power and reactive power. > VA would be the product of the RMS-averaged voltage and current > values, which throws away phase information. The average of the > instantaneous e/i sample pairs is true power, just as if you'd > used an analog multiplier to calculate power. Good explanation - thanks. >>> What's tricky is the reactive power/phase angle thing. >> Can't you just detect the zero crossings in the voltage and >> current waveforms and get the phase angle between them? > No, because I only have the digitized samples, and because the > current waveform has a huge dynamic range and might be very ugly. > The voltage waveform in a power system is usually pretty close to > a clean sine. > John Yes, the current waveform could be difficult, especially with rectifier loads feeding capacitors. The peak current can be enormous. I couldn't find any references that discuss this, but you can see the peaks of the AC waveform are flattened because of it. I did come across an article that discusses different methods of measuring reactive power. One method is to shift the voltage waveform 90 degrees in software. Another method used in the Analog Devices E77xx series is the phase shift of a simple rc filter. This would certainly cause errors with short current spikes such as DC power supplies. Here's the url: http://www.metering.com/archive/021/52_1.htm Looks like you are going to have fun:) Mike MonettArticle: 84974
Adding opb_spi through ADD/EDIT CORE is correct, and the opb_spi has drivers in the MSS file,which is 1.00.b, i am confused for this problem.
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